drivers/clk/imx/clk-gate2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
   4  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   5  *
   6  * Gated clock implementation
   7  */
   8
   9 #include <linux/clk-provider.h>
  10 #include <linux/module.h>
  11 #include <linux/slab.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/string.h>
  15 #include "clk.h"
  16
  17 /**
  18  * DOC: basic gatable clock which can gate and ungate it's ouput
  19  *
  20  * Traits of this clock:
  21  * prepare - clk_(un)prepare only ensures parent is (un)prepared
  22  * enable - clk_enable and clk_disable are functional & control gating
  23  * rate - inherits rate from parent.  No clk_set_rate support
  24  * parent - fixed parent.  No clk_set_parent support
  25  */
  26
  27 struct clk_gate2 {
  28         struct clk_hw hw;
  29         void __iomem    *reg;
  30         u8              bit_idx;
  31         u8              cgr_val;
  32         u8              flags;
  33         spinlock_t      *lock;
  34         unsigned int    *share_count;
  35 };
  36
  37 #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
  38
  39 static int clk_gate2_enable(struct clk_hw *hw)
  40 {
  41         struct clk_gate2 *gate = to_clk_gate2(hw);
  42         u32 reg;
  43         unsigned long flags;
  44         int ret = 0;
  45
  46         spin_lock_irqsave(gate->lock, flags);
  47
  48         if (gate->share_count && (*gate->share_count)++ > 0)
  49                 goto out;
  50
  51         if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
  52                 ret = clk_gate_ops.enable(hw);
  53         } else {
  54                 reg = readl(gate->reg);
  55                 reg &= ~(3 << gate->bit_idx);
  56                 reg |= gate->cgr_val << gate->bit_idx;
  57                 writel(reg, gate->reg);
  58         }
  59
  60 out:
  61         spin_unlock_irqrestore(gate->lock, flags);
  62
  63         return ret;
  64 }
  65
  66 static void clk_gate2_disable(struct clk_hw *hw)
  67 {
  68         struct clk_gate2 *gate = to_clk_gate2(hw);
  69         u32 reg;
  70         unsigned long flags;
  71
  72         spin_lock_irqsave(gate->lock, flags);
  73
  74         if (gate->share_count) {
  75                 if (WARN_ON(*gate->share_count == 0))
  76                         goto out;
  77                 else if (--(*gate->share_count) > 0)
  78                         goto out;
  79         }
  80
  81         if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
  82                 clk_gate_ops.disable(hw);
  83         } else {
  84                 reg = readl(gate->reg);
  85                 reg &= ~(3 << gate->bit_idx);
  86                 writel(reg, gate->reg);
  87         }
  88
  89 out:
  90         spin_unlock_irqrestore(gate->lock, flags);
  91 }
  92
  93 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
  94 {
  95         u32 val = readl(reg);
  96
  97         if (((val >> bit_idx) & 1) == 1)
  98                 return 1;
  99
 100         return 0;
 101 }
 102
 103 static int clk_gate2_is_enabled(struct clk_hw *hw)
 104 {
 105         struct clk_gate2 *gate = to_clk_gate2(hw);
 106
 107         if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
 108                 return clk_gate_ops.is_enabled(hw);
 109
 110         return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
 111 }
 112
 113 static void clk_gate2_disable_unused(struct clk_hw *hw)
 114 {
 115         struct clk_gate2 *gate = to_clk_gate2(hw);
 116         unsigned long flags;
 117         u32 reg;
 118
 119         if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
 120                 return;
 121
 122         spin_lock_irqsave(gate->lock, flags);
 123
 124         if (!gate->share_count || *gate->share_count == 0) {
 125                 reg = readl(gate->reg);
 126                 reg &= ~(3 << gate->bit_idx);
 127                 writel(reg, gate->reg);
 128         }
 129
 130         spin_unlock_irqrestore(gate->lock, flags);
 131 }
 132
 133 static const struct clk_ops clk_gate2_ops = {
 134         .enable = clk_gate2_enable,
 135         .disable = clk_gate2_disable,
 136         .disable_unused = clk_gate2_disable_unused,
 137         .is_enabled = clk_gate2_is_enabled,
 138 };
 139
 140 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
 141                 const char *parent_name, unsigned long flags,
 142                 void __iomem *reg, u8 bit_idx, u8 cgr_val,
 143                 u8 clk_gate2_flags, spinlock_t *lock,
 144                 unsigned int *share_count)
 145 {
 146         struct clk_gate2 *gate;
 147         struct clk_hw *hw;
 148         struct clk_init_data init;
 149         int ret;
 150
 151         gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
 152         if (!gate)
 153                 return ERR_PTR(-ENOMEM);
 154
 155         /* struct clk_gate2 assignments */
 156         gate->reg = reg;
 157         gate->bit_idx = bit_idx;
 158         gate->cgr_val = cgr_val;
 159         gate->flags = clk_gate2_flags;
 160         gate->lock = lock;
 161         gate->share_count = share_count;
 162
 163         init.name = name;
 164         init.ops = &clk_gate2_ops;
 165         init.flags = flags;
 166         init.parent_names = parent_name ? &parent_name : NULL;
 167         init.num_parents = parent_name ? 1 : 0;
 168
 169         gate->hw.init = &init;
 170         hw = &gate->hw;
 171
 172         ret = clk_hw_register(dev, hw);
 173         if (ret) {
 174                 kfree(gate);
 175                 return ERR_PTR(ret);
 176         }
 177
 178         return hw;
 179 }