1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the fractional plls found in the imx8m SOCs
7 * Documentation for this fractional pll can be found at:
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
12 #include <linux/err.h>
13 #include <linux/export.h>
15 #include <linux/iopoll.h>
16 #include <linux/slab.h>
17 #include <linux/bitfield.h>
24 #define PLL_LOCK_STATUS BIT(31)
25 #define PLL_PD_MASK BIT(19)
26 #define PLL_BYPASS_MASK BIT(14)
27 #define PLL_NEWDIV_VAL BIT(12)
28 #define PLL_NEWDIV_ACK BIT(11)
29 #define PLL_FRAC_DIV_MASK GENMASK(30, 7)
30 #define PLL_INT_DIV_MASK GENMASK(6, 0)
31 #define PLL_OUTPUT_DIV_MASK GENMASK(4, 0)
32 #define PLL_FRAC_DENOM 0x1000000
34 #define PLL_FRAC_LOCK_TIMEOUT 10000
35 #define PLL_FRAC_ACK_TIMEOUT 500000
42 #define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw)
44 static int clk_wait_lock(struct clk_frac_pll *pll)
48 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
49 PLL_FRAC_LOCK_TIMEOUT);
52 static int clk_wait_ack(struct clk_frac_pll *pll)
56 /* return directly if the pll is in powerdown or in bypass */
57 if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
60 /* Wait for the pll's divfi and divff to be reloaded */
61 return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
62 PLL_FRAC_ACK_TIMEOUT);
65 static int clk_pll_prepare(struct clk_hw *hw)
67 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
70 val = readl_relaxed(pll->base + PLL_CFG0);
72 writel_relaxed(val, pll->base + PLL_CFG0);
74 return clk_wait_lock(pll);
77 static void clk_pll_unprepare(struct clk_hw *hw)
79 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
82 val = readl_relaxed(pll->base + PLL_CFG0);
84 writel_relaxed(val, pll->base + PLL_CFG0);
87 static int clk_pll_is_prepared(struct clk_hw *hw)
89 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
92 val = readl_relaxed(pll->base + PLL_CFG0);
93 return (val & PLL_PD_MASK) ? 0 : 1;
96 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
97 unsigned long parent_rate)
99 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
100 u32 val, divff, divfi, divq;
101 u64 temp64 = parent_rate;
104 val = readl_relaxed(pll->base + PLL_CFG0);
105 divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2;
106 val = readl_relaxed(pll->base + PLL_CFG1);
107 divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
108 divfi = FIELD_GET(PLL_INT_DIV_MASK, val);
112 do_div(temp64, PLL_FRAC_DENOM);
113 do_div(temp64, divq);
115 rate = parent_rate * 8 * (divfi + 1);
122 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
123 unsigned long *prate)
125 u64 parent_rate = *prate;
132 do_div(temp64, parent_rate);
134 temp64 = rate - divfi * parent_rate;
135 temp64 *= PLL_FRAC_DENOM;
136 do_div(temp64, parent_rate);
139 temp64 = parent_rate;
141 do_div(temp64, PLL_FRAC_DENOM);
143 rate = parent_rate * divfi + temp64;
149 * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
150 * (means the PLL output will be divided by 2). So the PLL output can use
152 * pllout = parent_rate * 8 / 2 * DIVF_VAL;
153 * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
155 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
156 unsigned long parent_rate)
158 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
159 u32 val, divfi, divff;
165 divfi = rate / parent_rate;
166 temp64 = parent_rate * divfi;
167 temp64 = rate - temp64;
168 temp64 *= PLL_FRAC_DENOM;
169 do_div(temp64, parent_rate);
172 val = readl_relaxed(pll->base + PLL_CFG1);
173 val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
174 val |= (divff << 7) | (divfi - 1);
175 writel_relaxed(val, pll->base + PLL_CFG1);
177 val = readl_relaxed(pll->base + PLL_CFG0);
179 writel_relaxed(val, pll->base + PLL_CFG0);
181 /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
182 val = readl_relaxed(pll->base + PLL_CFG0);
183 val |= PLL_NEWDIV_VAL;
184 writel_relaxed(val, pll->base + PLL_CFG0);
186 ret = clk_wait_ack(pll);
188 /* clear the NEV_DIV_VAL */
189 val = readl_relaxed(pll->base + PLL_CFG0);
190 val &= ~PLL_NEWDIV_VAL;
191 writel_relaxed(val, pll->base + PLL_CFG0);
196 static const struct clk_ops clk_frac_pll_ops = {
197 .prepare = clk_pll_prepare,
198 .unprepare = clk_pll_unprepare,
199 .is_prepared = clk_pll_is_prepared,
200 .recalc_rate = clk_pll_recalc_rate,
201 .round_rate = clk_pll_round_rate,
202 .set_rate = clk_pll_set_rate,
205 struct clk_hw *imx_clk_hw_frac_pll(const char *name,
206 const char *parent_name,
209 struct clk_init_data init;
210 struct clk_frac_pll *pll;
214 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
216 return ERR_PTR(-ENOMEM);
219 init.ops = &clk_frac_pll_ops;
221 init.parent_names = &parent_name;
222 init.num_parents = 1;
225 pll->hw.init = &init;
229 ret = clk_hw_register(NULL, hw);
237 EXPORT_SYMBOL_GPL(imx_clk_hw_frac_pll);