Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-microblaze.git] / drivers / clk / clk-u300.c
1 /*
2  * U300 clock implementation
3  * Copyright (C) 2007-2012 ST-Ericsson AB
4  * License terms: GNU General Public License (GPL) version 2
5  * Author: Linus Walleij <linus.walleij@stericsson.com>
6  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7  */
8 #include <linux/clkdev.h>
9 #include <linux/slab.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/clk-provider.h>
13 #include <linux/spinlock.h>
14 #include <linux/of.h>
15 #include <linux/platform_data/clk-u300.h>
16
17 /* APP side SYSCON registers */
18 /* CLK Control Register 16bit (R/W) */
19 #define U300_SYSCON_CCR                                         (0x0000)
20 #define U300_SYSCON_CCR_I2S1_USE_VCXO                           (0x0040)
21 #define U300_SYSCON_CCR_I2S0_USE_VCXO                           (0x0020)
22 #define U300_SYSCON_CCR_TURN_VCXO_ON                            (0x0008)
23 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK                 (0x0007)
24 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER            (0x04)
25 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW                  (0x03)
26 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE         (0x02)
27 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH                 (0x01)
28 #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST                 (0x00)
29 /* CLK Status Register 16bit (R/W) */
30 #define U300_SYSCON_CSR                                         (0x0004)
31 #define U300_SYSCON_CSR_PLL208_LOCK_IND                         (0x0002)
32 #define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
33 /* Reset lines for SLOW devices 16bit (R/W) */
34 #define U300_SYSCON_RSR                                         (0x0014)
35 #define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
36 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
37 #define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
38 #define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
39 #define U300_SYSCON_RSR_KEYPAD_RESET_EN                         (0x0020)
40 #define U300_SYSCON_RSR_GPIO_RESET_EN                           (0x0010)
41 #define U300_SYSCON_RSR_EH_RESET_EN                             (0x0008)
42 #define U300_SYSCON_RSR_BTR_RESET_EN                            (0x0004)
43 #define U300_SYSCON_RSR_UART_RESET_EN                           (0x0002)
44 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
45 /* Reset lines for FAST devices 16bit (R/W) */
46 #define U300_SYSCON_RFR                                         (0x0018)
47 #define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
48 #define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
49 #define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
50 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
51 #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE                   (0x0008)
52 #define U300_SYSCON_RFR_I2C1_RESET_ENABLE                       (0x0004)
53 #define U300_SYSCON_RFR_I2C0_RESET_ENABLE                       (0x0002)
54 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
55 /* Reset lines for the rest of the peripherals 16bit (R/W) */
56 #define U300_SYSCON_RRR                                         (0x001c)
57 #define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
58 #define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
59 #define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
60 #define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
61 #define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
62 #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN                   (0x0080)
63 #define U300_SYSCON_RRR_NANDIF_RESET_EN                         (0x0040)
64 #define U300_SYSCON_RRR_EMIF_RESET_EN                           (0x0020)
65 #define U300_SYSCON_RRR_DMAC_RESET_EN                           (0x0010)
66 #define U300_SYSCON_RRR_CPU_RESET_EN                            (0x0008)
67 #define U300_SYSCON_RRR_APEX_RESET_EN                           (0x0004)
68 #define U300_SYSCON_RRR_AHB_RESET_EN                            (0x0002)
69 #define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
70 /* Clock enable for SLOW peripherals 16bit (R/W) */
71 #define U300_SYSCON_CESR                                        (0x0020)
72 #define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
73 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
74 #define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
75 #define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
76 #define U300_SYSCON_CESR_GPIO_CLK_EN                            (0x0010)
77 #define U300_SYSCON_CESR_EH_CLK_EN                              (0x0008)
78 #define U300_SYSCON_CESR_BTR_CLK_EN                             (0x0004)
79 #define U300_SYSCON_CESR_UART_CLK_EN                            (0x0002)
80 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
81 /* Clock enable for FAST peripherals 16bit (R/W) */
82 #define U300_SYSCON_CEFR                                        (0x0024)
83 #define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
84 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
85 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
86 #define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
87 #define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
88 #define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
89 #define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
90 #define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
91 #define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
92 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
93 /* Clock enable for the rest of the peripherals 16bit (R/W) */
94 #define U300_SYSCON_CERR                                        (0x0028)
95 #define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
96 #define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
97 #define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
98 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
99 #define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
100 #define U300_SYSCON_CERR_XGAM_CLK_EN                            (0x0100)
101 #define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN                       (0x0080)
102 #define U300_SYSCON_CERR_NANDIF_CLK_EN                          (0x0040)
103 #define U300_SYSCON_CERR_EMIF_CLK_EN                            (0x0020)
104 #define U300_SYSCON_CERR_DMAC_CLK_EN                            (0x0010)
105 #define U300_SYSCON_CERR_CPU_CLK_EN                             (0x0008)
106 #define U300_SYSCON_CERR_APEX_CLK_EN                            (0x0004)
107 #define U300_SYSCON_CERR_AHB_CLK_EN                             (0x0002)
108 #define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
109 /* Single block clock enable 16bit (-/W) */
110 #define U300_SYSCON_SBCER                                       (0x002c)
111 #define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
112 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
113 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
114 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
115 #define U300_SYSCON_SBCER_GPIO_CLK_EN                           (0x0004)
116 #define U300_SYSCON_SBCER_EH_CLK_EN                             (0x0003)
117 #define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
118 #define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
119 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
120 #define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
121 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
122 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
123 #define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
124 #define U300_SYSCON_SBCER_MMC_CLK_EN                            (0x0015)
125 #define U300_SYSCON_SBCER_I2S1_CLK_EN                           (0x0014)
126 #define U300_SYSCON_SBCER_I2S0_CLK_EN                           (0x0013)
127 #define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
128 #define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
129 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
130 #define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
131 #define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
132 #define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
133 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
134 #define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
135 #define U300_SYSCON_SBCER_XGAM_CLK_EN                           (0x0028)
136 #define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN                      (0x0027)
137 #define U300_SYSCON_SBCER_NANDIF_CLK_EN                         (0x0026)
138 #define U300_SYSCON_SBCER_EMIF_CLK_EN                           (0x0025)
139 #define U300_SYSCON_SBCER_DMAC_CLK_EN                           (0x0024)
140 #define U300_SYSCON_SBCER_CPU_CLK_EN                            (0x0023)
141 #define U300_SYSCON_SBCER_APEX_CLK_EN                           (0x0022)
142 #define U300_SYSCON_SBCER_AHB_CLK_EN                            (0x0021)
143 #define U300_SYSCON_SBCER_AAIF_CLK_EN                           (0x0020)
144 /* Single block clock disable 16bit (-/W) */
145 #define U300_SYSCON_SBCDR                                       (0x0030)
146 /* Same values as above for SBCER */
147 /* Clock force SLOW peripherals 16bit (R/W) */
148 #define U300_SYSCON_CFSR                                        (0x003c)
149 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
150 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
151 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
152 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
153 #define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN                      (0x0010)
154 #define U300_SYSCON_CFSR_EH_CLK_FORCE_EN                        (0x0008)
155 #define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN                       (0x0004)
156 #define U300_SYSCON_CFSR_UART_CLK_FORCE_EN                      (0x0002)
157 #define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN               (0x0001)
158 /* Clock force FAST peripherals 16bit (R/W) */
159 #define U300_SYSCON_CFFR                                        (0x40)
160 /* Values not defined. Define if you want to use them. */
161 /* Clock force the rest of the peripherals 16bit (R/W) */
162 #define U300_SYSCON_CFRR                                        (0x44)
163 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
164 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
165 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
166 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
167 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
168 #define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN                      (0x0100)
169 #define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN                 (0x0080)
170 #define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN                    (0x0040)
171 #define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN                      (0x0020)
172 #define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN                      (0x0010)
173 #define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN                       (0x0008)
174 #define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN                      (0x0004)
175 #define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN                       (0x0002)
176 #define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN                      (0x0001)
177 /* PLL208 Frequency Control 16bit (R/W) */
178 #define U300_SYSCON_PFCR                                        (0x48)
179 #define U300_SYSCON_PFCR_DPLL_MULT_NUM                          (0x000F)
180 /* Power Management Control 16bit (R/W) */
181 #define U300_SYSCON_PMCR                                        (0x50)
182 #define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
183 #define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
184 /* Reset Out 16bit (R/W) */
185 #define U300_SYSCON_RCR                                         (0x6c)
186 #define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE                   (0x0001)
187 /* EMIF Slew Rate Control 16bit (R/W) */
188 #define U300_SYSCON_SRCLR                                       (0x70)
189 #define U300_SYSCON_SRCLR_MASK                                  (0x03FF)
190 #define U300_SYSCON_SRCLR_VALUE                                 (0x03FF)
191 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B                       (0x0200)
192 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A                       (0x0100)
193 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B                       (0x0080)
194 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A                       (0x0040)
195 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B                       (0x0020)
196 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A                       (0x0010)
197 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B                       (0x0008)
198 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A                       (0x0004)
199 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B                       (0x0002)
200 #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A                       (0x0001)
201 /* EMIF Clock Control Register 16bit (R/W) */
202 #define U300_SYSCON_ECCR                                        (0x0078)
203 #define U300_SYSCON_ECCR_MASK                                   (0x000F)
204 #define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE         (0x0008)
205 #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
206 #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
207 #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
208 /* MMC/MSPRO frequency divider register 0 16bit (R/W) */
209 #define U300_SYSCON_MMF0R                                       (0x90)
210 #define U300_SYSCON_MMF0R_MASK                                  (0x00FF)
211 #define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK                      (0x00F0)
212 #define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK                       (0x000F)
213 /* MMC/MSPRO frequency divider register 1 16bit (R/W) */
214 #define U300_SYSCON_MMF1R                                       (0x94)
215 #define U300_SYSCON_MMF1R_MASK                                  (0x00FF)
216 #define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK                      (0x00F0)
217 #define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK                       (0x000F)
218 /* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
219 #define U300_SYSCON_MMCR                                        (0x9C)
220 #define U300_SYSCON_MMCR_MASK                                   (0x0003)
221 #define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE                  (0x0002)
222 #define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE                   (0x0001)
223 /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
224 #define U300_SYSCON_S0CCR                                       (0x120)
225 #define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
226 #define U300_SYSCON_S0CCR_CLOCK_REQ                             (0x4000)
227 #define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR                     (0x2000)
228 #define U300_SYSCON_S0CCR_CLOCK_INV                             (0x0200)
229 #define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK                       (0x01E0)
230 #define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK                     (0x001E)
231 #define U300_SYSCON_S0CCR_CLOCK_ENABLE                          (0x0001)
232 #define U300_SYSCON_S0CCR_SEL_MCLK                              (0x8 << 1)
233 #define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK                       (0xA << 1)
234 #define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK                      (0xC << 1)
235 #define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK                      (0xD << 1)
236 #define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK                    (0xE << 1)
237 #define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK                     (0x0 << 1)
238 #define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK                       (0x2 << 1)
239 #define U300_SYSCON_S0CCR_SEL_RTC_CLK                           (0x4 << 1)
240 #define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK                    (0x6 << 1)
241 /* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
242 #define U300_SYSCON_S1CCR                                       (0x124)
243 #define U300_SYSCON_S1CCR_FIELD_MASK                            (0x43FF)
244 #define U300_SYSCON_S1CCR_CLOCK_REQ                             (0x4000)
245 #define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR                     (0x2000)
246 #define U300_SYSCON_S1CCR_CLOCK_INV                             (0x0200)
247 #define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK                       (0x01E0)
248 #define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK                     (0x001E)
249 #define U300_SYSCON_S1CCR_CLOCK_ENABLE                          (0x0001)
250 #define U300_SYSCON_S1CCR_SEL_MCLK                              (0x8 << 1)
251 #define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK                       (0xA << 1)
252 #define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK                      (0xC << 1)
253 #define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK                      (0xD << 1)
254 #define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK                    (0xE << 1)
255 #define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK                     (0x0 << 1)
256 #define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK                       (0x2 << 1)
257 #define U300_SYSCON_S1CCR_SEL_RTC_CLK                           (0x4 << 1)
258 #define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK                    (0x6 << 1)
259 /* SYS_2_CLK_CONTROL third clock control 16 bit (R/W) */
260 #define U300_SYSCON_S2CCR                                       (0x128)
261 #define U300_SYSCON_S2CCR_FIELD_MASK                            (0xC3FF)
262 #define U300_SYSCON_S2CCR_CLK_STEAL                             (0x8000)
263 #define U300_SYSCON_S2CCR_CLOCK_REQ                             (0x4000)
264 #define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR                     (0x2000)
265 #define U300_SYSCON_S2CCR_CLOCK_INV                             (0x0200)
266 #define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK                       (0x01E0)
267 #define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK                     (0x001E)
268 #define U300_SYSCON_S2CCR_CLOCK_ENABLE                          (0x0001)
269 #define U300_SYSCON_S2CCR_SEL_MCLK                              (0x8 << 1)
270 #define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK                       (0xA << 1)
271 #define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK                      (0xC << 1)
272 #define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK                      (0xD << 1)
273 #define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK                    (0xE << 1)
274 #define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK                     (0x0 << 1)
275 #define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK                       (0x2 << 1)
276 #define U300_SYSCON_S2CCR_SEL_RTC_CLK                           (0x4 << 1)
277 #define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK                    (0x6 << 1)
278 /* SC_PLL_IRQ_CONTROL 16bit (R/W) */
279 #define U300_SYSCON_PICR                                        (0x0130)
280 #define U300_SYSCON_PICR_MASK                                   (0x00FF)
281 #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE           (0x0080)
282 #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE          (0x0040)
283 #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE            (0x0020)
284 #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE           (0x0010)
285 #define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE            (0x0008)
286 #define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE              (0x0004)
287 #define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE           (0x0002)
288 #define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE             (0x0001)
289 /* SC_PLL_IRQ_STATUS 16 bit (R/-) */
290 #define U300_SYSCON_PISR                                        (0x0134)
291 #define U300_SYSCON_PISR_MASK                                   (0x000F)
292 #define U300_SYSCON_PISR_PLL13_UNLOCK_IND                       (0x0008)
293 #define U300_SYSCON_PISR_PLL13_LOCK_IND                         (0x0004)
294 #define U300_SYSCON_PISR_PLL208_UNLOCK_IND                      (0x0002)
295 #define U300_SYSCON_PISR_PLL208_LOCK_IND                        (0x0001)
296 /* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
297 #define U300_SYSCON_PICLR                                       (0x0138)
298 #define U300_SYSCON_PICLR_MASK                                  (0x000F)
299 #define U300_SYSCON_PICLR_RWMASK                                (0x0000)
300 #define U300_SYSCON_PICLR_PLL13_UNLOCK_SC                       (0x0008)
301 #define U300_SYSCON_PICLR_PLL13_LOCK_SC                         (0x0004)
302 #define U300_SYSCON_PICLR_PLL208_UNLOCK_SC                      (0x0002)
303 #define U300_SYSCON_PICLR_PLL208_LOCK_SC                        (0x0001)
304 /* Clock activity observability register 0 */
305 #define U300_SYSCON_C0OAR                                       (0x140)
306 #define U300_SYSCON_C0OAR_MASK                                  (0xFFFF)
307 #define U300_SYSCON_C0OAR_VALUE                                 (0xFFFF)
308 #define U300_SYSCON_C0OAR_BT_H_CLK                              (0x8000)
309 #define U300_SYSCON_C0OAR_ASPB_P_CLK                            (0x4000)
310 #define U300_SYSCON_C0OAR_APP_SEMI_H_CLK                        (0x2000)
311 #define U300_SYSCON_C0OAR_APP_SEMI_CLK                          (0x1000)
312 #define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK                     (0x0800)
313 #define U300_SYSCON_C0OAR_APP_I2S1_CLK                          (0x0400)
314 #define U300_SYSCON_C0OAR_APP_I2S0_CLK                          (0x0200)
315 #define U300_SYSCON_C0OAR_APP_CPU_CLK                           (0x0100)
316 #define U300_SYSCON_C0OAR_APP_52_CLK                            (0x0080)
317 #define U300_SYSCON_C0OAR_APP_208_CLK                           (0x0040)
318 #define U300_SYSCON_C0OAR_APP_104_CLK                           (0x0020)
319 #define U300_SYSCON_C0OAR_APEX_CLK                              (0x0010)
320 #define U300_SYSCON_C0OAR_AHPB_M_H_CLK                          (0x0008)
321 #define U300_SYSCON_C0OAR_AHB_CLK                               (0x0004)
322 #define U300_SYSCON_C0OAR_AFPB_P_CLK                            (0x0002)
323 #define U300_SYSCON_C0OAR_AAIF_CLK                              (0x0001)
324 /* Clock activity observability register 1 */
325 #define U300_SYSCON_C1OAR                                       (0x144)
326 #define U300_SYSCON_C1OAR_MASK                                  (0x3FFE)
327 #define U300_SYSCON_C1OAR_VALUE                                 (0x3FFE)
328 #define U300_SYSCON_C1OAR_NFIF_F_CLK                            (0x2000)
329 #define U300_SYSCON_C1OAR_MSPRO_CLK                             (0x1000)
330 #define U300_SYSCON_C1OAR_MMC_P_CLK                             (0x0800)
331 #define U300_SYSCON_C1OAR_MMC_CLK                               (0x0400)
332 #define U300_SYSCON_C1OAR_KP_P_CLK                              (0x0200)
333 #define U300_SYSCON_C1OAR_I2C1_P_CLK                            (0x0100)
334 #define U300_SYSCON_C1OAR_I2C0_P_CLK                            (0x0080)
335 #define U300_SYSCON_C1OAR_GPIO_CLK                              (0x0040)
336 #define U300_SYSCON_C1OAR_EMIF_MPMC_CLK                         (0x0020)
337 #define U300_SYSCON_C1OAR_EMIF_H_CLK                            (0x0010)
338 #define U300_SYSCON_C1OAR_EVHIST_CLK                            (0x0008)
339 #define U300_SYSCON_C1OAR_PPM_CLK                               (0x0004)
340 #define U300_SYSCON_C1OAR_DMA_CLK                               (0x0002)
341 /* Clock activity observability register 2 */
342 #define U300_SYSCON_C2OAR                                       (0x148)
343 #define U300_SYSCON_C2OAR_MASK                                  (0x0FFF)
344 #define U300_SYSCON_C2OAR_VALUE                                 (0x0FFF)
345 #define U300_SYSCON_C2OAR_XGAM_CDI_CLK                          (0x0800)
346 #define U300_SYSCON_C2OAR_XGAM_CLK                              (0x0400)
347 #define U300_SYSCON_C2OAR_VC_H_CLK                              (0x0200)
348 #define U300_SYSCON_C2OAR_VC_CLK                                (0x0100)
349 #define U300_SYSCON_C2OAR_UA_P_CLK                              (0x0080)
350 #define U300_SYSCON_C2OAR_TMR1_CLK                              (0x0040)
351 #define U300_SYSCON_C2OAR_TMR0_CLK                              (0x0020)
352 #define U300_SYSCON_C2OAR_SPI_P_CLK                             (0x0010)
353 #define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK                     (0x0008)
354 #define U300_SYSCON_C2OAR_PCM_I2S1_CLK                          (0x0004)
355 #define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK                     (0x0002)
356 #define U300_SYSCON_C2OAR_PCM_I2S0_CLK                          (0x0001)
357
358
359 /*
360  * The clocking hierarchy currently looks like this.
361  * NOTE: the idea is NOT to show how the clocks are routed on the chip!
362  * The ideas is to show dependencies, so a clock higher up in the
363  * hierarchy has to be on in order for another clock to be on. Now,
364  * both CPU and DMA can actually be on top of the hierarchy, and that
365  * is not modeled currently. Instead we have the backbone AMBA bus on
366  * top. This bus cannot be programmed in any way but conceptually it
367  * needs to be active for the bridges and devices to transport data.
368  *
369  * Please be aware that a few clocks are hw controlled, which mean that
370  * the hw itself can turn on/off or change the rate of the clock when
371  * needed!
372  *
373  *  AMBA bus
374  *  |
375  *  +- CPU
376  *  +- FSMC NANDIF NAND Flash interface
377  *  +- SEMI Shared Memory interface
378  *  +- ISP Image Signal Processor (U335 only)
379  *  +- CDS (U335 only)
380  *  +- DMA Direct Memory Access Controller
381  *  +- AAIF APP/ACC Interface (Mobile Scalable Link, MSL)
382  *  +- APEX
383  *  +- VIDEO_ENC AVE2/3 Video Encoder
384  *  +- XGAM Graphics Accelerator Controller
385  *  +- AHB
386  *  |
387  *  +- ahb:0 AHB Bridge
388  *  |  |
389  *  |  +- ahb:1 INTCON Interrupt controller
390  *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
391  *  |  +- ahb:4 EMIF   External Memory interface
392  *  |
393  *  +- fast:0 FAST bridge
394  *  |  |
395  *  |  +- fast:1 MMCSD MMC/SD card reader controller
396  *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
397  *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
398  *  |  +- fast:4 I2C0  I2C channel 0 controller
399  *  |  +- fast:5 I2C1  I2C channel 1 controller
400  *  |  +- fast:6 SPI   SPI controller
401  *  |  +- fast:7 UART1 Secondary UART (U335 only)
402  *  |
403  *  +- slow:0 SLOW bridge
404  *     |
405  *     +- slow:1 SYSCON (not possible to control)
406  *     +- slow:2 WDOG Watchdog
407  *     +- slow:3 UART0 primary UART
408  *     +- slow:4 TIMER_APP Application timer - used in Linux
409  *     +- slow:5 KEYPAD controller
410  *     +- slow:6 GPIO controller
411  *     +- slow:7 RTC controller
412  *     +- slow:8 BT Bus Tracer (not used currently)
413  *     +- slow:9 EH Event Handler (not used currently)
414  *     +- slow:a TIMER_ACC Access style timer (not used currently)
415  *     +- slow:b PPM (U335 only, what is that?)
416  */
417
418 /* Global syscon virtual base */
419 static void __iomem *syscon_vbase;
420
421 /**
422  * struct clk_syscon - U300 syscon clock
423  * @hw: corresponding clock hardware entry
424  * @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
425  *      and does not need any magic pokes to be enabled/disabled
426  * @reset: state holder, whether this block's reset line is asserted or not
427  * @res_reg: reset line enable/disable flag register
428  * @res_bit: bit for resetting or taking this consumer out of reset
429  * @en_reg: clock line enable/disable flag register
430  * @en_bit: bit for enabling/disabling this consumer clock line
431  * @clk_val: magic value to poke in the register to enable/disable
432  *      this one clock
433  */
434 struct clk_syscon {
435         struct clk_hw hw;
436         bool hw_ctrld;
437         bool reset;
438         void __iomem *res_reg;
439         u8 res_bit;
440         void __iomem *en_reg;
441         u8 en_bit;
442         u16 clk_val;
443 };
444
445 #define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
446
447 static DEFINE_SPINLOCK(syscon_resetreg_lock);
448
449 /*
450  * Reset control functions. We remember if a block has been
451  * taken out of reset and don't remove the reset assertion again
452  * and vice versa. Currently we only remove resets so the
453  * enablement function is defined out.
454  */
455 static void syscon_block_reset_enable(struct clk_syscon *sclk)
456 {
457         unsigned long iflags;
458         u16 val;
459
460         /* Not all blocks support resetting */
461         if (!sclk->res_reg)
462                 return;
463         spin_lock_irqsave(&syscon_resetreg_lock, iflags);
464         val = readw(sclk->res_reg);
465         val |= BIT(sclk->res_bit);
466         writew(val, sclk->res_reg);
467         spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
468         sclk->reset = true;
469 }
470
471 static void syscon_block_reset_disable(struct clk_syscon *sclk)
472 {
473         unsigned long iflags;
474         u16 val;
475
476         /* Not all blocks support resetting */
477         if (!sclk->res_reg)
478                 return;
479         spin_lock_irqsave(&syscon_resetreg_lock, iflags);
480         val = readw(sclk->res_reg);
481         val &= ~BIT(sclk->res_bit);
482         writew(val, sclk->res_reg);
483         spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
484         sclk->reset = false;
485 }
486
487 static int syscon_clk_prepare(struct clk_hw *hw)
488 {
489         struct clk_syscon *sclk = to_syscon(hw);
490
491         /* If the block is in reset, bring it out */
492         if (sclk->reset)
493                 syscon_block_reset_disable(sclk);
494         return 0;
495 }
496
497 static void syscon_clk_unprepare(struct clk_hw *hw)
498 {
499         struct clk_syscon *sclk = to_syscon(hw);
500
501         /* Please don't force the console into reset */
502         if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
503                 return;
504         /* When unpreparing, force block into reset */
505         if (!sclk->reset)
506                 syscon_block_reset_enable(sclk);
507 }
508
509 static int syscon_clk_enable(struct clk_hw *hw)
510 {
511         struct clk_syscon *sclk = to_syscon(hw);
512
513         /* Don't touch the hardware controlled clocks */
514         if (sclk->hw_ctrld)
515                 return 0;
516         /* These cannot be controlled */
517         if (sclk->clk_val == 0xFFFFU)
518                 return 0;
519
520         writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
521         return 0;
522 }
523
524 static void syscon_clk_disable(struct clk_hw *hw)
525 {
526         struct clk_syscon *sclk = to_syscon(hw);
527
528         /* Don't touch the hardware controlled clocks */
529         if (sclk->hw_ctrld)
530                 return;
531         if (sclk->clk_val == 0xFFFFU)
532                 return;
533         /* Please don't disable the console port */
534         if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
535                 return;
536
537         writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
538 }
539
540 static int syscon_clk_is_enabled(struct clk_hw *hw)
541 {
542         struct clk_syscon *sclk = to_syscon(hw);
543         u16 val;
544
545         /* If no enable register defined, it's always-on */
546         if (!sclk->en_reg)
547                 return 1;
548
549         val = readw(sclk->en_reg);
550         val &= BIT(sclk->en_bit);
551
552         return val ? 1 : 0;
553 }
554
555 static u16 syscon_get_perf(void)
556 {
557         u16 val;
558
559         val = readw(syscon_vbase + U300_SYSCON_CCR);
560         val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
561         return val;
562 }
563
564 static unsigned long
565 syscon_clk_recalc_rate(struct clk_hw *hw,
566                        unsigned long parent_rate)
567 {
568         struct clk_syscon *sclk = to_syscon(hw);
569         u16 perf = syscon_get_perf();
570
571         switch (sclk->clk_val) {
572         case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
573         case U300_SYSCON_SBCER_I2C0_CLK_EN:
574         case U300_SYSCON_SBCER_I2C1_CLK_EN:
575         case U300_SYSCON_SBCER_MMC_CLK_EN:
576         case U300_SYSCON_SBCER_SPI_CLK_EN:
577                 /* The FAST clocks have one progression */
578                 switch (perf) {
579                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
580                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
581                         return 13000000;
582                 default:
583                         return parent_rate; /* 26 MHz */
584                 }
585         case U300_SYSCON_SBCER_DMAC_CLK_EN:
586         case U300_SYSCON_SBCER_NANDIF_CLK_EN:
587         case U300_SYSCON_SBCER_XGAM_CLK_EN:
588                 /* AMBA interconnect peripherals */
589                 switch (perf) {
590                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
591                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
592                         return 6500000;
593                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
594                         return 26000000;
595                 default:
596                         return parent_rate; /* 52 MHz */
597                 }
598         case U300_SYSCON_SBCER_SEMI_CLK_EN:
599         case U300_SYSCON_SBCER_EMIF_CLK_EN:
600                 /* EMIF speeds */
601                 switch (perf) {
602                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
603                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
604                         return 13000000;
605                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
606                         return 52000000;
607                 default:
608                         return 104000000;
609                 }
610         case U300_SYSCON_SBCER_CPU_CLK_EN:
611                 /* And the fast CPU clock */
612                 switch (perf) {
613                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
614                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
615                         return 13000000;
616                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
617                         return 52000000;
618                 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
619                         return 104000000;
620                 default:
621                         return parent_rate; /* 208 MHz */
622                 }
623         default:
624                 /*
625                  * The SLOW clocks and default just inherit the rate of
626                  * their parent (typically PLL13 13 MHz).
627                  */
628                 return parent_rate;
629         }
630 }
631
632 static long
633 syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
634                       unsigned long *prate)
635 {
636         struct clk_syscon *sclk = to_syscon(hw);
637
638         if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
639                 return *prate;
640         /* We really only support setting the rate of the CPU clock */
641         if (rate <= 13000000)
642                 return 13000000;
643         if (rate <= 52000000)
644                 return 52000000;
645         if (rate <= 104000000)
646                 return 104000000;
647         return 208000000;
648 }
649
650 static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
651                                unsigned long parent_rate)
652 {
653         struct clk_syscon *sclk = to_syscon(hw);
654         u16 val;
655
656         /* We only support setting the rate of the CPU clock */
657         if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
658                 return -EINVAL;
659         switch (rate) {
660         case 13000000:
661                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
662                 break;
663         case 52000000:
664                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
665                 break;
666         case 104000000:
667                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
668                 break;
669         case 208000000:
670                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
671                 break;
672         default:
673                 return -EINVAL;
674         }
675         val |= readw(syscon_vbase + U300_SYSCON_CCR) &
676                 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
677         writew(val, syscon_vbase + U300_SYSCON_CCR);
678         return 0;
679 }
680
681 static const struct clk_ops syscon_clk_ops = {
682         .prepare = syscon_clk_prepare,
683         .unprepare = syscon_clk_unprepare,
684         .enable = syscon_clk_enable,
685         .disable = syscon_clk_disable,
686         .is_enabled = syscon_clk_is_enabled,
687         .recalc_rate = syscon_clk_recalc_rate,
688         .round_rate = syscon_clk_round_rate,
689         .set_rate = syscon_clk_set_rate,
690 };
691
692 static struct clk_hw * __init
693 syscon_clk_register(struct device *dev, const char *name,
694                     const char *parent_name, unsigned long flags,
695                     bool hw_ctrld,
696                     void __iomem *res_reg, u8 res_bit,
697                     void __iomem *en_reg, u8 en_bit,
698                     u16 clk_val)
699 {
700         struct clk_hw *hw;
701         struct clk_syscon *sclk;
702         struct clk_init_data init;
703         int ret;
704
705         sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
706         if (!sclk)
707                 return ERR_PTR(-ENOMEM);
708
709         init.name = name;
710         init.ops = &syscon_clk_ops;
711         init.flags = flags;
712         init.parent_names = (parent_name ? &parent_name : NULL);
713         init.num_parents = (parent_name ? 1 : 0);
714         sclk->hw.init = &init;
715         sclk->hw_ctrld = hw_ctrld;
716         /* Assume the block is in reset at registration */
717         sclk->reset = true;
718         sclk->res_reg = res_reg;
719         sclk->res_bit = res_bit;
720         sclk->en_reg = en_reg;
721         sclk->en_bit = en_bit;
722         sclk->clk_val = clk_val;
723
724         hw = &sclk->hw;
725         ret = clk_hw_register(dev, hw);
726         if (ret) {
727                 kfree(sclk);
728                 hw = ERR_PTR(ret);
729         }
730
731         return hw;
732 }
733
734 #define U300_CLK_TYPE_SLOW 0
735 #define U300_CLK_TYPE_FAST 1
736 #define U300_CLK_TYPE_REST 2
737
738 /**
739  * struct u300_clock - defines the bits and pieces for a certain clock
740  * @type: the clock type, slow fast or rest
741  * @id: the bit in the slow/fast/rest register for this clock
742  * @hw_ctrld: whether the clock is hardware controlled
743  * @clk_val: a value to poke in the one-write enable/disable registers
744  */
745 struct u300_clock {
746         u8 type;
747         u8 id;
748         bool hw_ctrld;
749         u16 clk_val;
750 };
751
752 static struct u300_clock const u300_clk_lookup[] __initconst = {
753         {
754                 .type = U300_CLK_TYPE_REST,
755                 .id = 3,
756                 .hw_ctrld = true,
757                 .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
758         },
759         {
760                 .type = U300_CLK_TYPE_REST,
761                 .id = 4,
762                 .hw_ctrld = true,
763                 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
764         },
765         {
766                 .type = U300_CLK_TYPE_REST,
767                 .id = 5,
768                 .hw_ctrld = false,
769                 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
770         },
771         {
772                 .type = U300_CLK_TYPE_REST,
773                 .id = 6,
774                 .hw_ctrld = false,
775                 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
776         },
777         {
778                 .type = U300_CLK_TYPE_REST,
779                 .id = 8,
780                 .hw_ctrld = true,
781                 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
782         },
783         {
784                 .type = U300_CLK_TYPE_REST,
785                 .id = 9,
786                 .hw_ctrld = false,
787                 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
788         },
789         {
790                 .type = U300_CLK_TYPE_REST,
791                 .id = 10,
792                 .hw_ctrld = true,
793                 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
794         },
795         {
796                 .type = U300_CLK_TYPE_REST,
797                 .id = 12,
798                 .hw_ctrld = false,
799                 /* INTCON: cannot be enabled, just taken out of reset */
800                 .clk_val = 0xFFFFU,
801         },
802         {
803                 .type = U300_CLK_TYPE_FAST,
804                 .id = 0,
805                 .hw_ctrld = true,
806                 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
807         },
808         {
809                 .type = U300_CLK_TYPE_FAST,
810                 .id = 1,
811                 .hw_ctrld = false,
812                 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
813         },
814         {
815                 .type = U300_CLK_TYPE_FAST,
816                 .id = 2,
817                 .hw_ctrld = false,
818                 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
819         },
820         {
821                 .type = U300_CLK_TYPE_FAST,
822                 .id = 5,
823                 .hw_ctrld = false,
824                 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
825         },
826         {
827                 .type = U300_CLK_TYPE_FAST,
828                 .id = 6,
829                 .hw_ctrld = false,
830                 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
831         },
832         {
833                 .type = U300_CLK_TYPE_SLOW,
834                 .id = 0,
835                 .hw_ctrld = true,
836                 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
837         },
838         {
839                 .type = U300_CLK_TYPE_SLOW,
840                 .id = 1,
841                 .hw_ctrld = false,
842                 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
843         },
844         {
845                 .type = U300_CLK_TYPE_SLOW,
846                 .id = 4,
847                 .hw_ctrld = false,
848                 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
849         },
850         {
851                 .type = U300_CLK_TYPE_SLOW,
852                 .id = 6,
853                 .hw_ctrld = true,
854                 /* No clock enable register bit */
855                 .clk_val = 0xFFFFU,
856         },
857         {
858                 .type = U300_CLK_TYPE_SLOW,
859                 .id = 7,
860                 .hw_ctrld = false,
861                 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
862         },
863         {
864                 .type = U300_CLK_TYPE_SLOW,
865                 .id = 8,
866                 .hw_ctrld = false,
867                 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
868         },
869 };
870
871 static void __init of_u300_syscon_clk_init(struct device_node *np)
872 {
873         struct clk_hw *hw = ERR_PTR(-EINVAL);
874         const char *clk_name = np->name;
875         const char *parent_name;
876         void __iomem *res_reg;
877         void __iomem *en_reg;
878         u32 clk_type;
879         u32 clk_id;
880         int i;
881
882         if (of_property_read_u32(np, "clock-type", &clk_type)) {
883                 pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
884                        __func__, clk_name);
885                 return;
886         }
887         if (of_property_read_u32(np, "clock-id", &clk_id)) {
888                 pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
889                        __func__, clk_name);
890                 return;
891         }
892         parent_name = of_clk_get_parent_name(np, 0);
893
894         switch (clk_type) {
895         case U300_CLK_TYPE_SLOW:
896                 res_reg = syscon_vbase + U300_SYSCON_RSR;
897                 en_reg = syscon_vbase + U300_SYSCON_CESR;
898                 break;
899         case U300_CLK_TYPE_FAST:
900                 res_reg = syscon_vbase + U300_SYSCON_RFR;
901                 en_reg = syscon_vbase + U300_SYSCON_CEFR;
902                 break;
903         case U300_CLK_TYPE_REST:
904                 res_reg = syscon_vbase + U300_SYSCON_RRR;
905                 en_reg = syscon_vbase + U300_SYSCON_CERR;
906                 break;
907         default:
908                 pr_err("unknown clock type %x specified\n", clk_type);
909                 return;
910         }
911
912         for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
913                 const struct u300_clock *u3clk = &u300_clk_lookup[i];
914
915                 if (u3clk->type == clk_type && u3clk->id == clk_id)
916                         hw = syscon_clk_register(NULL, clk_name, parent_name,
917                                                  0, u3clk->hw_ctrld,
918                                                  res_reg, u3clk->id,
919                                                  en_reg, u3clk->id,
920                                                  u3clk->clk_val);
921         }
922
923         if (!IS_ERR(hw)) {
924                 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
925
926                 /*
927                  * Some few system clocks - device tree does not
928                  * represent clocks without a corresponding device node.
929                  * for now we add these three clocks here.
930                  */
931                 if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
932                         clk_hw_register_clkdev(hw, NULL, "pl172");
933                 if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
934                         clk_hw_register_clkdev(hw, NULL, "semi");
935                 if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
936                         clk_hw_register_clkdev(hw, NULL, "intcon");
937         }
938 }
939
940 /**
941  * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
942  * @hw: corresponding clock hardware entry
943  * @is_mspro: if this is the memory stick clock rather than MMC/SD
944  */
945 struct clk_mclk {
946         struct clk_hw hw;
947         bool is_mspro;
948 };
949
950 #define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
951
952 static int mclk_clk_prepare(struct clk_hw *hw)
953 {
954         struct clk_mclk *mclk = to_mclk(hw);
955         u16 val;
956
957         /* The MMC and MSPRO clocks need some special set-up */
958         if (!mclk->is_mspro) {
959                 /* Set default MMC clock divisor to 18.9 MHz */
960                 writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
961                 val = readw(syscon_vbase + U300_SYSCON_MMCR);
962                 /* Disable the MMC feedback clock */
963                 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
964                 /* Disable MSPRO frequency */
965                 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
966                 writew(val, syscon_vbase + U300_SYSCON_MMCR);
967         } else {
968                 val = readw(syscon_vbase + U300_SYSCON_MMCR);
969                 /* Disable the MMC feedback clock */
970                 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
971                 /* Enable MSPRO frequency */
972                 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
973                 writew(val, syscon_vbase + U300_SYSCON_MMCR);
974         }
975
976         return 0;
977 }
978
979 static unsigned long
980 mclk_clk_recalc_rate(struct clk_hw *hw,
981                      unsigned long parent_rate)
982 {
983         u16 perf = syscon_get_perf();
984
985         switch (perf) {
986         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
987                 /*
988                  * Here, the 208 MHz PLL gets shut down and the always
989                  * on 13 MHz PLL used for RTC etc kicks into use
990                  * instead.
991                  */
992                 return 13000000;
993         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
994         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
995         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
996         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
997         {
998                 /*
999                  * This clock is under program control. The register is
1000                  * divided in two nybbles, bit 7-4 gives cycles-1 to count
1001                  * high, bit 3-0 gives cycles-1 to count low. Distribute
1002                  * these with no more than 1 cycle difference between
1003                  * low and high and add low and high to get the actual
1004                  * divisor. The base PLL is 208 MHz. Writing 0x00 will
1005                  * divide by 1 and 1 so the highest frequency possible
1006                  * is 104 MHz.
1007                  *
1008                  * e.g. 0x54 =>
1009                  * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
1010                  */
1011                 u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
1012                         U300_SYSCON_MMF0R_MASK;
1013                 switch (val) {
1014                 case 0x0054:
1015                         return 18900000;
1016                 case 0x0044:
1017                         return 20800000;
1018                 case 0x0043:
1019                         return 23100000;
1020                 case 0x0033:
1021                         return 26000000;
1022                 case 0x0032:
1023                         return 29700000;
1024                 case 0x0022:
1025                         return 34700000;
1026                 case 0x0021:
1027                         return 41600000;
1028                 case 0x0011:
1029                         return 52000000;
1030                 case 0x0000:
1031                         return 104000000;
1032                 default:
1033                         break;
1034                 }
1035         }
1036         default:
1037                 break;
1038         }
1039         return parent_rate;
1040 }
1041
1042 static long
1043 mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1044                     unsigned long *prate)
1045 {
1046         if (rate <= 18900000)
1047                 return 18900000;
1048         if (rate <= 20800000)
1049                 return 20800000;
1050         if (rate <= 23100000)
1051                 return 23100000;
1052         if (rate <= 26000000)
1053                 return 26000000;
1054         if (rate <= 29700000)
1055                 return 29700000;
1056         if (rate <= 34700000)
1057                 return 34700000;
1058         if (rate <= 41600000)
1059                 return 41600000;
1060         /* Highest rate */
1061         return 52000000;
1062 }
1063
1064 static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1065                              unsigned long parent_rate)
1066 {
1067         u16 val;
1068         u16 reg;
1069
1070         switch (rate) {
1071         case 18900000:
1072                 val = 0x0054;
1073                 break;
1074         case 20800000:
1075                 val = 0x0044;
1076                 break;
1077         case 23100000:
1078                 val = 0x0043;
1079                 break;
1080         case 26000000:
1081                 val = 0x0033;
1082                 break;
1083         case 29700000:
1084                 val = 0x0032;
1085                 break;
1086         case 34700000:
1087                 val = 0x0022;
1088                 break;
1089         case 41600000:
1090                 val = 0x0021;
1091                 break;
1092         case 52000000:
1093                 val = 0x0011;
1094                 break;
1095         case 104000000:
1096                 val = 0x0000;
1097                 break;
1098         default:
1099                 return -EINVAL;
1100         }
1101
1102         reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
1103                 ~U300_SYSCON_MMF0R_MASK;
1104         writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
1105         return 0;
1106 }
1107
1108 static const struct clk_ops mclk_ops = {
1109         .prepare = mclk_clk_prepare,
1110         .recalc_rate = mclk_clk_recalc_rate,
1111         .round_rate = mclk_clk_round_rate,
1112         .set_rate = mclk_clk_set_rate,
1113 };
1114
1115 static struct clk_hw * __init
1116 mclk_clk_register(struct device *dev, const char *name,
1117                   const char *parent_name, bool is_mspro)
1118 {
1119         struct clk_hw *hw;
1120         struct clk_mclk *mclk;
1121         struct clk_init_data init;
1122         int ret;
1123
1124         mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
1125         if (!mclk)
1126                 return ERR_PTR(-ENOMEM);
1127
1128         init.name = "mclk";
1129         init.ops = &mclk_ops;
1130         init.flags = 0;
1131         init.parent_names = (parent_name ? &parent_name : NULL);
1132         init.num_parents = (parent_name ? 1 : 0);
1133         mclk->hw.init = &init;
1134         mclk->is_mspro = is_mspro;
1135
1136         hw = &mclk->hw;
1137         ret = clk_hw_register(dev, hw);
1138         if (ret) {
1139                 kfree(mclk);
1140                 hw = ERR_PTR(ret);
1141         }
1142
1143         return hw;
1144 }
1145
1146 static void __init of_u300_syscon_mclk_init(struct device_node *np)
1147 {
1148         struct clk_hw *hw;
1149         const char *clk_name = np->name;
1150         const char *parent_name;
1151
1152         parent_name = of_clk_get_parent_name(np, 0);
1153         hw = mclk_clk_register(NULL, clk_name, parent_name, false);
1154         if (!IS_ERR(hw))
1155                 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
1156 }
1157
1158 static const struct of_device_id u300_clk_match[] __initconst = {
1159         {
1160                 .compatible = "fixed-clock",
1161                 .data = of_fixed_clk_setup,
1162         },
1163         {
1164                 .compatible = "fixed-factor-clock",
1165                 .data = of_fixed_factor_clk_setup,
1166         },
1167         {
1168                 .compatible = "stericsson,u300-syscon-clk",
1169                 .data = of_u300_syscon_clk_init,
1170         },
1171         {
1172                 .compatible = "stericsson,u300-syscon-mclk",
1173                 .data = of_u300_syscon_mclk_init,
1174         },
1175         {}
1176 };
1177
1178
1179 void __init u300_clk_init(void __iomem *base)
1180 {
1181         u16 val;
1182
1183         syscon_vbase = base;
1184
1185         /* Set system to run at PLL208, max performance, a known state. */
1186         val = readw(syscon_vbase + U300_SYSCON_CCR);
1187         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1188         writew(val, syscon_vbase + U300_SYSCON_CCR);
1189         /* Wait for the PLL208 to lock if not locked in yet */
1190         while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
1191                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1192
1193         /* Power management enable */
1194         val = readw(syscon_vbase + U300_SYSCON_PMCR);
1195         val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1196         writew(val, syscon_vbase + U300_SYSCON_PMCR);
1197
1198         of_clk_init(u300_clk_match);
1199 }