drivers/clk/clk-stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
   5  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/of.h>
  14 #include <linux/of_address.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17
  18 #include <dt-bindings/clock/stm32mp1-clks.h>
  19
  20 static DEFINE_SPINLOCK(rlock);
  21
  22 #define RCC_OCENSETR            0x0C
  23 #define RCC_HSICFGR             0x18
  24 #define RCC_RDLSICR             0x144
  25 #define RCC_PLL1CR              0x80
  26 #define RCC_PLL1CFGR1           0x84
  27 #define RCC_PLL1CFGR2           0x88
  28 #define RCC_PLL2CR              0x94
  29 #define RCC_PLL2CFGR1           0x98
  30 #define RCC_PLL2CFGR2           0x9C
  31 #define RCC_PLL3CR              0x880
  32 #define RCC_PLL3CFGR1           0x884
  33 #define RCC_PLL3CFGR2           0x888
  34 #define RCC_PLL4CR              0x894
  35 #define RCC_PLL4CFGR1           0x898
  36 #define RCC_PLL4CFGR2           0x89C
  37 #define RCC_APB1ENSETR          0xA00
  38 #define RCC_APB2ENSETR          0xA08
  39 #define RCC_APB3ENSETR          0xA10
  40 #define RCC_APB4ENSETR          0x200
  41 #define RCC_APB5ENSETR          0x208
  42 #define RCC_AHB2ENSETR          0xA18
  43 #define RCC_AHB3ENSETR          0xA20
  44 #define RCC_AHB4ENSETR          0xA28
  45 #define RCC_AHB5ENSETR          0x210
  46 #define RCC_AHB6ENSETR          0x218
  47 #define RCC_AHB6LPENSETR        0x318
  48 #define RCC_RCK12SELR           0x28
  49 #define RCC_RCK3SELR            0x820
  50 #define RCC_RCK4SELR            0x824
  51 #define RCC_MPCKSELR            0x20
  52 #define RCC_ASSCKSELR           0x24
  53 #define RCC_MSSCKSELR           0x48
  54 #define RCC_SPI6CKSELR          0xC4
  55 #define RCC_SDMMC12CKSELR       0x8F4
  56 #define RCC_SDMMC3CKSELR        0x8F8
  57 #define RCC_FMCCKSELR           0x904
  58 #define RCC_I2C46CKSELR         0xC0
  59 #define RCC_I2C12CKSELR         0x8C0
  60 #define RCC_I2C35CKSELR         0x8C4
  61 #define RCC_UART1CKSELR         0xC8
  62 #define RCC_QSPICKSELR          0x900
  63 #define RCC_ETHCKSELR           0x8FC
  64 #define RCC_RNG1CKSELR          0xCC
  65 #define RCC_RNG2CKSELR          0x920
  66 #define RCC_GPUCKSELR           0x938
  67 #define RCC_USBCKSELR           0x91C
  68 #define RCC_STGENCKSELR         0xD4
  69 #define RCC_SPDIFCKSELR         0x914
  70 #define RCC_SPI2S1CKSELR        0x8D8
  71 #define RCC_SPI2S23CKSELR       0x8DC
  72 #define RCC_SPI2S45CKSELR       0x8E0
  73 #define RCC_CECCKSELR           0x918
  74 #define RCC_LPTIM1CKSELR        0x934
  75 #define RCC_LPTIM23CKSELR       0x930
  76 #define RCC_LPTIM45CKSELR       0x92C
  77 #define RCC_UART24CKSELR        0x8E8
  78 #define RCC_UART35CKSELR        0x8EC
  79 #define RCC_UART6CKSELR         0x8E4
  80 #define RCC_UART78CKSELR        0x8F0
  81 #define RCC_FDCANCKSELR         0x90C
  82 #define RCC_SAI1CKSELR          0x8C8
  83 #define RCC_SAI2CKSELR          0x8CC
  84 #define RCC_SAI3CKSELR          0x8D0
  85 #define RCC_SAI4CKSELR          0x8D4
  86 #define RCC_ADCCKSELR           0x928
  87 #define RCC_MPCKDIVR            0x2C
  88 #define RCC_DSICKSELR           0x924
  89 #define RCC_CPERCKSELR          0xD0
  90 #define RCC_MCO1CFGR            0x800
  91 #define RCC_MCO2CFGR            0x804
  92 #define RCC_BDCR                0x140
  93 #define RCC_AXIDIVR             0x30
  94 #define RCC_MCUDIVR             0x830
  95 #define RCC_APB1DIVR            0x834
  96 #define RCC_APB2DIVR            0x838
  97 #define RCC_APB3DIVR            0x83C
  98 #define RCC_APB4DIVR            0x3C
  99 #define RCC_APB5DIVR            0x40
 100 #define RCC_TIMG1PRER           0x828
 101 #define RCC_TIMG2PRER           0x82C
 102 #define RCC_RTCDIVR             0x44
 103 #define RCC_DBGCFGR             0x80C
 104
 105 #define RCC_CLR 0x4
 106
 107 static const char * const ref12_parents[] = {
 108         "ck_hsi", "ck_hse"
 109 };
 110
 111 static const char * const ref3_parents[] = {
 112         "ck_hsi", "ck_hse", "ck_csi"
 113 };
 114
 115 static const char * const ref4_parents[] = {
 116         "ck_hsi", "ck_hse", "ck_csi"
 117 };
 118
 119 static const char * const cpu_src[] = {
 120         "ck_hsi", "ck_hse", "pll1_p"
 121 };
 122
 123 static const char * const axi_src[] = {
 124         "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
 125 };
 126
 127 static const char * const per_src[] = {
 128         "ck_hsi", "ck_csi", "ck_hse"
 129 };
 130
 131 static const char * const mcu_src[] = {
 132         "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
 133 };
 134
 135 static const char * const sdmmc12_src[] = {
 136         "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
 137 };
 138
 139 static const char * const sdmmc3_src[] = {
 140         "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
 141 };
 142
 143 static const char * const fmc_src[] = {
 144         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 145 };
 146
 147 static const char * const qspi_src[] = {
 148         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 149 };
 150
 151 static const char * const eth_src[] = {
 152         "pll4_p", "pll3_q"
 153 };
 154
 155 static const char * const rng_src[] = {
 156         "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
 157 };
 158
 159 static const char * const usbphy_src[] = {
 160         "ck_hse", "pll4_r", "clk-hse-div2"
 161 };
 162
 163 static const char * const usbo_src[] = {
 164         "pll4_r", "ck_usbo_48m"
 165 };
 166
 167 static const char * const stgen_src[] = {
 168         "ck_hsi", "ck_hse"
 169 };
 170
 171 static const char * const spdif_src[] = {
 172         "pll4_p", "pll3_q", "ck_hsi"
 173 };
 174
 175 static const char * const spi123_src[] = {
 176         "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 177 };
 178
 179 static const char * const spi45_src[] = {
 180         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 181 };
 182
 183 static const char * const spi6_src[] = {
 184         "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
 185 };
 186
 187 static const char * const cec_src[] = {
 188         "ck_lse", "ck_lsi", "ck_csi"
 189 };
 190
 191 static const char * const i2c12_src[] = {
 192         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 193 };
 194
 195 static const char * const i2c35_src[] = {
 196         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 197 };
 198
 199 static const char * const i2c46_src[] = {
 200         "pclk5", "pll3_q", "ck_hsi", "ck_csi"
 201 };
 202
 203 static const char * const lptim1_src[] = {
 204         "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 205 };
 206
 207 static const char * const lptim23_src[] = {
 208         "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
 209 };
 210
 211 static const char * const lptim45_src[] = {
 212         "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 213 };
 214
 215 static const char * const usart1_src[] = {
 216         "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 217 };
 218
 219 static const char * const usart234578_src[] = {
 220         "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 221 };
 222
 223 static const char * const usart6_src[] = {
 224         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 225 };
 226
 227 static const char * const fdcan_src[] = {
 228         "ck_hse", "pll3_q", "pll4_q"
 229 };
 230
 231 static const char * const sai_src[] = {
 232         "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
 233 };
 234
 235 static const char * const sai2_src[] = {
 236         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
 237 };
 238
 239 static const char * const adc12_src[] = {
 240         "pll4_q", "ck_per"
 241 };
 242
 243 static const char * const dsi_src[] = {
 244         "ck_dsi_phy", "pll4_p"
 245 };
 246
 247 static const char * const rtc_src[] = {
 248         "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
 249 };
 250
 251 static const char * const mco1_src[] = {
 252         "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
 253 };
 254
 255 static const char * const mco2_src[] = {
 256         "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
 257 };
 258
 259 static const char * const ck_trace_src[] = {
 260         "ck_axi"
 261 };
 262
 263 static const struct clk_div_table axi_div_table[] = {
 264         { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
 265         { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
 266         { 0 },
 267 };
 268
 269 static const struct clk_div_table mcu_div_table[] = {
 270         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 271         { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
 272         { 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
 273         { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
 274         { 0 },
 275 };
 276
 277 static const struct clk_div_table apb_div_table[] = {
 278         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 279         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 280         { 0 },
 281 };
 282
 283 static const struct clk_div_table ck_trace_div_table[] = {
 284         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 285         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 286         { 0 },
 287 };
 288
 289 #define MAX_MUX_CLK 2
 290
 291 struct stm32_mmux {
 292         u8 nbr_clk;
 293         struct clk_hw *hws[MAX_MUX_CLK];
 294 };
 295
 296 struct stm32_clk_mmux {
 297         struct clk_mux mux;
 298         struct stm32_mmux *mmux;
 299 };
 300
 301 struct stm32_mgate {
 302         u8 nbr_clk;
 303         u32 flag;
 304 };
 305
 306 struct stm32_clk_mgate {
 307         struct clk_gate gate;
 308         struct stm32_mgate *mgate;
 309         u32 mask;
 310 };
 311
 312 struct clock_config {
 313         u32 id;
 314         const char *name;
 315         const char *parent_name;
 316         const char * const *parent_names;
 317         int num_parents;
 318         unsigned long flags;
 319         void *cfg;
 320         struct clk_hw * (*func)(struct device *dev,
 321                                 struct clk_hw_onecell_data *clk_data,
 322                                 void __iomem *base, spinlock_t *lock,
 323                                 const struct clock_config *cfg);
 324 };
 325
 326 #define NO_ID ~0
 327
 328 struct gate_cfg {
 329         u32 reg_off;
 330         u8 bit_idx;
 331         u8 gate_flags;
 332 };
 333
 334 struct fixed_factor_cfg {
 335         unsigned int mult;
 336         unsigned int div;
 337 };
 338
 339 struct div_cfg {
 340         u32 reg_off;
 341         u8 shift;
 342         u8 width;
 343         u8 div_flags;
 344         const struct clk_div_table *table;
 345 };
 346
 347 struct mux_cfg {
 348         u32 reg_off;
 349         u8 shift;
 350         u8 width;
 351         u8 mux_flags;
 352         u32 *table;
 353 };
 354
 355 struct stm32_gate_cfg {
 356         struct gate_cfg         *gate;
 357         struct stm32_mgate      *mgate;
 358         const struct clk_ops    *ops;
 359 };
 360
 361 struct stm32_div_cfg {
 362         struct div_cfg          *div;
 363         const struct clk_ops    *ops;
 364 };
 365
 366 struct stm32_mux_cfg {
 367         struct mux_cfg          *mux;
 368         struct stm32_mmux       *mmux;
 369         const struct clk_ops    *ops;
 370 };
 371
 372 /* STM32 Composite clock */
 373 struct stm32_composite_cfg {
 374         const struct stm32_gate_cfg     *gate;
 375         const struct stm32_div_cfg      *div;
 376         const struct stm32_mux_cfg      *mux;
 377 };
 378
 379 static struct clk_hw *
 380 _clk_hw_register_gate(struct device *dev,
 381                       struct clk_hw_onecell_data *clk_data,
 382                       void __iomem *base, spinlock_t *lock,
 383                       const struct clock_config *cfg)
 384 {
 385         struct gate_cfg *gate_cfg = cfg->cfg;
 386
 387         return clk_hw_register_gate(dev,
 388                                     cfg->name,
 389                                     cfg->parent_name,
 390                                     cfg->flags,
 391                                     gate_cfg->reg_off + base,
 392                                     gate_cfg->bit_idx,
 393                                     gate_cfg->gate_flags,
 394                                     lock);
 395 }
 396
 397 static struct clk_hw *
 398 _clk_hw_register_fixed_factor(struct device *dev,
 399                               struct clk_hw_onecell_data *clk_data,
 400                               void __iomem *base, spinlock_t *lock,
 401                               const struct clock_config *cfg)
 402 {
 403         struct fixed_factor_cfg *ff_cfg = cfg->cfg;
 404
 405         return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
 406                                             cfg->flags, ff_cfg->mult,
 407                                             ff_cfg->div);
 408 }
 409
 410 static struct clk_hw *
 411 _clk_hw_register_divider_table(struct device *dev,
 412                                struct clk_hw_onecell_data *clk_data,
 413                                void __iomem *base, spinlock_t *lock,
 414                                const struct clock_config *cfg)
 415 {
 416         struct div_cfg *div_cfg = cfg->cfg;
 417
 418         return clk_hw_register_divider_table(dev,
 419                                              cfg->name,
 420                                              cfg->parent_name,
 421                                              cfg->flags,
 422                                              div_cfg->reg_off + base,
 423                                              div_cfg->shift,
 424                                              div_cfg->width,
 425                                              div_cfg->div_flags,
 426                                              div_cfg->table,
 427                                              lock);
 428 }
 429
 430 static struct clk_hw *
 431 _clk_hw_register_mux(struct device *dev,
 432                      struct clk_hw_onecell_data *clk_data,
 433                      void __iomem *base, spinlock_t *lock,
 434                      const struct clock_config *cfg)
 435 {
 436         struct mux_cfg *mux_cfg = cfg->cfg;
 437
 438         return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
 439                                    cfg->num_parents, cfg->flags,
 440                                    mux_cfg->reg_off + base, mux_cfg->shift,
 441                                    mux_cfg->width, mux_cfg->mux_flags, lock);
 442 }
 443
 444 /* MP1 Gate clock with set & clear registers */
 445
 446 static int mp1_gate_clk_enable(struct clk_hw *hw)
 447 {
 448         if (!clk_gate_ops.is_enabled(hw))
 449                 clk_gate_ops.enable(hw);
 450
 451         return 0;
 452 }
 453
 454 static void mp1_gate_clk_disable(struct clk_hw *hw)
 455 {
 456         struct clk_gate *gate = to_clk_gate(hw);
 457         unsigned long flags = 0;
 458
 459         if (clk_gate_ops.is_enabled(hw)) {
 460                 spin_lock_irqsave(gate->lock, flags);
 461                 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
 462                 spin_unlock_irqrestore(gate->lock, flags);
 463         }
 464 }
 465
 466 static const struct clk_ops mp1_gate_clk_ops = {
 467         .enable         = mp1_gate_clk_enable,
 468         .disable        = mp1_gate_clk_disable,
 469         .is_enabled     = clk_gate_is_enabled,
 470 };
 471
 472 static struct clk_hw *_get_stm32_mux(void __iomem *base,
 473                                      const struct stm32_mux_cfg *cfg,
 474                                      spinlock_t *lock)
 475 {
 476         struct stm32_clk_mmux *mmux;
 477         struct clk_mux *mux;
 478         struct clk_hw *mux_hw;
 479
 480         if (cfg->mmux) {
 481                 mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
 482                 if (!mmux)
 483                         return ERR_PTR(-ENOMEM);
 484
 485                 mmux->mux.reg = cfg->mux->reg_off + base;
 486                 mmux->mux.shift = cfg->mux->shift;
 487                 mmux->mux.mask = (1 << cfg->mux->width) - 1;
 488                 mmux->mux.flags = cfg->mux->mux_flags;
 489                 mmux->mux.table = cfg->mux->table;
 490                 mmux->mux.lock = lock;
 491                 mmux->mmux = cfg->mmux;
 492                 mux_hw = &mmux->mux.hw;
 493                 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
 494
 495         } else {
 496                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 497                 if (!mux)
 498                         return ERR_PTR(-ENOMEM);
 499
 500                 mux->reg = cfg->mux->reg_off + base;
 501                 mux->shift = cfg->mux->shift;
 502                 mux->mask = (1 << cfg->mux->width) - 1;
 503                 mux->flags = cfg->mux->mux_flags;
 504                 mux->table = cfg->mux->table;
 505                 mux->lock = lock;
 506                 mux_hw = &mux->hw;
 507         }
 508
 509         return mux_hw;
 510 }
 511
 512 static struct clk_hw *_get_stm32_div(void __iomem *base,
 513                                      const struct stm32_div_cfg *cfg,
 514                                      spinlock_t *lock)
 515 {
 516         struct clk_divider *div;
 517
 518         div = kzalloc(sizeof(*div), GFP_KERNEL);
 519
 520         if (!div)
 521                 return ERR_PTR(-ENOMEM);
 522
 523         div->reg = cfg->div->reg_off + base;
 524         div->shift = cfg->div->shift;
 525         div->width = cfg->div->width;
 526         div->flags = cfg->div->div_flags;
 527         div->table = cfg->div->table;
 528         div->lock = lock;
 529
 530         return &div->hw;
 531 }
 532
 533 static struct clk_hw *
 534 _get_stm32_gate(void __iomem *base,
 535                 const struct stm32_gate_cfg *cfg, spinlock_t *lock)
 536 {
 537         struct stm32_clk_mgate *mgate;
 538         struct clk_gate *gate;
 539         struct clk_hw *gate_hw;
 540
 541         if (cfg->mgate) {
 542                 mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
 543                 if (!mgate)
 544                         return ERR_PTR(-ENOMEM);
 545
 546                 mgate->gate.reg = cfg->gate->reg_off + base;
 547                 mgate->gate.bit_idx = cfg->gate->bit_idx;
 548                 mgate->gate.flags = cfg->gate->gate_flags;
 549                 mgate->gate.lock = lock;
 550                 mgate->mask = BIT(cfg->mgate->nbr_clk++);
 551
 552                 mgate->mgate = cfg->mgate;
 553
 554                 gate_hw = &mgate->gate.hw;
 555
 556         } else {
 557                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 558                 if (!gate)
 559                         return ERR_PTR(-ENOMEM);
 560
 561                 gate->reg = cfg->gate->reg_off + base;
 562                 gate->bit_idx = cfg->gate->bit_idx;
 563                 gate->flags = cfg->gate->gate_flags;
 564                 gate->lock = lock;
 565
 566                 gate_hw = &gate->hw;
 567         }
 568
 569         return gate_hw;
 570 }
 571
 572 static struct clk_hw *
 573 clk_stm32_register_gate_ops(struct device *dev,
 574                             const char *name,
 575                             const char *parent_name,
 576                             unsigned long flags,
 577                             void __iomem *base,
 578                             const struct stm32_gate_cfg *cfg,
 579                             spinlock_t *lock)
 580 {
 581         struct clk_init_data init = { NULL };
 582         struct clk_gate *gate;
 583         struct clk_hw *hw;
 584         int ret;
 585
 586         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 587         if (!gate)
 588                 return ERR_PTR(-ENOMEM);
 589
 590         init.name = name;
 591         init.parent_names = &parent_name;
 592         init.num_parents = 1;
 593         init.flags = flags;
 594
 595         init.ops = &clk_gate_ops;
 596
 597         if (cfg->ops)
 598                 init.ops = cfg->ops;
 599
 600         hw = _get_stm32_gate(base, cfg, lock);
 601         if (IS_ERR(hw))
 602                 return ERR_PTR(-ENOMEM);
 603
 604         hw->init = &init;
 605
 606         ret = clk_hw_register(dev, hw);
 607         if (ret) {
 608                 kfree(gate);
 609                 hw = ERR_PTR(ret);
 610         }
 611
 612         return hw;
 613 }
 614
 615 static struct clk_hw *
 616 clk_stm32_register_composite(struct device *dev,
 617                              const char *name, const char * const *parent_names,
 618                              int num_parents, void __iomem *base,
 619                              const struct stm32_composite_cfg *cfg,
 620                              unsigned long flags, spinlock_t *lock)
 621 {
 622         const struct clk_ops *mux_ops, *div_ops, *gate_ops;
 623         struct clk_hw *mux_hw, *div_hw, *gate_hw;
 624
 625         mux_hw = NULL;
 626         div_hw = NULL;
 627         gate_hw = NULL;
 628         mux_ops = NULL;
 629         div_ops = NULL;
 630         gate_ops = NULL;
 631
 632         if (cfg->mux) {
 633                 mux_hw = _get_stm32_mux(base, cfg->mux, lock);
 634
 635                 if (!IS_ERR(mux_hw)) {
 636                         mux_ops = &clk_mux_ops;
 637
 638                         if (cfg->mux->ops)
 639                                 mux_ops = cfg->mux->ops;
 640                 }
 641         }
 642
 643         if (cfg->div) {
 644                 div_hw = _get_stm32_div(base, cfg->div, lock);
 645
 646                 if (!IS_ERR(div_hw)) {
 647                         div_ops = &clk_divider_ops;
 648
 649                         if (cfg->div->ops)
 650                                 div_ops = cfg->div->ops;
 651                 }
 652         }
 653
 654         if (cfg->gate) {
 655                 gate_hw = _get_stm32_gate(base, cfg->gate, lock);
 656
 657                 if (!IS_ERR(gate_hw)) {
 658                         gate_ops = &clk_gate_ops;
 659
 660                         if (cfg->gate->ops)
 661                                 gate_ops = cfg->gate->ops;
 662                 }
 663         }
 664
 665         return clk_hw_register_composite(dev, name, parent_names, num_parents,
 666                                        mux_hw, mux_ops, div_hw, div_ops,
 667                                        gate_hw, gate_ops, flags);
 668 }
 669
 670 #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
 671
 672 static int mp1_mgate_clk_enable(struct clk_hw *hw)
 673 {
 674         struct clk_gate *gate = to_clk_gate(hw);
 675         struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 676
 677         clk_mgate->mgate->flag |= clk_mgate->mask;
 678
 679         mp1_gate_clk_enable(hw);
 680
 681         return  0;
 682 }
 683
 684 static void mp1_mgate_clk_disable(struct clk_hw *hw)
 685 {
 686         struct clk_gate *gate = to_clk_gate(hw);
 687         struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 688
 689         clk_mgate->mgate->flag &= ~clk_mgate->mask;
 690
 691         if (clk_mgate->mgate->flag == 0)
 692                 mp1_gate_clk_disable(hw);
 693 }
 694
 695 static const struct clk_ops mp1_mgate_clk_ops = {
 696         .enable         = mp1_mgate_clk_enable,
 697         .disable        = mp1_mgate_clk_disable,
 698         .is_enabled     = clk_gate_is_enabled,
 699
 700 };
 701
 702 #define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
 703
 704 static u8 clk_mmux_get_parent(struct clk_hw *hw)
 705 {
 706         return clk_mux_ops.get_parent(hw);
 707 }
 708
 709 static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
 710 {
 711         struct clk_mux *mux = to_clk_mux(hw);
 712         struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
 713         struct clk_hw *hwp;
 714         int ret, n;
 715
 716         ret = clk_mux_ops.set_parent(hw, index);
 717         if (ret)
 718                 return ret;
 719
 720         hwp = clk_hw_get_parent(hw);
 721
 722         for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
 723                 if (clk_mmux->mmux->hws[n] != hw)
 724                         clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
 725
 726         return 0;
 727 }
 728
 729 static const struct clk_ops clk_mmux_ops = {
 730         .get_parent     = clk_mmux_get_parent,
 731         .set_parent     = clk_mmux_set_parent,
 732         .determine_rate = __clk_mux_determine_rate,
 733 };
 734
 735 /* STM32 PLL */
 736 struct stm32_pll_obj {
 737         /* lock pll enable/disable registers */
 738         spinlock_t *lock;
 739         void __iomem *reg;
 740         struct clk_hw hw;
 741 };
 742
 743 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
 744
 745 #define PLL_ON          BIT(0)
 746 #define PLL_RDY         BIT(1)
 747 #define DIVN_MASK       0x1FF
 748 #define DIVM_MASK       0x3F
 749 #define DIVM_SHIFT      16
 750 #define DIVN_SHIFT      0
 751 #define FRAC_OFFSET     0xC
 752 #define FRAC_MASK       0x1FFF
 753 #define FRAC_SHIFT      3
 754 #define FRACLE          BIT(16)
 755
 756 static int __pll_is_enabled(struct clk_hw *hw)
 757 {
 758         struct stm32_pll_obj *clk_elem = to_pll(hw);
 759
 760         return readl_relaxed(clk_elem->reg) & PLL_ON;
 761 }
 762
 763 #define TIMEOUT 5
 764
 765 static int pll_enable(struct clk_hw *hw)
 766 {
 767         struct stm32_pll_obj *clk_elem = to_pll(hw);
 768         u32 reg;
 769         unsigned long flags = 0;
 770         unsigned int timeout = TIMEOUT;
 771         int bit_status = 0;
 772
 773         spin_lock_irqsave(clk_elem->lock, flags);
 774
 775         if (__pll_is_enabled(hw))
 776                 goto unlock;
 777
 778         reg = readl_relaxed(clk_elem->reg);
 779         reg |= PLL_ON;
 780         writel_relaxed(reg, clk_elem->reg);
 781
 782         /* We can't use readl_poll_timeout() because we can be blocked if
 783          * someone enables this clock before clocksource changes.
 784          * Only jiffies counter is available. Jiffies are incremented by
 785          * interruptions and enable op does not allow to be interrupted.
 786          */
 787         do {
 788                 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
 789
 790                 if (bit_status)
 791                         udelay(120);
 792
 793         } while (bit_status && --timeout);
 794
 795 unlock:
 796         spin_unlock_irqrestore(clk_elem->lock, flags);
 797
 798         return bit_status;
 799 }
 800
 801 static void pll_disable(struct clk_hw *hw)
 802 {
 803         struct stm32_pll_obj *clk_elem = to_pll(hw);
 804         u32 reg;
 805         unsigned long flags = 0;
 806
 807         spin_lock_irqsave(clk_elem->lock, flags);
 808
 809         reg = readl_relaxed(clk_elem->reg);
 810         reg &= ~PLL_ON;
 811         writel_relaxed(reg, clk_elem->reg);
 812
 813         spin_unlock_irqrestore(clk_elem->lock, flags);
 814 }
 815
 816 static u32 pll_frac_val(struct clk_hw *hw)
 817 {
 818         struct stm32_pll_obj *clk_elem = to_pll(hw);
 819         u32 reg, frac = 0;
 820
 821         reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
 822         if (reg & FRACLE)
 823                 frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
 824
 825         return frac;
 826 }
 827
 828 static unsigned long pll_recalc_rate(struct clk_hw *hw,
 829                                      unsigned long parent_rate)
 830 {
 831         struct stm32_pll_obj *clk_elem = to_pll(hw);
 832         u32 reg;
 833         u32 frac, divm, divn;
 834         u64 rate, rate_frac = 0;
 835
 836         reg = readl_relaxed(clk_elem->reg + 4);
 837
 838         divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
 839         divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
 840         rate = (u64)parent_rate * divn;
 841
 842         do_div(rate, divm);
 843
 844         frac = pll_frac_val(hw);
 845         if (frac) {
 846                 rate_frac = (u64)parent_rate * (u64)frac;
 847                 do_div(rate_frac, (divm * 8192));
 848         }
 849
 850         return rate + rate_frac;
 851 }
 852
 853 static int pll_is_enabled(struct clk_hw *hw)
 854 {
 855         struct stm32_pll_obj *clk_elem = to_pll(hw);
 856         unsigned long flags = 0;
 857         int ret;
 858
 859         spin_lock_irqsave(clk_elem->lock, flags);
 860         ret = __pll_is_enabled(hw);
 861         spin_unlock_irqrestore(clk_elem->lock, flags);
 862
 863         return ret;
 864 }
 865
 866 static const struct clk_ops pll_ops = {
 867         .enable         = pll_enable,
 868         .disable        = pll_disable,
 869         .recalc_rate    = pll_recalc_rate,
 870         .is_enabled     = pll_is_enabled,
 871 };
 872
 873 static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
 874                                        const char *parent_name,
 875                                        void __iomem *reg,
 876                                        unsigned long flags,
 877                                        spinlock_t *lock)
 878 {
 879         struct stm32_pll_obj *element;
 880         struct clk_init_data init;
 881         struct clk_hw *hw;
 882         int err;
 883
 884         element = kzalloc(sizeof(*element), GFP_KERNEL);
 885         if (!element)
 886                 return ERR_PTR(-ENOMEM);
 887
 888         init.name = name;
 889         init.ops = &pll_ops;
 890         init.flags = flags;
 891         init.parent_names = &parent_name;
 892         init.num_parents = 1;
 893
 894         element->hw.init = &init;
 895         element->reg = reg;
 896         element->lock = lock;
 897
 898         hw = &element->hw;
 899         err = clk_hw_register(dev, hw);
 900
 901         if (err) {
 902                 kfree(element);
 903                 return ERR_PTR(err);
 904         }
 905
 906         return hw;
 907 }
 908
 909 /* Kernel Timer */
 910 struct timer_cker {
 911         /* lock the kernel output divider register */
 912         spinlock_t *lock;
 913         void __iomem *apbdiv;
 914         void __iomem *timpre;
 915         struct clk_hw hw;
 916 };
 917
 918 #define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
 919
 920 #define APB_DIV_MASK 0x07
 921 #define TIM_PRE_MASK 0x01
 922
 923 static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
 924                                 unsigned long parent_rate)
 925 {
 926         struct timer_cker *tim_ker = to_timer_cker(hw);
 927         u32 prescaler;
 928         unsigned int mult = 0;
 929
 930         prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
 931         if (prescaler < 2)
 932                 return 1;
 933
 934         mult = 2;
 935
 936         if (rate / parent_rate >= 4)
 937                 mult = 4;
 938
 939         return mult;
 940 }
 941
 942 static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
 943                                  unsigned long *parent_rate)
 944 {
 945         unsigned long factor = __bestmult(hw, rate, *parent_rate);
 946
 947         return *parent_rate * factor;
 948 }
 949
 950 static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
 951                               unsigned long parent_rate)
 952 {
 953         struct timer_cker *tim_ker = to_timer_cker(hw);
 954         unsigned long flags = 0;
 955         unsigned long factor = __bestmult(hw, rate, parent_rate);
 956         int ret = 0;
 957
 958         spin_lock_irqsave(tim_ker->lock, flags);
 959
 960         switch (factor) {
 961         case 1:
 962                 break;
 963         case 2:
 964                 writel_relaxed(0, tim_ker->timpre);
 965                 break;
 966         case 4:
 967                 writel_relaxed(1, tim_ker->timpre);
 968                 break;
 969         default:
 970                 ret = -EINVAL;
 971         }
 972         spin_unlock_irqrestore(tim_ker->lock, flags);
 973
 974         return ret;
 975 }
 976
 977 static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
 978                                            unsigned long parent_rate)
 979 {
 980         struct timer_cker *tim_ker = to_timer_cker(hw);
 981         u32 prescaler, timpre;
 982         u32 mul;
 983
 984         prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
 985
 986         timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
 987
 988         if (!prescaler)
 989                 return parent_rate;
 990
 991         mul = (timpre + 1) * 2;
 992
 993         return parent_rate * mul;
 994 }
 995
 996 static const struct clk_ops timer_ker_ops = {
 997         .recalc_rate    = timer_ker_recalc_rate,
 998         .round_rate     = timer_ker_round_rate,
 999         .set_rate       = timer_ker_set_rate,
1000
1001 };
1002
1003 static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
1004                                          const char *parent_name,
1005                                          unsigned long flags,
1006                                          void __iomem *apbdiv,
1007                                          void __iomem *timpre,
1008                                          spinlock_t *lock)
1009 {
1010         struct timer_cker *tim_ker;
1011         struct clk_init_data init;
1012         struct clk_hw *hw;
1013         int err;
1014
1015         tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL);
1016         if (!tim_ker)
1017                 return ERR_PTR(-ENOMEM);
1018
1019         init.name = name;
1020         init.ops = &timer_ker_ops;
1021         init.flags = flags;
1022         init.parent_names = &parent_name;
1023         init.num_parents = 1;
1024
1025         tim_ker->hw.init = &init;
1026         tim_ker->lock = lock;
1027         tim_ker->apbdiv = apbdiv;
1028         tim_ker->timpre = timpre;
1029
1030         hw = &tim_ker->hw;
1031         err = clk_hw_register(dev, hw);
1032
1033         if (err) {
1034                 kfree(tim_ker);
1035                 return ERR_PTR(err);
1036         }
1037
1038         return hw;
1039 }
1040
1041 struct stm32_pll_cfg {
1042         u32 offset;
1043 };
1044
1045 static struct clk_hw *_clk_register_pll(struct device *dev,
1046                                         struct clk_hw_onecell_data *clk_data,
1047                                         void __iomem *base, spinlock_t *lock,
1048                                         const struct clock_config *cfg)
1049 {
1050         struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1051
1052         return clk_register_pll(dev, cfg->name, cfg->parent_name,
1053                                 base + stm_pll_cfg->offset, cfg->flags, lock);
1054 }
1055
1056 struct stm32_cktim_cfg {
1057         u32 offset_apbdiv;
1058         u32 offset_timpre;
1059 };
1060
1061 static struct clk_hw *_clk_register_cktim(struct device *dev,
1062                                           struct clk_hw_onecell_data *clk_data,
1063                                           void __iomem *base, spinlock_t *lock,
1064                                           const struct clock_config *cfg)
1065 {
1066         struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
1067
1068         return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
1069                                   cktim_cfg->offset_apbdiv + base,
1070                                   cktim_cfg->offset_timpre + base, lock);
1071 }
1072
1073 static struct clk_hw *
1074 _clk_stm32_register_gate(struct device *dev,
1075                          struct clk_hw_onecell_data *clk_data,
1076                          void __iomem *base, spinlock_t *lock,
1077                          const struct clock_config *cfg)
1078 {
1079         return clk_stm32_register_gate_ops(dev,
1080                                     cfg->name,
1081                                     cfg->parent_name,
1082                                     cfg->flags,
1083                                     base,
1084                                     cfg->cfg,
1085                                     lock);
1086 }
1087
1088 static struct clk_hw *
1089 _clk_stm32_register_composite(struct device *dev,
1090                               struct clk_hw_onecell_data *clk_data,
1091                               void __iomem *base, spinlock_t *lock,
1092                               const struct clock_config *cfg)
1093 {
1094         return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
1095                                             cfg->num_parents, base, cfg->cfg,
1096                                             cfg->flags, lock);
1097 }
1098
1099 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1100 {\
1101         .id             = _id,\
1102         .name           = _name,\
1103         .parent_name    = _parent,\
1104         .flags          = _flags,\
1105         .cfg            =  &(struct gate_cfg) {\
1106                 .reg_off        = _offset,\
1107                 .bit_idx        = _bit_idx,\
1108                 .gate_flags     = _gate_flags,\
1109         },\
1110         .func           = _clk_hw_register_gate,\
1111 }
1112
1113 #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
1114 {\
1115         .id             = _id,\
1116         .name           = _name,\
1117         .parent_name    = _parent,\
1118         .flags          = _flags,\
1119         .cfg            =  &(struct fixed_factor_cfg) {\
1120                 .mult = _mult,\
1121                 .div = _div,\
1122         },\
1123         .func           = _clk_hw_register_fixed_factor,\
1124 }
1125
1126 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1127                   _div_flags, _div_table)\
1128 {\
1129         .id             = _id,\
1130         .name           = _name,\
1131         .parent_name    = _parent,\
1132         .flags          = _flags,\
1133         .cfg            =  &(struct div_cfg) {\
1134                 .reg_off        = _offset,\
1135                 .shift          = _shift,\
1136                 .width          = _width,\
1137                 .div_flags      = _div_flags,\
1138                 .table          = _div_table,\
1139         },\
1140         .func           = _clk_hw_register_divider_table,\
1141 }
1142
1143 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
1144         DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1145                   _div_flags, NULL)
1146
1147 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
1148 {\
1149         .id             = _id,\
1150         .name           = _name,\
1151         .parent_names   = _parents,\
1152         .num_parents    = ARRAY_SIZE(_parents),\
1153         .flags          = _flags,\
1154         .cfg            =  &(struct mux_cfg) {\
1155                 .reg_off        = _offset,\
1156                 .shift          = _shift,\
1157                 .width          = _width,\
1158                 .mux_flags      = _mux_flags,\
1159         },\
1160         .func           = _clk_hw_register_mux,\
1161 }
1162
1163 #define PLL(_id, _name, _parent, _flags, _offset)\
1164 {\
1165         .id             = _id,\
1166         .name           = _name,\
1167         .parent_name    = _parent,\
1168         .flags          = _flags,\
1169         .cfg            =  &(struct stm32_pll_cfg) {\
1170                 .offset = _offset,\
1171         },\
1172         .func           = _clk_register_pll,\
1173 }
1174
1175 #define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
1176 {\
1177         .id             = NO_ID,\
1178         .name           = _name,\
1179         .parent_name    = _parent,\
1180         .flags          = _flags,\
1181         .cfg            =  &(struct stm32_cktim_cfg) {\
1182                 .offset_apbdiv = _offset_apbdiv,\
1183                 .offset_timpre = _offset_timpre,\
1184         },\
1185         .func           = _clk_register_cktim,\
1186 }
1187
1188 #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
1189                   GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
1190                            _offset_set, _bit_idx, 0)
1191
1192 /* STM32 GATE */
1193 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\
1194 {\
1195         .id             = _id,\
1196         .name           = _name,\
1197         .parent_name    = _parent,\
1198         .flags          = _flags,\
1199         .cfg            = (struct stm32_gate_cfg *) {_gate},\
1200         .func           = _clk_stm32_register_gate,\
1201 }
1202
1203 #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
1204         (&(struct stm32_gate_cfg) {\
1205                 &(struct gate_cfg) {\
1206                         .reg_off        = _gate_offset,\
1207                         .bit_idx        = _gate_bit_idx,\
1208                         .gate_flags     = _gate_flags,\
1209                 },\
1210                 .mgate          = _mgate,\
1211                 .ops            = _ops,\
1212         })
1213
1214 #define _STM32_MGATE(_mgate)\
1215         (&per_gate_cfg[_mgate])
1216
1217 #define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
1218         _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1219                     NULL, NULL)\
1220
1221 #define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
1222         _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1223                     NULL, &mp1_gate_clk_ops)\
1224
1225 #define _MGATE_MP1(_mgate)\
1226         .gate = &per_gate_cfg[_mgate]
1227
1228 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1229         STM32_GATE(_id, _name, _parent, _flags,\
1230                    _GATE_MP1(_offset, _bit_idx, _gate_flags))
1231
1232 #define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
1233         STM32_GATE(_id, _name, _parent, _flags,\
1234                    _STM32_MGATE(_mgate))
1235
1236 #define _STM32_DIV(_div_offset, _div_shift, _div_width,\
1237                    _div_flags, _div_table, _ops)\
1238         .div = &(struct stm32_div_cfg) {\
1239                 &(struct div_cfg) {\
1240                         .reg_off        = _div_offset,\
1241                         .shift          = _div_shift,\
1242                         .width          = _div_width,\
1243                         .div_flags      = _div_flags,\
1244                         .table          = _div_table,\
1245                 },\
1246                 .ops            = _ops,\
1247         }
1248
1249 #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1250         _STM32_DIV(_div_offset, _div_shift, _div_width,\
1251                    _div_flags, _div_table, NULL)\
1252
1253 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
1254         .mux = &(struct stm32_mux_cfg) {\
1255                 &(struct mux_cfg) {\
1256                         .reg_off        = _offset,\
1257                         .shift          = _shift,\
1258                         .width          = _width,\
1259                         .mux_flags      = _mux_flags,\
1260                         .table          = NULL,\
1261                 },\
1262                 .mmux           = _mmux,\
1263                 .ops            = _ops,\
1264         }
1265
1266 #define _MUX(_offset, _shift, _width, _mux_flags)\
1267         _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
1268
1269 #define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
1270
1271 #define PARENT(_parent) ((const char *[]) { _parent})
1272
1273 #define _NO_MUX .mux = NULL
1274 #define _NO_DIV .div = NULL
1275 #define _NO_GATE .gate = NULL
1276
1277 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
1278 {\
1279         .id             = _id,\
1280         .name           = _name,\
1281         .parent_names   = _parents,\
1282         .num_parents    = ARRAY_SIZE(_parents),\
1283         .flags          = _flags,\
1284         .cfg            = &(struct stm32_composite_cfg) {\
1285                 _gate,\
1286                 _mux,\
1287                 _div,\
1288         },\
1289         .func           = _clk_stm32_register_composite,\
1290 }
1291
1292 #define PCLK(_id, _name, _parent, _flags, _mgate)\
1293         MGATE_MP1(_id, _name, _parent, _flags, _mgate)
1294
1295 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
1296              COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\
1297                   _MGATE_MP1(_mgate),\
1298                   _MMUX(_mmux),\
1299                   _NO_DIV)
1300
1301 enum {
1302         G_SAI1,
1303         G_SAI2,
1304         G_SAI3,
1305         G_SAI4,
1306         G_SPI1,
1307         G_SPI2,
1308         G_SPI3,
1309         G_SPI4,
1310         G_SPI5,
1311         G_SPI6,
1312         G_SPDIF,
1313         G_I2C1,
1314         G_I2C2,
1315         G_I2C3,
1316         G_I2C4,
1317         G_I2C5,
1318         G_I2C6,
1319         G_USART2,
1320         G_UART4,
1321         G_USART3,
1322         G_UART5,
1323         G_USART1,
1324         G_USART6,
1325         G_UART7,
1326         G_UART8,
1327         G_LPTIM1,
1328         G_LPTIM2,
1329         G_LPTIM3,
1330         G_LPTIM4,
1331         G_LPTIM5,
1332         G_LTDC,
1333         G_DSI,
1334         G_QSPI,
1335         G_FMC,
1336         G_SDMMC1,
1337         G_SDMMC2,
1338         G_SDMMC3,
1339         G_USBO,
1340         G_USBPHY,
1341         G_RNG1,
1342         G_RNG2,
1343         G_FDCAN,
1344         G_DAC12,
1345         G_CEC,
1346         G_ADC12,
1347         G_GPU,
1348         G_STGEN,
1349         G_DFSDM,
1350         G_ADFSDM,
1351         G_TIM2,
1352         G_TIM3,
1353         G_TIM4,
1354         G_TIM5,
1355         G_TIM6,
1356         G_TIM7,
1357         G_TIM12,
1358         G_TIM13,
1359         G_TIM14,
1360         G_MDIO,
1361         G_TIM1,
1362         G_TIM8,
1363         G_TIM15,
1364         G_TIM16,
1365         G_TIM17,
1366         G_SYSCFG,
1367         G_VREF,
1368         G_TMPSENS,
1369         G_PMBCTRL,
1370         G_HDP,
1371         G_IWDG2,
1372         G_STGENRO,
1373         G_DMA1,
1374         G_DMA2,
1375         G_DMAMUX,
1376         G_DCMI,
1377         G_CRYP2,
1378         G_HASH2,
1379         G_CRC2,
1380         G_HSEM,
1381         G_IPCC,
1382         G_GPIOA,
1383         G_GPIOB,
1384         G_GPIOC,
1385         G_GPIOD,
1386         G_GPIOE,
1387         G_GPIOF,
1388         G_GPIOG,
1389         G_GPIOH,
1390         G_GPIOI,
1391         G_GPIOJ,
1392         G_GPIOK,
1393         G_MDMA,
1394         G_ETHCK,
1395         G_ETHTX,
1396         G_ETHRX,
1397         G_ETHMAC,
1398         G_CRC1,
1399         G_USBH,
1400         G_ETHSTP,
1401         G_RTCAPB,
1402         G_TZC1,
1403         G_TZC2,
1404         G_TZPC,
1405         G_IWDG1,
1406         G_BSEC,
1407         G_GPIOZ,
1408         G_CRYP1,
1409         G_HASH1,
1410         G_BKPSRAM,
1411
1412         G_LAST
1413 };
1414
1415 static struct stm32_mgate mp1_mgate[G_LAST];
1416
1417 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1418                _mgate, _ops)\
1419         [_id] = {\
1420                 &(struct gate_cfg) {\
1421                         .reg_off        = _gate_offset,\
1422                         .bit_idx        = _gate_bit_idx,\
1423                         .gate_flags     = _gate_flags,\
1424                 },\
1425                 .mgate          = _mgate,\
1426                 .ops            = _ops,\
1427         }
1428
1429 #define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1430         _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1431                NULL, &mp1_gate_clk_ops)
1432
1433 #define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1434         _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1435                &mp1_mgate[_id], &mp1_mgate_clk_ops)
1436
1437 /* Peripheral gates */
1438 static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1439         /* Multi gates */
1440         K_GATE(G_MDIO,          RCC_APB1ENSETR, 31, 0),
1441         K_MGATE(G_DAC12,        RCC_APB1ENSETR, 29, 0),
1442         K_MGATE(G_CEC,          RCC_APB1ENSETR, 27, 0),
1443         K_MGATE(G_SPDIF,        RCC_APB1ENSETR, 26, 0),
1444         K_MGATE(G_I2C5,         RCC_APB1ENSETR, 24, 0),
1445         K_MGATE(G_I2C3,         RCC_APB1ENSETR, 23, 0),
1446         K_MGATE(G_I2C2,         RCC_APB1ENSETR, 22, 0),
1447         K_MGATE(G_I2C1,         RCC_APB1ENSETR, 21, 0),
1448         K_MGATE(G_UART8,        RCC_APB1ENSETR, 19, 0),
1449         K_MGATE(G_UART7,        RCC_APB1ENSETR, 18, 0),
1450         K_MGATE(G_UART5,        RCC_APB1ENSETR, 17, 0),
1451         K_MGATE(G_UART4,        RCC_APB1ENSETR, 16, 0),
1452         K_MGATE(G_USART3,       RCC_APB1ENSETR, 15, 0),
1453         K_MGATE(G_USART2,       RCC_APB1ENSETR, 14, 0),
1454         K_MGATE(G_SPI3,         RCC_APB1ENSETR, 12, 0),
1455         K_MGATE(G_SPI2,         RCC_APB1ENSETR, 11, 0),
1456         K_MGATE(G_LPTIM1,       RCC_APB1ENSETR, 9, 0),
1457         K_GATE(G_TIM14,         RCC_APB1ENSETR, 8, 0),
1458         K_GATE(G_TIM13,         RCC_APB1ENSETR, 7, 0),
1459         K_GATE(G_TIM12,         RCC_APB1ENSETR, 6, 0),
1460         K_GATE(G_TIM7,          RCC_APB1ENSETR, 5, 0),
1461         K_GATE(G_TIM6,          RCC_APB1ENSETR, 4, 0),
1462         K_GATE(G_TIM5,          RCC_APB1ENSETR, 3, 0),
1463         K_GATE(G_TIM4,          RCC_APB1ENSETR, 2, 0),
1464         K_GATE(G_TIM3,          RCC_APB1ENSETR, 1, 0),
1465         K_GATE(G_TIM2,          RCC_APB1ENSETR, 0, 0),
1466
1467         K_MGATE(G_FDCAN,        RCC_APB2ENSETR, 24, 0),
1468         K_GATE(G_ADFSDM,        RCC_APB2ENSETR, 21, 0),
1469         K_GATE(G_DFSDM,         RCC_APB2ENSETR, 20, 0),
1470         K_MGATE(G_SAI3,         RCC_APB2ENSETR, 18, 0),
1471         K_MGATE(G_SAI2,         RCC_APB2ENSETR, 17, 0),
1472         K_MGATE(G_SAI1,         RCC_APB2ENSETR, 16, 0),
1473         K_MGATE(G_USART6,       RCC_APB2ENSETR, 13, 0),
1474         K_MGATE(G_SPI5,         RCC_APB2ENSETR, 10, 0),
1475         K_MGATE(G_SPI4,         RCC_APB2ENSETR, 9, 0),
1476         K_MGATE(G_SPI1,         RCC_APB2ENSETR, 8, 0),
1477         K_GATE(G_TIM17,         RCC_APB2ENSETR, 4, 0),
1478         K_GATE(G_TIM16,         RCC_APB2ENSETR, 3, 0),
1479         K_GATE(G_TIM15,         RCC_APB2ENSETR, 2, 0),
1480         K_GATE(G_TIM8,          RCC_APB2ENSETR, 1, 0),
1481         K_GATE(G_TIM1,          RCC_APB2ENSETR, 0, 0),
1482
1483         K_GATE(G_HDP,           RCC_APB3ENSETR, 20, 0),
1484         K_GATE(G_PMBCTRL,       RCC_APB3ENSETR, 17, 0),
1485         K_GATE(G_TMPSENS,       RCC_APB3ENSETR, 16, 0),
1486         K_GATE(G_VREF,          RCC_APB3ENSETR, 13, 0),
1487         K_GATE(G_SYSCFG,        RCC_APB3ENSETR, 11, 0),
1488         K_MGATE(G_SAI4,         RCC_APB3ENSETR, 8, 0),
1489         K_MGATE(G_LPTIM5,       RCC_APB3ENSETR, 3, 0),
1490         K_MGATE(G_LPTIM4,       RCC_APB3ENSETR, 2, 0),
1491         K_MGATE(G_LPTIM3,       RCC_APB3ENSETR, 1, 0),
1492         K_MGATE(G_LPTIM2,       RCC_APB3ENSETR, 0, 0),
1493
1494         K_GATE(G_STGENRO,       RCC_APB4ENSETR, 20, 0),
1495         K_MGATE(G_USBPHY,       RCC_APB4ENSETR, 16, 0),
1496         K_GATE(G_IWDG2,         RCC_APB4ENSETR, 15, 0),
1497         K_MGATE(G_DSI,          RCC_APB4ENSETR, 4, 0),
1498         K_MGATE(G_LTDC,         RCC_APB4ENSETR, 0, 0),
1499
1500         K_GATE(G_STGEN,         RCC_APB5ENSETR, 20, 0),
1501         K_GATE(G_BSEC,          RCC_APB5ENSETR, 16, 0),
1502         K_GATE(G_IWDG1,         RCC_APB5ENSETR, 15, 0),
1503         K_GATE(G_TZPC,          RCC_APB5ENSETR, 13, 0),
1504         K_GATE(G_TZC2,          RCC_APB5ENSETR, 12, 0),
1505         K_GATE(G_TZC1,          RCC_APB5ENSETR, 11, 0),
1506         K_GATE(G_RTCAPB,        RCC_APB5ENSETR, 8, 0),
1507         K_MGATE(G_USART1,       RCC_APB5ENSETR, 4, 0),
1508         K_MGATE(G_I2C6,         RCC_APB5ENSETR, 3, 0),
1509         K_MGATE(G_I2C4,         RCC_APB5ENSETR, 2, 0),
1510         K_MGATE(G_SPI6,         RCC_APB5ENSETR, 0, 0),
1511
1512         K_MGATE(G_SDMMC3,       RCC_AHB2ENSETR, 16, 0),
1513         K_MGATE(G_USBO,         RCC_AHB2ENSETR, 8, 0),
1514         K_MGATE(G_ADC12,        RCC_AHB2ENSETR, 5, 0),
1515         K_GATE(G_DMAMUX,        RCC_AHB2ENSETR, 2, 0),
1516         K_GATE(G_DMA2,          RCC_AHB2ENSETR, 1, 0),
1517         K_GATE(G_DMA1,          RCC_AHB2ENSETR, 0, 0),
1518
1519         K_GATE(G_IPCC,          RCC_AHB3ENSETR, 12, 0),
1520         K_GATE(G_HSEM,          RCC_AHB3ENSETR, 11, 0),
1521         K_GATE(G_CRC2,          RCC_AHB3ENSETR, 7, 0),
1522         K_MGATE(G_RNG2,         RCC_AHB3ENSETR, 6, 0),
1523         K_GATE(G_HASH2,         RCC_AHB3ENSETR, 5, 0),
1524         K_GATE(G_CRYP2,         RCC_AHB3ENSETR, 4, 0),
1525         K_GATE(G_DCMI,          RCC_AHB3ENSETR, 0, 0),
1526
1527         K_GATE(G_GPIOK,         RCC_AHB4ENSETR, 10, 0),
1528         K_GATE(G_GPIOJ,         RCC_AHB4ENSETR, 9, 0),
1529         K_GATE(G_GPIOI,         RCC_AHB4ENSETR, 8, 0),
1530         K_GATE(G_GPIOH,         RCC_AHB4ENSETR, 7, 0),
1531         K_GATE(G_GPIOG,         RCC_AHB4ENSETR, 6, 0),
1532         K_GATE(G_GPIOF,         RCC_AHB4ENSETR, 5, 0),
1533         K_GATE(G_GPIOE,         RCC_AHB4ENSETR, 4, 0),
1534         K_GATE(G_GPIOD,         RCC_AHB4ENSETR, 3, 0),
1535         K_GATE(G_GPIOC,         RCC_AHB4ENSETR, 2, 0),
1536         K_GATE(G_GPIOB,         RCC_AHB4ENSETR, 1, 0),
1537         K_GATE(G_GPIOA,         RCC_AHB4ENSETR, 0, 0),
1538
1539         K_GATE(G_BKPSRAM,       RCC_AHB5ENSETR, 8, 0),
1540         K_MGATE(G_RNG1,         RCC_AHB5ENSETR, 6, 0),
1541         K_GATE(G_HASH1,         RCC_AHB5ENSETR, 5, 0),
1542         K_GATE(G_CRYP1,         RCC_AHB5ENSETR, 4, 0),
1543         K_GATE(G_GPIOZ,         RCC_AHB5ENSETR, 0, 0),
1544
1545         K_GATE(G_USBH,          RCC_AHB6ENSETR, 24, 0),
1546         K_GATE(G_CRC1,          RCC_AHB6ENSETR, 20, 0),
1547         K_MGATE(G_SDMMC2,       RCC_AHB6ENSETR, 17, 0),
1548         K_MGATE(G_SDMMC1,       RCC_AHB6ENSETR, 16, 0),
1549         K_MGATE(G_QSPI,         RCC_AHB6ENSETR, 14, 0),
1550         K_MGATE(G_FMC,          RCC_AHB6ENSETR, 12, 0),
1551         K_GATE(G_ETHMAC,        RCC_AHB6ENSETR, 10, 0),
1552         K_GATE(G_ETHRX,         RCC_AHB6ENSETR, 9, 0),
1553         K_GATE(G_ETHTX,         RCC_AHB6ENSETR, 8, 0),
1554         K_GATE(G_ETHCK,         RCC_AHB6ENSETR, 7, 0),
1555         K_MGATE(G_GPU,          RCC_AHB6ENSETR, 5, 0),
1556         K_GATE(G_MDMA,          RCC_AHB6ENSETR, 0, 0),
1557         K_GATE(G_ETHSTP,        RCC_AHB6LPENSETR, 11, 0),
1558 };
1559
1560 enum {
1561         M_SDMMC12,
1562         M_SDMMC3,
1563         M_FMC,
1564         M_QSPI,
1565         M_RNG1,
1566         M_RNG2,
1567         M_USBPHY,
1568         M_USBO,
1569         M_STGEN,
1570         M_SPDIF,
1571         M_SPI1,
1572         M_SPI23,
1573         M_SPI45,
1574         M_SPI6,
1575         M_CEC,
1576         M_I2C12,
1577         M_I2C35,
1578         M_I2C46,
1579         M_LPTIM1,
1580         M_LPTIM23,
1581         M_LPTIM45,
1582         M_USART1,
1583         M_UART24,
1584         M_UART35,
1585         M_USART6,
1586         M_UART78,
1587         M_SAI1,
1588         M_SAI2,
1589         M_SAI3,
1590         M_SAI4,
1591         M_DSI,
1592         M_FDCAN,
1593         M_ADC12,
1594         M_ETHCK,
1595         M_CKPER,
1596         M_LAST
1597 };
1598
1599 static struct stm32_mmux ker_mux[M_LAST];
1600
1601 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1602         [_id] = {\
1603                 &(struct mux_cfg) {\
1604                         .reg_off        = _offset,\
1605                         .shift          = _shift,\
1606                         .width          = _width,\
1607                         .mux_flags      = _mux_flags,\
1608                         .table          = NULL,\
1609                 },\
1610                 .mmux           = _mmux,\
1611                 .ops            = _ops,\
1612         }
1613
1614 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
1615         _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1616                         NULL, NULL)
1617
1618 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
1619         _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1620                         &ker_mux[_id], &clk_mmux_ops)
1621
1622 static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1623         /* Kernel multi mux */
1624         K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1625         K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
1626         K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
1627         K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
1628         K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
1629         K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
1630         K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
1631         K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
1632         K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
1633         K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
1634         K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
1635         K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
1636         K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
1637
1638         /*  Kernel simple mux */
1639         K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
1640         K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
1641         K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
1642         K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
1643         K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
1644         K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
1645         K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
1646         K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
1647         K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
1648         K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
1649         K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
1650         K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
1651         K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
1652         K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
1653         K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
1654         K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
1655         K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
1656         K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
1657         K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
1658         K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
1659         K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
1660         K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
1661 };
1662
1663 static const struct clock_config stm32mp1_clock_cfg[] = {
1664         /* Oscillator divider */
1665         DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
1666             CLK_DIVIDER_READ_ONLY),
1667
1668         /*  External / Internal Oscillators */
1669         GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1670         GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
1671         GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
1672         GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1673         GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1674
1675         FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1676
1677         /* ref clock pll */
1678         MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
1679             0, 2, CLK_MUX_READ_ONLY),
1680
1681         MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
1682             0, 2, CLK_MUX_READ_ONLY),
1683
1684         MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
1685             0, 2, CLK_MUX_READ_ONLY),
1686
1687         /* PLLs */
1688         PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
1689         PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
1690         PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
1691         PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
1692
1693         /* ODF */
1694         COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1695                   _GATE(RCC_PLL1CR, 4, 0),
1696                   _NO_MUX,
1697                   _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
1698
1699         COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1700                   _GATE(RCC_PLL2CR, 4, 0),
1701                   _NO_MUX,
1702                   _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
1703
1704         COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1705                   _GATE(RCC_PLL2CR, 5, 0),
1706                   _NO_MUX,
1707                   _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
1708
1709         COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
1710                   _GATE(RCC_PLL2CR, 6, 0),
1711                   _NO_MUX,
1712                   _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
1713
1714         COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1715                   _GATE(RCC_PLL3CR, 4, 0),
1716                   _NO_MUX,
1717                   _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
1718
1719         COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1720                   _GATE(RCC_PLL3CR, 5, 0),
1721                   _NO_MUX,
1722                   _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
1723
1724         COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1725                   _GATE(RCC_PLL3CR, 6, 0),
1726                   _NO_MUX,
1727                   _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
1728
1729         COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1730                   _GATE(RCC_PLL4CR, 4, 0),
1731                   _NO_MUX,
1732                   _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
1733
1734         COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1735                   _GATE(RCC_PLL4CR, 5, 0),
1736                   _NO_MUX,
1737                   _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
1738
1739         COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
1740                   _GATE(RCC_PLL4CR, 6, 0),
1741                   _NO_MUX,
1742                   _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
1743
1744         /* MUX system clocks */
1745         MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1746             RCC_CPERCKSELR, 0, 2, 0),
1747
1748         MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1749              CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
1750
1751         COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
1752                    CLK_OPS_PARENT_ENABLE,
1753                    _NO_GATE,
1754                    _MUX(RCC_ASSCKSELR, 0, 2, 0),
1755                    _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
1756
1757         COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
1758                    CLK_OPS_PARENT_ENABLE,
1759                    _NO_GATE,
1760                    _MUX(RCC_MSSCKSELR, 0, 2, 0),
1761                    _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
1762
1763         DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
1764                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1765
1766         DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
1767                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1768
1769         DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
1770                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1771
1772         DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
1773                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1774
1775         DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
1776                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1777
1778         /* Kernel Timers */
1779         STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1780         STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1781
1782         STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
1783         STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
1784         STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
1785         STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
1786         STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
1787         STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
1788         STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
1789         STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
1790         STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
1791         STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
1792         STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
1793         STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
1794         STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
1795         STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
1796
1797         /* Peripheral clocks */
1798         PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1799         PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1800         PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1801         PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1802         PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1803         PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1804         PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1805         PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1806         PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
1807         PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
1808         PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
1809         PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
1810         PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
1811         PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
1812         PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
1813         PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
1814         PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
1815         PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
1816         PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
1817         PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
1818         PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
1819         PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
1820         PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
1821         PCLK(CEC, "cec", "pclk1", 0, G_CEC),
1822         PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
1823         PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
1824         PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
1825         PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
1826         PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
1827         PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
1828         PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
1829         PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
1830         PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
1831         PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
1832         PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
1833         PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
1834         PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
1835         PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
1836         PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
1837         PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
1838         PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
1839         PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
1840         PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
1841         PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
1842         PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
1843         PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
1844         PCLK(VREF, "vref", "pclk3", 13, G_VREF),
1845         PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
1846         PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
1847         PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
1848         PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
1849         PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
1850         PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
1851         PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
1852         PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
1853         PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
1854         PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
1855         PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
1856         PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1857         PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1858              CLK_IS_CRITICAL, G_RTCAPB),
1859         PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
1860         PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
1861         PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1862         PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1863         PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
1864         PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
1865         PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
1866         PCLK(DMA2, "dma2", "ck_mcu",  0, G_DMA2),
1867         PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
1868         PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
1869         PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
1870         PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
1871         PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
1872         PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
1873         PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
1874         PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
1875         PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
1876         PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
1877         PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
1878         PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
1879         PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
1880         PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
1881         PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
1882         PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
1883         PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
1884         PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
1885         PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
1886         PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
1887         PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
1888         PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
1889         PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
1890         PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
1891         PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
1892         PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
1893         PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
1894         PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
1895         PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
1896         PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
1897         PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
1898         PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
1899         PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
1900         PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
1901         PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
1902         PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
1903         PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
1904         PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
1905         PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1906
1907         /* Kernel clocks */
1908         KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
1909         KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
1910         KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
1911         KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
1912         KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
1913         KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
1914         KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
1915         KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
1916         KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
1917         KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
1918         KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
1919         KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
1920         KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
1921         KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
1922         KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
1923         KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
1924         KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
1925         KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
1926         KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
1927         KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
1928         KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
1929         KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
1930         KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
1931         KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
1932         KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
1933         KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
1934         KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
1935         KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
1936         KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
1937         KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
1938         KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
1939         KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
1940         KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
1941         KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
1942         KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
1943         KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
1944         KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
1945         KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
1946         KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
1947         KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
1948         KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
1949         KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
1950         KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
1951         KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
1952         KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
1953         KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK),
1954
1955         /* Particulary Kernel Clocks (no mux or no gate) */
1956         MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
1957         MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
1958         MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
1959         MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
1960         MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
1961
1962         COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,
1963                   _NO_GATE,
1964                   _MMUX(M_ETHCK),
1965                   _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
1966
1967         /* RTC clock */
1968         DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
1969             CLK_DIVIDER_ALLOW_ZERO),
1970
1971         COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
1972                    CLK_SET_RATE_PARENT,
1973                   _GATE(RCC_BDCR, 20, 0),
1974                   _MUX(RCC_BDCR, 16, 2, 0),
1975                   _NO_DIV),
1976
1977         /* MCO clocks */
1978         COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
1979                   CLK_SET_RATE_NO_REPARENT,
1980                   _GATE(RCC_MCO1CFGR, 12, 0),
1981                   _MUX(RCC_MCO1CFGR, 0, 3, 0),
1982                   _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
1983
1984         COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
1985                   CLK_SET_RATE_NO_REPARENT,
1986                   _GATE(RCC_MCO2CFGR, 12, 0),
1987                   _MUX(RCC_MCO2CFGR, 0, 3, 0),
1988                   _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
1989
1990         /* Debug clocks */
1991         GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
1992
1993         COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
1994                   _GATE(RCC_DBGCFGR, 9, 0),
1995                   _NO_MUX,
1996                   _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
1997 };
1998
1999 struct stm32_clock_match_data {
2000         const struct clock_config *cfg;
2001         unsigned int num;
2002         unsigned int maxbinding;
2003 };
2004
2005 static struct stm32_clock_match_data stm32mp1_data = {
2006         .cfg            = stm32mp1_clock_cfg,
2007         .num            = ARRAY_SIZE(stm32mp1_clock_cfg),
2008         .maxbinding     = STM32MP1_LAST_CLK,
2009 };
2010
2011 static const struct of_device_id stm32mp1_match_data[] = {
2012         {
2013                 .compatible = "st,stm32mp1-rcc",
2014                 .data = &stm32mp1_data,
2015         },
2016         { }
2017 };
2018
2019 static int stm32_register_hw_clk(struct device *dev,
2020                                  struct clk_hw_onecell_data *clk_data,
2021                                  void __iomem *base, spinlock_t *lock,
2022                                  const struct clock_config *cfg)
2023 {
2024         static struct clk_hw **hws;
2025         struct clk_hw *hw = ERR_PTR(-ENOENT);
2026
2027         hws = clk_data->hws;
2028
2029         if (cfg->func)
2030                 hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
2031
2032         if (IS_ERR(hw)) {
2033                 pr_err("Unable to register %s\n", cfg->name);
2034                 return  PTR_ERR(hw);
2035         }
2036
2037         if (cfg->id != NO_ID)
2038                 hws[cfg->id] = hw;
2039
2040         return 0;
2041 }
2042
2043 static int stm32_rcc_init(struct device_node *np,
2044                           void __iomem *base,
2045                           const struct of_device_id *match_data)
2046 {
2047         struct clk_hw_onecell_data *clk_data;
2048         struct clk_hw **hws;
2049         const struct of_device_id *match;
2050         const struct stm32_clock_match_data *data;
2051         int err, n, max_binding;
2052
2053         match = of_match_node(match_data, np);
2054         if (!match) {
2055                 pr_err("%s: match data not found\n", __func__);
2056                 return -ENODEV;
2057         }
2058
2059         data = match->data;
2060
2061         max_binding =  data->maxbinding;
2062
2063         clk_data = kzalloc(struct_size(clk_data, hws, max_binding),
2064                            GFP_KERNEL);
2065         if (!clk_data)
2066                 return -ENOMEM;
2067
2068         clk_data->num = max_binding;
2069
2070         hws = clk_data->hws;
2071
2072         for (n = 0; n < max_binding; n++)
2073                 hws[n] = ERR_PTR(-ENOENT);
2074
2075         for (n = 0; n < data->num; n++) {
2076                 err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
2077                                             &data->cfg[n]);
2078                 if (err) {
2079                         pr_err("%s: can't register  %s\n", __func__,
2080                                data->cfg[n].name);
2081
2082                         kfree(clk_data);
2083
2084                         return err;
2085                 }
2086         }
2087
2088         return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
2089 }
2090
2091 static void stm32mp1_rcc_init(struct device_node *np)
2092 {
2093         void __iomem *base;
2094
2095         base = of_iomap(np, 0);
2096         if (!base) {
2097                 pr_err("%s: unable to map resource", np->name);
2098                 of_node_put(np);
2099                 return;
2100         }
2101
2102         if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
2103                 iounmap(base);
2104                 of_node_put(np);
2105         }
2106 }
2107
2108 CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);