1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/gcd.h>
18 #include <linux/math64.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <asm/unaligned.h>
25 #define SI5341_NUM_INPUTS 4
27 #define SI5340_MAX_NUM_OUTPUTS 4
28 #define SI5341_MAX_NUM_OUTPUTS 10
29 #define SI5342_MAX_NUM_OUTPUTS 2
30 #define SI5344_MAX_NUM_OUTPUTS 4
31 #define SI5345_MAX_NUM_OUTPUTS 10
33 #define SI5340_NUM_SYNTH 4
34 #define SI5341_NUM_SYNTH 5
35 #define SI5342_NUM_SYNTH 2
36 #define SI5344_NUM_SYNTH 4
37 #define SI5345_NUM_SYNTH 5
39 /* Range of the synthesizer fractional divider */
40 #define SI5341_SYNTH_N_MIN 10
41 #define SI5341_SYNTH_N_MAX 4095
43 /* The chip can get its input clock from 3 input pins or an XTAL */
45 /* There is one PLL running at 13500–14256 MHz */
46 #define SI5341_PLL_VCO_MIN 13500000000ull
47 #define SI5341_PLL_VCO_MAX 14256000000ull
49 /* The 5 frequency synthesizers obtain their input from the PLL */
50 struct clk_si5341_synth {
52 struct clk_si5341 *data;
55 #define to_clk_si5341_synth(_hw) \
56 container_of(_hw, struct clk_si5341_synth, hw)
58 /* The output stages can be connected to any synth (full mux) */
59 struct clk_si5341_output {
61 struct clk_si5341 *data;
64 #define to_clk_si5341_output(_hw) \
65 container_of(_hw, struct clk_si5341_output, hw)
69 struct regmap *regmap;
70 struct i2c_client *i2c_client;
71 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
73 struct clk *input_clk[SI5341_NUM_INPUTS];
74 const char *input_clk_name[SI5341_NUM_INPUTS];
75 const u16 *reg_output_offset;
76 const u16 *reg_rdiv_offset;
77 u64 freq_vco; /* 13500–14256 MHz */
82 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
84 struct clk_si5341_output_config {
85 u8 out_format_drv_bits;
91 #define SI5341_PAGE 0x0001
92 #define SI5341_PN_BASE 0x0002
93 #define SI5341_DEVICE_REV 0x0005
94 #define SI5341_STATUS 0x000C
95 #define SI5341_SOFT_RST 0x001C
96 #define SI5341_IN_SEL 0x0021
97 #define SI5341_DEVICE_READY 0x00FE
98 #define SI5341_XAXB_CFG 0x090E
99 #define SI5341_IN_EN 0x0949
100 #define SI5341_INX_TO_PFD_EN 0x094A
102 /* Input selection */
103 #define SI5341_IN_SEL_MASK 0x06
104 #define SI5341_IN_SEL_SHIFT 1
105 #define SI5341_IN_SEL_REGCTRL 0x01
106 #define SI5341_INX_TO_PFD_SHIFT 4
108 /* XTAL config bits */
109 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
110 #define SI5341_XAXB_CFG_PDNB BIT(1)
112 /* Input dividers (48-bit) */
113 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
114 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
115 #define SI5341_PX_UPD 0x0230
117 /* PLL configuration */
118 #define SI5341_PLL_M_NUM 0x0235
119 #define SI5341_PLL_M_DEN 0x023B
121 /* Output configuration */
122 #define SI5341_OUT_CONFIG(output) \
123 ((output)->data->reg_output_offset[(output)->index])
124 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
125 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
126 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
127 #define SI5341_OUT_R_REG(output) \
128 ((output)->data->reg_rdiv_offset[(output)->index])
130 /* Synthesize N divider */
131 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
132 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
133 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
135 /* Synthesizer output enable, phase bypass, power mode */
136 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
137 #define SI5341_SYNTH_N_PIBYP 0x0A04
138 #define SI5341_SYNTH_N_PDNB 0x0A05
139 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
141 #define SI5341_REGISTER_MAX 0xBFF
143 /* SI5341_OUT_CONFIG bits */
144 #define SI5341_OUT_CFG_PDN BIT(0)
145 #define SI5341_OUT_CFG_OE BIT(1)
146 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
148 /* Static configuration (to be moved to firmware) */
149 struct si5341_reg_default {
154 static const char * const si5341_input_clock_names[] = {
155 "in0", "in1", "in2", "xtal"
158 /* Output configuration registers 0..9 are not quite logically organized */
159 /* Also for si5345 */
160 static const u16 si5341_reg_output_offset[] = {
173 /* for si5340, si5342 and si5344 */
174 static const u16 si5340_reg_output_offset[] = {
181 /* The location of the R divider registers */
182 static const u16 si5341_reg_rdiv_offset[] = {
194 static const u16 si5340_reg_rdiv_offset[] = {
202 * Programming sequence from ClockBuilder, settings to initialize the system
203 * using only the XTAL input, without pre-divider.
204 * This also contains settings that aren't mentioned anywhere in the datasheet.
205 * The "known" settings like synth and output configuration are done later.
207 static const struct si5341_reg_default si5341_reg_defaults[] = {
208 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
209 { 0x0018, 0xFF }, /* INT mask */
210 { 0x0021, 0x0F }, /* Select XTAL as input */
211 { 0x0022, 0x00 }, /* Not in datasheet */
212 { 0x002B, 0x02 }, /* SPI config */
213 { 0x002C, 0x20 }, /* LOS enable for XTAL */
214 { 0x002D, 0x00 }, /* LOS timing */
225 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
230 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
231 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
232 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
233 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
234 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
235 { 0x009E, 0x00 }, /* Not in datasheet */
236 { 0x0102, 0x01 }, /* Enable outputs */
237 { 0x013F, 0x00 }, /* Not in datasheet */
238 { 0x0140, 0x00 }, /* Not in datasheet */
239 { 0x0141, 0x40 }, /* OUT LOS */
240 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
244 { 0x0206, 0x00 }, /* PXAXB (2^x) */
245 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
284 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
285 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
292 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
293 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
294 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
323 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
324 { 0x0359, 0x00 }, /* Nx_DELAY */
333 { 0x0362, 0x00 }, /* Nx_DELAY end */
334 { 0x0802, 0x00 }, /* Not in datasheet */
335 { 0x0803, 0x00 }, /* Not in datasheet */
336 { 0x0804, 0x00 }, /* Not in datasheet */
337 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
338 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
339 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
340 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
341 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
342 { 0x0A02, 0x00 }, /* Not in datasheet */
343 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
346 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
347 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
348 u64 *val1, u32 *val2)
353 err = regmap_bulk_read(regmap, reg, r, 10);
357 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
358 (get_unaligned_le32(r));
359 *val2 = get_unaligned_le32(&r[6]);
364 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
365 u64 n_num, u32 n_den)
369 /* Shift left as far as possible without overflowing */
370 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
375 /* 44 bits (6 bytes) numerator */
376 put_unaligned_le32(n_num, r);
377 r[4] = (n_num >> 32) & 0xff;
378 r[5] = (n_num >> 40) & 0x0f;
379 /* 32 bits denominator */
380 put_unaligned_le32(n_den, &r[6]);
382 /* Program the fraction */
383 return regmap_bulk_write(regmap, reg, r, sizeof(r));
386 /* VCO, we assume it runs at a constant frequency */
387 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
388 unsigned long parent_rate)
390 struct clk_si5341 *data = to_clk_si5341(hw);
397 /* Assume that PDIV is not being used, just read the PLL setting */
398 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
403 if (!m_num || !m_den)
407 * Though m_num is 64-bit, only the upper bits are actually used. While
408 * calculating m_num and m_den, they are shifted as far as possible to
409 * the left. To avoid 96-bit division here, we just shift them back so
410 * we can do with just 64 bits.
414 while (res & 0xffff00000000ULL) {
419 do_div(res, (m_den >> shift));
421 /* We cannot return the actual frequency in 32 bit, store it locally */
422 data->freq_vco = res;
424 /* Report kHz since the value is out of range */
427 return (unsigned long)res;
430 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
435 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
439 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
442 static u8 si5341_clk_get_parent(struct clk_hw *hw)
444 struct clk_si5341 *data = to_clk_si5341(hw);
445 int res = si5341_clk_get_selected_input(data);
448 return 0; /* Apparently we cannot report errors */
453 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
458 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
459 /* Enable register-based input selection */
460 val |= SI5341_IN_SEL_REGCTRL;
462 err = regmap_update_bits(data->regmap,
463 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
468 /* Enable input buffer for selected input */
469 err = regmap_update_bits(data->regmap,
470 SI5341_IN_EN, 0x07, BIT(index));
474 /* Enables the input to phase detector */
475 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
476 0x7 << SI5341_INX_TO_PFD_SHIFT,
477 BIT(index + SI5341_INX_TO_PFD_SHIFT));
481 /* Power down XTAL oscillator and buffer */
482 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
483 SI5341_XAXB_CFG_PDNB, 0);
488 * Set the P divider to "1". There's no explanation in the
489 * datasheet of these registers, but the clockbuilder software
490 * programs a "1" when the input is being used.
492 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
496 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
500 /* Set update PDIV bit */
501 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
505 /* Disable all input buffers */
506 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
510 /* Disable input to phase detector */
511 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
512 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
516 /* Power up XTAL oscillator and buffer */
517 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
518 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
526 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
528 struct clk_si5341 *data = to_clk_si5341(hw);
530 return si5341_clk_reparent(data, index);
533 static const struct clk_ops si5341_clk_ops = {
534 .set_parent = si5341_clk_set_parent,
535 .get_parent = si5341_clk_get_parent,
536 .recalc_rate = si5341_clk_recalc_rate,
539 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
541 /* The synthesizer is on if all power and enable bits are set */
542 static int si5341_synth_clk_is_on(struct clk_hw *hw)
544 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
547 u8 index = synth->index;
549 err = regmap_read(synth->data->regmap,
550 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
554 if (!(val & BIT(index)))
557 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
561 if (!(val & BIT(index)))
564 /* This bit must be 0 for the synthesizer to receive clock input */
565 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
569 return !(val & BIT(index));
572 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
574 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
575 u8 index = synth->index; /* In range 0..5 */
576 u8 mask = BIT(index);
579 regmap_update_bits(synth->data->regmap,
580 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
582 regmap_update_bits(synth->data->regmap,
583 SI5341_SYNTH_N_PDNB, mask, 0);
584 /* Disable clock input to synth (set to 1 to disable) */
585 regmap_update_bits(synth->data->regmap,
586 SI5341_SYNTH_N_CLK_DIS, mask, mask);
589 static int si5341_synth_clk_prepare(struct clk_hw *hw)
591 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
593 u8 index = synth->index;
594 u8 mask = BIT(index);
597 err = regmap_update_bits(synth->data->regmap,
598 SI5341_SYNTH_N_PDNB, mask, mask);
602 /* Enable clock input to synth (set bit to 0 to enable) */
603 err = regmap_update_bits(synth->data->regmap,
604 SI5341_SYNTH_N_CLK_DIS, mask, 0);
609 return regmap_update_bits(synth->data->regmap,
610 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
613 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
614 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
615 unsigned long parent_rate)
617 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
623 err = si5341_decode_44_32(synth->data->regmap,
624 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
629 * n_num and n_den are shifted left as much as possible, so to prevent
630 * overflow in 64-bit math, we shift n_den 4 bits to the right
632 f = synth->data->freq_vco;
635 /* Now we need to to 64-bit division: f/n_num */
636 /* And compensate for the 4 bits we dropped */
637 f = div64_u64(f, (n_num >> 4));
642 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
643 unsigned long *parent_rate)
645 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
648 /* The synthesizer accuracy is such that anything in range will work */
649 f = synth->data->freq_vco;
650 do_div(f, SI5341_SYNTH_N_MAX);
654 f = synth->data->freq_vco;
655 do_div(f, SI5341_SYNTH_N_MIN);
662 static int si5341_synth_program(struct clk_si5341_synth *synth,
663 u64 n_num, u32 n_den, bool is_integer)
666 u8 index = synth->index;
668 err = si5341_encode_44_32(synth->data->regmap,
669 SI5341_SYNTH_N_NUM(index), n_num, n_den);
671 err = regmap_update_bits(synth->data->regmap,
672 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
676 return regmap_write(synth->data->regmap,
677 SI5341_SYNTH_N_UPD(index), 0x01);
681 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
682 unsigned long parent_rate)
684 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
691 n_num = synth->data->freq_vco;
693 /* see if there's an integer solution */
694 r = do_div(n_num, rate);
695 is_integer = (r == 0);
697 /* Integer divider equal to n_num */
700 /* Calculate a fractional solution */
707 dev_dbg(&synth->data->i2c_client->dev,
708 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
709 synth->index, n_num, n_den,
710 is_integer ? "int" : "frac");
712 return si5341_synth_program(synth, n_num, n_den, is_integer);
715 static const struct clk_ops si5341_synth_clk_ops = {
716 .is_prepared = si5341_synth_clk_is_on,
717 .prepare = si5341_synth_clk_prepare,
718 .unprepare = si5341_synth_clk_unprepare,
719 .recalc_rate = si5341_synth_clk_recalc_rate,
720 .round_rate = si5341_synth_clk_round_rate,
721 .set_rate = si5341_synth_clk_set_rate,
724 static int si5341_output_clk_is_on(struct clk_hw *hw)
726 struct clk_si5341_output *output = to_clk_si5341_output(hw);
730 err = regmap_read(output->data->regmap,
731 SI5341_OUT_CONFIG(output), &val);
735 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
736 return (val & 0x03) == SI5341_OUT_CFG_OE;
739 /* Disables and then powers down the output */
740 static void si5341_output_clk_unprepare(struct clk_hw *hw)
742 struct clk_si5341_output *output = to_clk_si5341_output(hw);
744 regmap_update_bits(output->data->regmap,
745 SI5341_OUT_CONFIG(output),
746 SI5341_OUT_CFG_OE, 0);
747 regmap_update_bits(output->data->regmap,
748 SI5341_OUT_CONFIG(output),
749 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
752 /* Powers up and then enables the output */
753 static int si5341_output_clk_prepare(struct clk_hw *hw)
755 struct clk_si5341_output *output = to_clk_si5341_output(hw);
758 err = regmap_update_bits(output->data->regmap,
759 SI5341_OUT_CONFIG(output),
760 SI5341_OUT_CFG_PDN, 0);
764 return regmap_update_bits(output->data->regmap,
765 SI5341_OUT_CONFIG(output),
766 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
769 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
770 unsigned long parent_rate)
772 struct clk_si5341_output *output = to_clk_si5341_output(hw);
778 err = regmap_bulk_read(output->data->regmap,
779 SI5341_OUT_R_REG(output), r, 3);
783 /* Calculate value as 24-bit integer*/
784 r_divider = r[2] << 16 | r[1] << 8 | r[0];
786 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
790 /* Divider is 2*(Rx_REG+1) */
794 err = regmap_read(output->data->regmap,
795 SI5341_OUT_CONFIG(output), &val);
799 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
802 return parent_rate / r_divider;
805 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
806 unsigned long *parent_rate)
810 r = *parent_rate >> 1;
812 /* If rate is an even divisor, no changes to parent required */
813 if (r && !(r % rate))
816 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
817 if (rate > 200000000) {
818 /* minimum r-divider is 2 */
821 /* Take a parent frequency near 400 MHz */
822 r = (400000000u / rate) & ~1;
824 *parent_rate = r * rate;
826 /* We cannot change our parent's rate, report what we can do */
828 rate = *parent_rate / (r << 1);
834 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
835 unsigned long parent_rate)
837 struct clk_si5341_output *output = to_clk_si5341_output(hw);
838 /* Frequency divider is (r_div + 1) * 2 */
839 u32 r_div = (parent_rate / rate) >> 1;
845 else if (r_div >= BIT(24))
850 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
851 err = regmap_update_bits(output->data->regmap,
852 SI5341_OUT_CONFIG(output),
853 SI5341_OUT_CFG_RDIV_FORCE2,
854 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
858 /* Always write Rx_REG, because a zero value disables the divider */
859 r[0] = r_div ? (r_div & 0xff) : 1;
860 r[1] = (r_div >> 8) & 0xff;
861 r[2] = (r_div >> 16) & 0xff;
862 err = regmap_bulk_write(output->data->regmap,
863 SI5341_OUT_R_REG(output), r, 3);
868 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
870 return regmap_update_bits(output->data->regmap,
871 SI5341_OUT_MUX_SEL(output), 0x07, index);
874 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
876 struct clk_si5341_output *output = to_clk_si5341_output(hw);
878 if (index >= output->data->num_synth)
881 return si5341_output_reparent(output, index);
884 static u8 si5341_output_get_parent(struct clk_hw *hw)
886 struct clk_si5341_output *output = to_clk_si5341_output(hw);
889 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
894 static const struct clk_ops si5341_output_clk_ops = {
895 .is_prepared = si5341_output_clk_is_on,
896 .prepare = si5341_output_clk_prepare,
897 .unprepare = si5341_output_clk_unprepare,
898 .recalc_rate = si5341_output_clk_recalc_rate,
899 .round_rate = si5341_output_clk_round_rate,
900 .set_rate = si5341_output_clk_set_rate,
901 .set_parent = si5341_output_set_parent,
902 .get_parent = si5341_output_get_parent,
906 * The chip can be bought in a pre-programmed version, or one can program the
907 * NVM in the chip to boot up in a preset mode. This routine tries to determine
908 * if that's the case, or if we need to reset and program everything from
909 * scratch. Returns negative error, or true/false.
911 static int si5341_is_programmed_already(struct clk_si5341 *data)
916 /* Read the PLL divider value, it must have a non-zero value */
917 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
922 return !!get_unaligned_le32(r);
925 static struct clk_hw *
926 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
928 struct clk_si5341 *data = _data;
929 unsigned int idx = clkspec->args[1];
930 unsigned int group = clkspec->args[0];
934 if (idx >= data->num_outputs) {
935 dev_err(&data->i2c_client->dev,
936 "invalid output index %u\n", idx);
937 return ERR_PTR(-EINVAL);
939 return &data->clk[idx].hw;
941 if (idx >= data->num_synth) {
942 dev_err(&data->i2c_client->dev,
943 "invalid synthesizer index %u\n", idx);
944 return ERR_PTR(-EINVAL);
946 return &data->synth[idx].hw;
949 dev_err(&data->i2c_client->dev,
950 "invalid PLL index %u\n", idx);
951 return ERR_PTR(-EINVAL);
955 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
956 return ERR_PTR(-EINVAL);
960 static int si5341_probe_chip_id(struct clk_si5341 *data)
966 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
969 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
973 model = get_unaligned_le16(reg);
975 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
976 model, reg[2], reg[3]);
980 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
981 data->num_synth = SI5340_NUM_SYNTH;
982 data->reg_output_offset = si5340_reg_output_offset;
983 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
986 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
987 data->num_synth = SI5341_NUM_SYNTH;
988 data->reg_output_offset = si5341_reg_output_offset;
989 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
992 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
993 data->num_synth = SI5342_NUM_SYNTH;
994 data->reg_output_offset = si5340_reg_output_offset;
995 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
998 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
999 data->num_synth = SI5344_NUM_SYNTH;
1000 data->reg_output_offset = si5340_reg_output_offset;
1001 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1004 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1005 data->num_synth = SI5345_NUM_SYNTH;
1006 data->reg_output_offset = si5341_reg_output_offset;
1007 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1010 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1015 data->chip_id = model;
1020 /* Read active settings into the regmap cache for later reference */
1021 static int si5341_read_settings(struct clk_si5341 *data)
1027 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1031 err = regmap_bulk_read(data->regmap,
1032 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1036 err = regmap_bulk_read(data->regmap,
1037 SI5341_SYNTH_N_CLK_DIS, r, 1);
1041 for (i = 0; i < data->num_synth; ++i) {
1042 err = regmap_bulk_read(data->regmap,
1043 SI5341_SYNTH_N_NUM(i), r, 10);
1048 for (i = 0; i < data->num_outputs; ++i) {
1049 err = regmap_bulk_read(data->regmap,
1050 data->reg_output_offset[i], r, 4);
1054 err = regmap_bulk_read(data->regmap,
1055 data->reg_rdiv_offset[i], r, 3);
1063 static int si5341_write_multiple(struct clk_si5341 *data,
1064 const struct si5341_reg_default *values, unsigned int num_values)
1069 for (i = 0; i < num_values; ++i) {
1070 res = regmap_write(data->regmap,
1071 values[i].address, values[i].value);
1073 dev_err(&data->i2c_client->dev,
1074 "Failed to write %#x:%#x\n",
1075 values[i].address, values[i].value);
1083 static const struct si5341_reg_default si5341_preamble[] = {
1091 static const struct si5341_reg_default si5345_preamble[] = {
1096 static int si5341_send_preamble(struct clk_si5341 *data)
1101 /* For revision 2 and up, the values are slightly different */
1102 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1106 /* Write "preamble" as specified by datasheet */
1107 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1111 /* The si5342..si5345 require a different preamble */
1112 if (data->chip_id > 0x5341)
1113 res = si5341_write_multiple(data,
1114 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1116 res = si5341_write_multiple(data,
1117 si5341_preamble, ARRAY_SIZE(si5341_preamble));
1121 /* Datasheet specifies a 300ms wait after sending the preamble */
1127 /* Perform a soft reset and write post-amble */
1128 static int si5341_finalize_defaults(struct clk_si5341 *data)
1133 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1137 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1139 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1143 /* The si5342..si5345 have an additional post-amble */
1144 if (data->chip_id > 0x5341) {
1145 res = regmap_write(data->regmap, 0x540, 0x0);
1150 /* Datasheet does not explain these nameless registers */
1151 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1154 res = regmap_write(data->regmap, 0x0B25, 0x02);
1162 static const struct regmap_range si5341_regmap_volatile_range[] = {
1163 regmap_reg_range(0x000C, 0x0012), /* Status */
1164 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1165 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1166 /* Update bits for P divider and synth config */
1167 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1168 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1169 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1170 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1171 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1172 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1175 static const struct regmap_access_table si5341_regmap_volatile = {
1176 .yes_ranges = si5341_regmap_volatile_range,
1177 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1180 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1181 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1184 .range_max = SI5341_REGISTER_MAX,
1185 .selector_reg = SI5341_PAGE,
1186 .selector_mask = 0xff,
1187 .selector_shift = 0,
1193 static int si5341_wait_device_ready(struct i2c_client *client)
1197 /* Datasheet warns: Any attempt to read or write any register other
1198 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1199 * NVM programming and may corrupt the register contents, as they are
1200 * read from NVM. Note that this includes accesses to the PAGE register.
1201 * Also: DEVICE_READY is available on every register page, so no page
1202 * change is needed to read it.
1203 * Do this outside regmap to avoid automatic PAGE register access.
1204 * May take up to 300ms to complete.
1206 for (count = 0; count < 15; ++count) {
1207 s32 result = i2c_smbus_read_byte_data(client,
1208 SI5341_DEVICE_READY);
1215 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1219 static const struct regmap_config si5341_regmap_config = {
1222 .cache_type = REGCACHE_RBTREE,
1223 .ranges = si5341_regmap_ranges,
1224 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1225 .max_register = SI5341_REGISTER_MAX,
1226 .volatile_table = &si5341_regmap_volatile,
1229 static int si5341_dt_parse_dt(struct i2c_client *client,
1230 struct clk_si5341_output_config *config)
1232 struct device_node *child;
1233 struct device_node *np = client->dev.of_node;
1237 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1238 SI5341_MAX_NUM_OUTPUTS);
1240 for_each_child_of_node(np, child) {
1241 if (of_property_read_u32(child, "reg", &num)) {
1242 dev_err(&client->dev, "missing reg property of %s\n",
1247 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1248 dev_err(&client->dev, "invalid clkout %d\n", num);
1252 if (!of_property_read_u32(child, "silabs,format", &val)) {
1253 /* Set cm and ampl conservatively to 3v3 settings */
1255 case 1: /* normal differential */
1256 config[num].out_cm_ampl_bits = 0x33;
1258 case 2: /* low-power differential */
1259 config[num].out_cm_ampl_bits = 0x13;
1261 case 4: /* LVCMOS */
1262 config[num].out_cm_ampl_bits = 0x33;
1263 /* Set SI recommended impedance for LVCMOS */
1264 config[num].out_format_drv_bits |= 0xc0;
1267 dev_err(&client->dev,
1268 "invalid silabs,format %u for %u\n",
1272 config[num].out_format_drv_bits &= ~0x07;
1273 config[num].out_format_drv_bits |= val & 0x07;
1274 /* Always enable the SYNC feature */
1275 config[num].out_format_drv_bits |= 0x08;
1278 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1280 dev_err(&client->dev,
1281 "invalid silabs,common-mode %u\n",
1285 config[num].out_cm_ampl_bits &= 0xf0;
1286 config[num].out_cm_ampl_bits |= val & 0x0f;
1289 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1291 dev_err(&client->dev,
1292 "invalid silabs,amplitude %u\n",
1296 config[num].out_cm_ampl_bits &= 0x0f;
1297 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1300 if (of_property_read_bool(child, "silabs,disable-high"))
1301 config[num].out_format_drv_bits |= 0x10;
1303 config[num].synth_master =
1304 of_property_read_bool(child, "silabs,synth-master");
1306 config[num].always_on =
1307 of_property_read_bool(child, "always-on");
1318 * If not pre-configured, calculate and set the PLL configuration manually.
1319 * For low-jitter performance, the PLL should be set such that the synthesizers
1320 * only need integer division.
1321 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1322 * the chip to generate any frequency on its outputs, but jitter performance
1323 * may be sub-optimal.
1325 static int si5341_initialize_pll(struct clk_si5341 *data)
1327 struct device_node *np = data->i2c_client->dev.of_node;
1332 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1333 dev_err(&data->i2c_client->dev,
1334 "PLL configuration requires silabs,pll-m-num\n");
1336 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1337 dev_err(&data->i2c_client->dev,
1338 "PLL configuration requires silabs,pll-m-den\n");
1341 if (!m_num || !m_den) {
1342 dev_err(&data->i2c_client->dev,
1343 "PLL configuration invalid, assume 14GHz\n");
1344 sel = si5341_clk_get_selected_input(data);
1348 m_den = clk_get_rate(data->input_clk[sel]) / 10;
1352 return si5341_encode_44_32(data->regmap,
1353 SI5341_PLL_M_NUM, m_num, m_den);
1356 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1362 res = si5341_clk_get_selected_input(data);
1366 /* If the current register setting is invalid, pick the first input */
1367 if (!data->input_clk[res]) {
1368 dev_dbg(&data->i2c_client->dev,
1369 "Input %d not connected, rerouting\n", res);
1371 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1372 if (data->input_clk[i]) {
1378 dev_err(&data->i2c_client->dev,
1379 "No clock input available\n");
1384 /* Make sure the selected clock is also enabled and routed */
1385 err = si5341_clk_reparent(data, res);
1389 err = clk_prepare_enable(data->input_clk[res]);
1396 static int si5341_probe(struct i2c_client *client,
1397 const struct i2c_device_id *id)
1399 struct clk_si5341 *data;
1400 struct clk_init_data init;
1402 const char *root_clock_name;
1403 const char *synth_clock_names[SI5341_NUM_SYNTH];
1406 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1407 bool initialization_required;
1409 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1413 data->i2c_client = client;
1415 /* Must be done before otherwise touching hardware */
1416 err = si5341_wait_device_ready(client);
1420 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1421 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1422 if (IS_ERR(input)) {
1423 if (PTR_ERR(input) == -EPROBE_DEFER)
1424 return -EPROBE_DEFER;
1425 data->input_clk_name[i] = si5341_input_clock_names[i];
1427 data->input_clk[i] = input;
1428 data->input_clk_name[i] = __clk_get_name(input);
1432 err = si5341_dt_parse_dt(client, config);
1436 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1438 init.name = client->dev.of_node->name;
1439 root_clock_name = init.name;
1441 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1442 if (IS_ERR(data->regmap))
1443 return PTR_ERR(data->regmap);
1445 i2c_set_clientdata(client, data);
1447 err = si5341_probe_chip_id(data);
1451 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1452 initialization_required = true;
1454 err = si5341_is_programmed_already(data);
1458 initialization_required = !err;
1461 if (initialization_required) {
1462 /* Populate the regmap cache in preparation for "cache only" */
1463 err = si5341_read_settings(data);
1467 err = si5341_send_preamble(data);
1472 * We intend to send all 'final' register values in a single
1473 * transaction. So cache all register writes until we're done
1476 regcache_cache_only(data->regmap, true);
1478 /* Write the configuration pairs from the firmware blob */
1479 err = si5341_write_multiple(data, si5341_reg_defaults,
1480 ARRAY_SIZE(si5341_reg_defaults));
1485 /* Input must be up and running at this point */
1486 err = si5341_clk_select_active_input(data);
1490 if (initialization_required) {
1491 /* PLL configuration is required */
1492 err = si5341_initialize_pll(data);
1497 /* Register the PLL */
1498 init.parent_names = data->input_clk_name;
1499 init.num_parents = SI5341_NUM_INPUTS;
1500 init.ops = &si5341_clk_ops;
1502 data->hw.init = &init;
1504 err = devm_clk_hw_register(&client->dev, &data->hw);
1506 dev_err(&client->dev, "clock registration failed\n");
1510 init.num_parents = 1;
1511 init.parent_names = &root_clock_name;
1512 init.ops = &si5341_synth_clk_ops;
1513 for (i = 0; i < data->num_synth; ++i) {
1514 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1515 "%s.N%u", client->dev.of_node->name, i);
1516 init.name = synth_clock_names[i];
1517 data->synth[i].index = i;
1518 data->synth[i].data = data;
1519 data->synth[i].hw.init = &init;
1520 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1522 dev_err(&client->dev,
1523 "synth N%u registration failed\n", i);
1527 init.num_parents = data->num_synth;
1528 init.parent_names = synth_clock_names;
1529 init.ops = &si5341_output_clk_ops;
1530 for (i = 0; i < data->num_outputs; ++i) {
1531 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1532 client->dev.of_node->name, i);
1533 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1534 data->clk[i].index = i;
1535 data->clk[i].data = data;
1536 data->clk[i].hw.init = &init;
1537 if (config[i].out_format_drv_bits & 0x07) {
1538 regmap_write(data->regmap,
1539 SI5341_OUT_FORMAT(&data->clk[i]),
1540 config[i].out_format_drv_bits);
1541 regmap_write(data->regmap,
1542 SI5341_OUT_CM(&data->clk[i]),
1543 config[i].out_cm_ampl_bits);
1545 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1546 kfree(init.name); /* clock framework made a copy of the name */
1548 dev_err(&client->dev,
1549 "output %u registration failed\n", i);
1552 if (config[i].always_on)
1553 clk_prepare(data->clk[i].hw.clk);
1556 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get,
1559 dev_err(&client->dev, "unable to add clk provider\n");
1563 if (initialization_required) {
1565 regcache_cache_only(data->regmap, false);
1566 err = regcache_sync(data->regmap);
1570 err = si5341_finalize_defaults(data);
1575 /* Free the names, clk framework makes copies */
1576 for (i = 0; i < data->num_synth; ++i)
1577 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1582 static const struct i2c_device_id si5341_id[] = {
1590 MODULE_DEVICE_TABLE(i2c, si5341_id);
1592 static const struct of_device_id clk_si5341_of_match[] = {
1593 { .compatible = "silabs,si5340" },
1594 { .compatible = "silabs,si5341" },
1595 { .compatible = "silabs,si5342" },
1596 { .compatible = "silabs,si5344" },
1597 { .compatible = "silabs,si5345" },
1600 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1602 static struct i2c_driver si5341_driver = {
1605 .of_match_table = clk_si5341_of_match,
1607 .probe = si5341_probe,
1608 .id_table = si5341_id,
1610 module_i2c_driver(si5341_driver);
1612 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1613 MODULE_DESCRIPTION("Si5341 driver");
1614 MODULE_LICENSE("GPL");