1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * clock driver for Freescale QorIQ SoCs.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/fsl/guts.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
20 #include <linux/slab.h>
27 #define PLATFORM_PLL 0
31 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
34 #define MAX_PLL_DIV 16
36 struct clockgen_pll_div {
42 struct clockgen_pll_div div[MAX_PLL_DIV];
45 #define CLKSEL_VALID 1
46 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
48 struct clockgen_sourceinfo {
49 u32 flags; /* CLKSEL_xxx */
50 int pll; /* CGx_PLLn */
51 int div; /* PLL_DIVn */
54 #define NUM_MUX_PARENTS 16
56 struct clockgen_muxinfo {
57 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
66 * cmux freq must be >= platform pll.
67 * If not set, cmux freq must be >= platform pll/2
69 #define CG_CMUX_GE_PLAT 1
71 #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
72 #define CG_VER3 4 /* version 3 cg: reg layout different */
73 #define CG_LITTLE_ENDIAN 8
75 struct clockgen_chipinfo {
76 const char *compat, *guts_compat;
77 const struct clockgen_muxinfo *cmux_groups[2];
78 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
79 void (*init_periph)(struct clockgen *cg);
80 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
81 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
82 u32 flags; /* CG_xxx */
86 struct device_node *node;
88 struct clockgen_chipinfo info; /* mutable copy */
89 struct clk *sysclk, *coreclk;
90 struct clockgen_pll pll[6];
91 struct clk *cmux[NUM_CMUX];
92 struct clk *hwaccel[NUM_HWACCEL];
94 struct ccsr_guts __iomem *guts;
97 static struct clockgen clockgen;
98 static bool add_cpufreq_dev __initdata;
100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
102 if (cg->info.flags & CG_LITTLE_ENDIAN)
105 iowrite32be(val, reg);
108 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
112 if (cg->info.flags & CG_LITTLE_ENDIAN)
115 val = ioread32be(reg);
120 static const struct clockgen_muxinfo p2041_cmux_grp1 = {
122 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
123 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
124 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
128 static const struct clockgen_muxinfo p2041_cmux_grp2 = {
130 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
131 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
132 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
136 static const struct clockgen_muxinfo p5020_cmux_grp1 = {
138 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
139 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
140 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
144 static const struct clockgen_muxinfo p5020_cmux_grp2 = {
146 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
147 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
148 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
152 static const struct clockgen_muxinfo p5040_cmux_grp1 = {
154 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
155 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
156 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
157 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
161 static const struct clockgen_muxinfo p5040_cmux_grp2 = {
163 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
164 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
165 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
166 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
170 static const struct clockgen_muxinfo p4080_cmux_grp1 = {
172 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
173 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
174 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
175 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
176 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
180 static const struct clockgen_muxinfo p4080_cmux_grp2 = {
182 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
183 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
184 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
185 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
186 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
190 static const struct clockgen_muxinfo t1023_cmux = {
192 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
193 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
197 static const struct clockgen_muxinfo t1040_cmux = {
199 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
200 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
201 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
202 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
207 static const struct clockgen_muxinfo clockgen2_cmux_cga = {
209 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
213 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
217 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
223 static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
225 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
229 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
235 static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
237 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
241 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
247 static const struct clockgen_muxinfo ls1028a_hwa1 = {
249 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
250 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
253 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
255 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
256 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
260 static const struct clockgen_muxinfo ls1028a_hwa2 = {
262 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
263 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
266 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
268 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
269 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
273 static const struct clockgen_muxinfo ls1028a_hwa3 = {
275 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
276 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
278 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
279 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
281 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
282 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
286 static const struct clockgen_muxinfo ls1028a_hwa4 = {
288 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
289 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
294 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
295 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
299 static const struct clockgen_muxinfo ls1043a_hwa1 = {
303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
304 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
307 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
308 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
312 static const struct clockgen_muxinfo ls1043a_hwa2 = {
315 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
317 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
321 static const struct clockgen_muxinfo ls1046a_hwa1 = {
325 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
326 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
327 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
328 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
329 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
330 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
334 static const struct clockgen_muxinfo ls1046a_hwa2 = {
337 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
339 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
342 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
346 static const struct clockgen_muxinfo ls1088a_hwa1 = {
349 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
350 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
351 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
352 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
354 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
355 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
359 static const struct clockgen_muxinfo ls1088a_hwa2 = {
362 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
363 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
364 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
365 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
367 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
368 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
372 static const struct clockgen_muxinfo ls1012a_cmux = {
374 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
376 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
380 static const struct clockgen_muxinfo t1023_hwa1 = {
383 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
384 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
385 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
389 static const struct clockgen_muxinfo t1023_hwa2 = {
391 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
395 static const struct clockgen_muxinfo t2080_hwa1 = {
398 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
399 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
400 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
401 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
402 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
403 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
404 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
408 static const struct clockgen_muxinfo t2080_hwa2 = {
411 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
412 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
413 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
414 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
415 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
416 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
417 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
421 static const struct clockgen_muxinfo t4240_hwa1 = {
423 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
424 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
425 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
426 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
427 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
429 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
430 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
434 static const struct clockgen_muxinfo t4240_hwa4 = {
436 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
437 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
438 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
439 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
440 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
444 static const struct clockgen_muxinfo t4240_hwa5 = {
446 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
447 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
448 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
449 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
450 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
451 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
455 #define RCWSR7_FM1_CLK_SEL 0x40000000
456 #define RCWSR7_FM2_CLK_SEL 0x20000000
457 #define RCWSR7_HWA_ASYNC_DIV 0x04000000
459 static void __init p2041_init_periph(struct clockgen *cg)
463 reg = ioread32be(&cg->guts->rcwsr[7]);
465 if (reg & RCWSR7_FM1_CLK_SEL)
466 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
468 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
471 static void __init p4080_init_periph(struct clockgen *cg)
475 reg = ioread32be(&cg->guts->rcwsr[7]);
477 if (reg & RCWSR7_FM1_CLK_SEL)
478 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
480 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
482 if (reg & RCWSR7_FM2_CLK_SEL)
483 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
485 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
488 static void __init p5020_init_periph(struct clockgen *cg)
493 reg = ioread32be(&cg->guts->rcwsr[7]);
494 if (reg & RCWSR7_HWA_ASYNC_DIV)
497 if (reg & RCWSR7_FM1_CLK_SEL)
498 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
500 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
503 static void __init p5040_init_periph(struct clockgen *cg)
508 reg = ioread32be(&cg->guts->rcwsr[7]);
509 if (reg & RCWSR7_HWA_ASYNC_DIV)
512 if (reg & RCWSR7_FM1_CLK_SEL)
513 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
515 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
517 if (reg & RCWSR7_FM2_CLK_SEL)
518 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
520 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
523 static void __init t1023_init_periph(struct clockgen *cg)
525 cg->fman[0] = cg->hwaccel[1];
528 static void __init t1040_init_periph(struct clockgen *cg)
530 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
533 static void __init t2080_init_periph(struct clockgen *cg)
535 cg->fman[0] = cg->hwaccel[0];
538 static void __init t4240_init_periph(struct clockgen *cg)
540 cg->fman[0] = cg->hwaccel[3];
541 cg->fman[1] = cg->hwaccel[4];
544 static const struct clockgen_chipinfo chipinfo[] = {
546 .compat = "fsl,b4420-clockgen",
547 .guts_compat = "fsl,b4860-device-config",
548 .init_periph = t2080_init_periph,
550 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
559 .flags = CG_PLL_8BIT,
562 .compat = "fsl,b4860-clockgen",
563 .guts_compat = "fsl,b4860-device-config",
564 .init_periph = t2080_init_periph,
566 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
575 .flags = CG_PLL_8BIT,
578 .compat = "fsl,ls1021a-clockgen",
588 .compat = "fsl,ls1028a-clockgen",
590 &clockgen2_cmux_cga12
593 &ls1028a_hwa1, &ls1028a_hwa2,
594 &ls1028a_hwa3, &ls1028a_hwa4
600 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
603 .compat = "fsl,ls1043a-clockgen",
604 .init_periph = t2080_init_periph,
609 &ls1043a_hwa1, &ls1043a_hwa2
615 .flags = CG_PLL_8BIT,
618 .compat = "fsl,ls1046a-clockgen",
619 .init_periph = t2080_init_periph,
624 &ls1046a_hwa1, &ls1046a_hwa2
630 .flags = CG_PLL_8BIT,
633 .compat = "fsl,ls1088a-clockgen",
635 &clockgen2_cmux_cga12
638 &ls1088a_hwa1, &ls1088a_hwa2
644 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
647 .compat = "fsl,ls1012a-clockgen",
657 .compat = "fsl,ls2080a-clockgen",
659 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
665 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
668 .compat = "fsl,lx2160a-clockgen",
670 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
673 0, 0, 0, 0, 1, 1, 1, 1, -1
676 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
679 .compat = "fsl,p2041-clockgen",
680 .guts_compat = "fsl,qoriq-device-config-1.0",
681 .init_periph = p2041_init_periph,
683 &p2041_cmux_grp1, &p2041_cmux_grp2
691 .compat = "fsl,p3041-clockgen",
692 .guts_compat = "fsl,qoriq-device-config-1.0",
693 .init_periph = p2041_init_periph,
695 &p2041_cmux_grp1, &p2041_cmux_grp2
703 .compat = "fsl,p4080-clockgen",
704 .guts_compat = "fsl,qoriq-device-config-1.0",
705 .init_periph = p4080_init_periph,
707 &p4080_cmux_grp1, &p4080_cmux_grp2
710 0, 0, 0, 0, 1, 1, 1, 1, -1
715 .compat = "fsl,p5020-clockgen",
716 .guts_compat = "fsl,qoriq-device-config-1.0",
717 .init_periph = p5020_init_periph,
719 &p5020_cmux_grp1, &p5020_cmux_grp2
727 .compat = "fsl,p5040-clockgen",
728 .guts_compat = "fsl,p5040-device-config",
729 .init_periph = p5040_init_periph,
731 &p5040_cmux_grp1, &p5040_cmux_grp2
739 .compat = "fsl,t1023-clockgen",
740 .guts_compat = "fsl,t1023-device-config",
741 .init_periph = t1023_init_periph,
746 &t1023_hwa1, &t1023_hwa2
752 .flags = CG_PLL_8BIT,
755 .compat = "fsl,t1040-clockgen",
756 .guts_compat = "fsl,t1040-device-config",
757 .init_periph = t1040_init_periph,
765 .flags = CG_PLL_8BIT,
768 .compat = "fsl,t2080-clockgen",
769 .guts_compat = "fsl,t2080-device-config",
770 .init_periph = t2080_init_periph,
772 &clockgen2_cmux_cga12
775 &t2080_hwa1, &t2080_hwa2
781 .flags = CG_PLL_8BIT,
784 .compat = "fsl,t4240-clockgen",
785 .guts_compat = "fsl,t4240-device-config",
786 .init_periph = t4240_init_periph,
788 &clockgen2_cmux_cga, &clockgen2_cmux_cgb
791 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
797 .flags = CG_PLL_8BIT,
805 const struct clockgen_muxinfo *info;
807 u8 parent_to_clksel[NUM_MUX_PARENTS];
808 s8 clksel_to_parent[NUM_MUX_PARENTS];
812 #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
813 #define CLKSEL_MASK 0x78000000
814 #define CLKSEL_SHIFT 27
816 static int mux_set_parent(struct clk_hw *hw, u8 idx)
818 struct mux_hwclock *hwc = to_mux_hwclock(hw);
821 if (idx >= hwc->num_parents)
824 clksel = hwc->parent_to_clksel[idx];
825 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
830 static u8 mux_get_parent(struct clk_hw *hw)
832 struct mux_hwclock *hwc = to_mux_hwclock(hw);
836 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
838 ret = hwc->clksel_to_parent[clksel];
840 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
847 static const struct clk_ops cmux_ops = {
848 .get_parent = mux_get_parent,
849 .set_parent = mux_set_parent,
853 * Don't allow setting for now, as the clock options haven't been
854 * sanitized for additional restrictions.
856 static const struct clk_ops hwaccel_ops = {
857 .get_parent = mux_get_parent,
860 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
861 struct mux_hwclock *hwc,
866 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
869 pll = hwc->info->clksel[idx].pll;
870 div = hwc->info->clksel[idx].div;
872 return &cg->pll[pll].div[div];
875 static struct clk * __init create_mux_common(struct clockgen *cg,
876 struct mux_hwclock *hwc,
877 const struct clk_ops *ops,
878 unsigned long min_rate,
879 unsigned long max_rate,
880 unsigned long pct80_rate,
881 const char *fmt, int idx)
883 struct clk_init_data init = {};
885 const struct clockgen_pll_div *div;
886 const char *parent_names[NUM_MUX_PARENTS];
890 snprintf(name, sizeof(name), fmt, idx);
892 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
895 hwc->clksel_to_parent[i] = -1;
897 div = get_pll_div(cg, hwc, i);
901 rate = clk_get_rate(div->clk);
903 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
911 parent_names[j] = div->name;
912 hwc->parent_to_clksel[j] = i;
913 hwc->clksel_to_parent[i] = j;
919 init.parent_names = parent_names;
920 init.num_parents = hwc->num_parents = j;
922 hwc->hw.init = &init;
925 clk = clk_register(NULL, &hwc->hw);
927 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
936 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
938 struct mux_hwclock *hwc;
939 const struct clockgen_pll_div *div;
940 unsigned long plat_rate, min_rate;
941 u64 max_rate, pct80_rate;
944 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
948 if (cg->info.flags & CG_VER3)
949 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
951 hwc->reg = cg->regs + 0x20 * idx;
953 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
956 * Find the rate for the default clksel, and treat it as the
957 * maximum rated core frequency. If this is an incorrect
958 * assumption, certain clock options (possibly including the
959 * default clksel) may be inappropriately excluded on certain
962 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
963 div = get_pll_div(cg, hwc, clksel);
969 max_rate = clk_get_rate(div->clk);
970 pct80_rate = max_rate * 8;
971 do_div(pct80_rate, 10);
973 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
975 if (cg->info.flags & CG_CMUX_GE_PLAT)
976 min_rate = plat_rate;
978 min_rate = plat_rate / 2;
980 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
981 pct80_rate, "cg-cmux%d", idx);
984 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
986 struct mux_hwclock *hwc;
988 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
992 hwc->reg = cg->regs + 0x20 * idx + 0x10;
993 hwc->info = cg->info.hwaccel[idx];
995 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
996 "cg-hwaccel%d", idx);
999 static void __init create_muxes(struct clockgen *cg)
1003 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
1004 if (cg->info.cmux_to_group[i] < 0)
1006 if (cg->info.cmux_to_group[i] >=
1007 ARRAY_SIZE(cg->info.cmux_groups)) {
1012 cg->cmux[i] = create_one_cmux(cg, i);
1015 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
1016 if (!cg->info.hwaccel[i])
1019 cg->hwaccel[i] = create_one_hwaccel(cg, i);
1023 static void __init _clockgen_init(struct device_node *np, bool legacy);
1026 * Legacy nodes may get probed before the parent clockgen node.
1027 * It is assumed that device trees with legacy nodes will not
1028 * contain a "clocks" property -- otherwise the input clocks may
1029 * not be initialized at this point.
1031 static void __init legacy_init_clockgen(struct device_node *np)
1034 _clockgen_init(of_get_parent(np), true);
1038 static void __init core_mux_init(struct device_node *np)
1041 struct resource res;
1044 legacy_init_clockgen(np);
1046 if (of_address_to_resource(np, 0, &res))
1049 idx = (res.start & 0xf0) >> 5;
1050 clk = clockgen.cmux[idx];
1052 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
1054 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1060 static struct clk __init
1061 *sysclk_from_fixed(struct device_node *node, const char *name)
1065 if (of_property_read_u32(node, "clock-frequency", &rate))
1066 return ERR_PTR(-ENODEV);
1068 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
1071 static struct clk __init *input_clock(const char *name, struct clk *clk)
1073 const char *input_name;
1075 /* Register the input clock under the desired name. */
1076 input_name = __clk_get_name(clk);
1077 clk = clk_register_fixed_factor(NULL, name, input_name,
1080 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
1086 static struct clk __init *input_clock_by_name(const char *name,
1091 clk = of_clk_get_by_name(clockgen.node, dtname);
1095 return input_clock(name, clk);
1098 static struct clk __init *input_clock_by_index(const char *name, int idx)
1102 clk = of_clk_get(clockgen.node, 0);
1106 return input_clock(name, clk);
1109 static struct clk * __init create_sysclk(const char *name)
1111 struct device_node *sysclk;
1114 clk = sysclk_from_fixed(clockgen.node, name);
1118 clk = input_clock_by_name(name, "sysclk");
1122 clk = input_clock_by_index(name, 0);
1126 sysclk = of_get_child_by_name(clockgen.node, "sysclk");
1128 clk = sysclk_from_fixed(sysclk, name);
1133 pr_err("%s: No input sysclk\n", __func__);
1137 static struct clk * __init create_coreclk(const char *name)
1141 clk = input_clock_by_name(name, "coreclk");
1146 * This indicates a mix of legacy nodes with the new coreclk
1147 * mechanism, which should never happen. If this error occurs,
1148 * don't use the wrong input clock just because coreclk isn't
1151 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
1158 static void __init sysclk_init(struct device_node *node)
1162 legacy_init_clockgen(node);
1164 clk = clockgen.sysclk;
1166 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1169 #define PLL_KILL BIT(31)
1171 static void __init create_one_pll(struct clockgen *cg, int idx)
1175 struct clockgen_pll *pll = &cg->pll[idx];
1176 const char *input = "cg-sysclk";
1179 if (!(cg->info.pll_mask & (1 << idx)))
1182 if (cg->coreclk && idx != PLATFORM_PLL) {
1183 if (IS_ERR(cg->coreclk))
1186 input = "cg-coreclk";
1189 if (cg->info.flags & CG_VER3) {
1192 reg = cg->regs + 0x60080;
1195 reg = cg->regs + 0x80;
1198 reg = cg->regs + 0xa0;
1201 reg = cg->regs + 0x10080;
1204 reg = cg->regs + 0x100a0;
1207 WARN_ONCE(1, "index %d\n", idx);
1211 if (idx == PLATFORM_PLL)
1212 reg = cg->regs + 0xc00;
1214 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1217 /* Get the multiple of PLL */
1218 mult = cg_in(cg, reg);
1220 /* Check if this PLL is disabled */
1221 if (mult & PLL_KILL) {
1222 pr_debug("%s(): pll %p disabled\n", __func__, reg);
1226 if ((cg->info.flags & CG_VER3) ||
1227 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1228 mult = (mult & GENMASK(8, 1)) >> 1;
1230 mult = (mult & GENMASK(6, 1)) >> 1;
1232 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
1237 * For platform PLL, there are MAX_PLL_DIV divider clocks.
1238 * For core PLL, there are 4 divider clocks at most.
1240 if (idx != PLATFORM_PLL && i >= 4)
1243 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
1244 "cg-pll%d-div%d", idx, i + 1);
1246 clk = clk_register_fixed_factor(NULL,
1247 pll->div[i].name, input, 0, mult, i + 1);
1249 pr_err("%s: %s: register failed %ld\n",
1250 __func__, pll->div[i].name, PTR_ERR(clk));
1254 pll->div[i].clk = clk;
1255 ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
1257 pr_err("%s: %s: register to lookup table failed %d\n",
1258 __func__, pll->div[i].name, ret);
1263 static void __init create_plls(struct clockgen *cg)
1267 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1268 create_one_pll(cg, i);
1271 static void __init legacy_pll_init(struct device_node *np, int idx)
1273 struct clockgen_pll *pll;
1274 struct clk_onecell_data *onecell_data;
1275 struct clk **subclks;
1278 legacy_init_clockgen(np);
1280 pll = &clockgen.pll[idx];
1281 count = of_property_count_strings(np, "clock-output-names");
1283 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
1284 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
1288 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
1293 subclks[0] = pll->div[0].clk;
1294 subclks[1] = pll->div[1].clk;
1295 subclks[2] = pll->div[3].clk;
1297 subclks[0] = pll->div[0].clk;
1298 subclks[1] = pll->div[1].clk;
1299 subclks[2] = pll->div[2].clk;
1300 subclks[3] = pll->div[3].clk;
1303 onecell_data->clks = subclks;
1304 onecell_data->clk_num = count;
1306 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1308 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1315 kfree(onecell_data);
1321 static void __init pltfrm_pll_init(struct device_node *np)
1323 legacy_pll_init(np, PLATFORM_PLL);
1327 static void __init core_pll_init(struct device_node *np)
1329 struct resource res;
1332 if (of_address_to_resource(np, 0, &res))
1335 if ((res.start & 0xfff) == 0xc00) {
1337 * ls1021a devtree labels the platform PLL
1338 * with the core PLL compatible
1340 pltfrm_pll_init(np);
1342 idx = (res.start & 0xf0) >> 5;
1343 legacy_pll_init(np, CGA_PLL1 + idx);
1347 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
1349 struct clockgen *cg = data;
1351 struct clockgen_pll *pll;
1354 if (clkspec->args_count < 2) {
1355 pr_err("%s: insufficient phandle args\n", __func__);
1356 return ERR_PTR(-EINVAL);
1359 type = clkspec->args[0];
1360 idx = clkspec->args[1];
1369 if (idx >= ARRAY_SIZE(cg->cmux))
1371 clk = cg->cmux[idx];
1374 if (idx >= ARRAY_SIZE(cg->hwaccel))
1376 clk = cg->hwaccel[idx];
1379 if (idx >= ARRAY_SIZE(cg->fman))
1381 clk = cg->fman[idx];
1384 pll = &cg->pll[PLATFORM_PLL];
1385 if (idx >= ARRAY_SIZE(pll->div))
1387 clk = pll->div[idx].clk;
1401 return ERR_PTR(-ENOENT);
1405 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
1406 return ERR_PTR(-EINVAL);
1410 #include <asm/mpc85xx.h>
1412 static const u32 a4510_svrs[] __initconst = {
1413 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
1414 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
1415 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
1416 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
1417 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
1418 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
1419 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
1420 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
1421 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
1422 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
1423 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
1424 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
1425 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
1428 #define SVR_SECURITY 0x80000 /* The Security (E) bit */
1430 static bool __init has_erratum_a4510(void)
1432 u32 svr = mfspr(SPRN_SVR);
1435 svr &= ~SVR_SECURITY;
1437 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
1438 if (svr == a4510_svrs[i])
1445 static bool __init has_erratum_a4510(void)
1451 static void __init _clockgen_init(struct device_node *np, bool legacy)
1454 bool is_old_ls1021a = false;
1456 /* May have already been called by a legacy probe */
1461 clockgen.regs = of_iomap(np, 0);
1462 if (!clockgen.regs &&
1463 of_device_is_compatible(of_root, "fsl,ls1021a")) {
1464 /* Compatibility hack for old, broken device trees */
1465 clockgen.regs = ioremap(0x1ee1000, 0x1000);
1466 is_old_ls1021a = true;
1468 if (!clockgen.regs) {
1469 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
1473 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
1474 if (of_device_is_compatible(np, chipinfo[i].compat))
1476 if (is_old_ls1021a &&
1477 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
1481 if (i == ARRAY_SIZE(chipinfo)) {
1482 pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
1485 clockgen.info = chipinfo[i];
1487 if (clockgen.info.guts_compat) {
1488 struct device_node *guts;
1490 guts = of_find_compatible_node(NULL, NULL,
1491 clockgen.info.guts_compat);
1493 clockgen.guts = of_iomap(guts, 0);
1494 if (!clockgen.guts) {
1495 pr_err("%s: Couldn't map %pOF regs\n", __func__,
1503 if (has_erratum_a4510())
1504 clockgen.info.flags |= CG_CMUX_GE_PLAT;
1506 clockgen.sysclk = create_sysclk("cg-sysclk");
1507 clockgen.coreclk = create_coreclk("cg-coreclk");
1508 create_plls(&clockgen);
1509 create_muxes(&clockgen);
1511 if (clockgen.info.init_periph)
1512 clockgen.info.init_periph(&clockgen);
1514 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1516 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1520 /* Don't create cpufreq device for legacy clockgen blocks */
1521 add_cpufreq_dev = !legacy;
1525 iounmap(clockgen.regs);
1526 clockgen.regs = NULL;
1529 static void __init clockgen_init(struct device_node *np)
1531 _clockgen_init(np, false);
1534 static int __init clockgen_cpufreq_init(void)
1536 struct platform_device *pdev;
1538 if (add_cpufreq_dev) {
1539 pdev = platform_device_register_simple("qoriq-cpufreq", -1,
1542 pr_err("Couldn't register qoriq-cpufreq err=%ld\n",
1547 device_initcall(clockgen_cpufreq_init);
1549 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1550 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1551 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1552 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1553 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1554 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1555 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1556 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1557 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1558 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1559 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1560 CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
1561 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1562 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1563 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1564 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1565 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1566 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1567 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1568 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1569 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1572 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1573 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1574 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1575 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1576 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1577 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1578 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1579 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);