1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * clock driver for Freescale QorIQ SoCs.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/fsl/guts.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
20 #include <linux/slab.h>
27 #define PLATFORM_PLL 0
31 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
34 #define MAX_PLL_DIV 16
36 struct clockgen_pll_div {
42 struct clockgen_pll_div div[MAX_PLL_DIV];
45 #define CLKSEL_VALID 1
46 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
48 struct clockgen_sourceinfo {
49 u32 flags; /* CLKSEL_xxx */
50 int pll; /* CGx_PLLn */
51 int div; /* PLL_DIVn */
54 #define NUM_MUX_PARENTS 16
56 struct clockgen_muxinfo {
57 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
66 * cmux freq must be >= platform pll.
67 * If not set, cmux freq must be >= platform pll/2
69 #define CG_CMUX_GE_PLAT 1
71 #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
72 #define CG_VER3 4 /* version 3 cg: reg layout different */
73 #define CG_LITTLE_ENDIAN 8
75 struct clockgen_chipinfo {
76 const char *compat, *guts_compat;
77 const struct clockgen_muxinfo *cmux_groups[2];
78 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
79 void (*init_periph)(struct clockgen *cg);
80 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
81 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
82 u32 flags; /* CG_xxx */
86 struct device_node *node;
88 struct clockgen_chipinfo info; /* mutable copy */
89 struct clk *sysclk, *coreclk;
90 struct clockgen_pll pll[6];
91 struct clk *cmux[NUM_CMUX];
92 struct clk *hwaccel[NUM_HWACCEL];
94 struct ccsr_guts __iomem *guts;
97 static struct clockgen clockgen;
99 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
101 if (cg->info.flags & CG_LITTLE_ENDIAN)
104 iowrite32be(val, reg);
107 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
111 if (cg->info.flags & CG_LITTLE_ENDIAN)
114 val = ioread32be(reg);
119 static const struct clockgen_muxinfo p2041_cmux_grp1 = {
121 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
122 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
123 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
127 static const struct clockgen_muxinfo p2041_cmux_grp2 = {
129 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
130 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
131 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
135 static const struct clockgen_muxinfo p5020_cmux_grp1 = {
137 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
138 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
139 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
143 static const struct clockgen_muxinfo p5020_cmux_grp2 = {
145 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
146 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
147 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
151 static const struct clockgen_muxinfo p5040_cmux_grp1 = {
153 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
154 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
155 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
156 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
160 static const struct clockgen_muxinfo p5040_cmux_grp2 = {
162 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
163 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
164 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
165 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
169 static const struct clockgen_muxinfo p4080_cmux_grp1 = {
171 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
172 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
173 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
174 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
175 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
179 static const struct clockgen_muxinfo p4080_cmux_grp2 = {
181 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
182 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
183 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
184 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
185 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
189 static const struct clockgen_muxinfo t1023_cmux = {
191 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
192 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
196 static const struct clockgen_muxinfo t1040_cmux = {
198 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
199 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
200 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
201 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
206 static const struct clockgen_muxinfo clockgen2_cmux_cga = {
208 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
209 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
212 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
213 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
216 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
217 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
222 static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
224 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
225 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
228 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
229 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
234 static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
236 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
237 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
240 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
241 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
246 static const struct clockgen_muxinfo ls1028a_hwa1 = {
248 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
249 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
250 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
254 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
255 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
259 static const struct clockgen_muxinfo ls1028a_hwa2 = {
261 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
262 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
263 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
267 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
268 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
272 static const struct clockgen_muxinfo ls1028a_hwa3 = {
274 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
275 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
276 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
278 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
280 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
281 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
285 static const struct clockgen_muxinfo ls1028a_hwa4 = {
287 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
288 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
289 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
293 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
294 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
298 static const struct clockgen_muxinfo ls1043a_hwa1 = {
302 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
306 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
307 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
311 static const struct clockgen_muxinfo ls1043a_hwa2 = {
314 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
316 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
320 static const struct clockgen_muxinfo ls1046a_hwa1 = {
324 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
325 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
326 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
327 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
328 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
329 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
333 static const struct clockgen_muxinfo ls1046a_hwa2 = {
336 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
337 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
341 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
345 static const struct clockgen_muxinfo ls1012a_cmux = {
347 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
349 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
353 static const struct clockgen_muxinfo t1023_hwa1 = {
356 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
357 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
358 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
362 static const struct clockgen_muxinfo t1023_hwa2 = {
364 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
368 static const struct clockgen_muxinfo t2080_hwa1 = {
371 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
372 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
373 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
374 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
375 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
376 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
377 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
381 static const struct clockgen_muxinfo t2080_hwa2 = {
384 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
385 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
386 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
387 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
388 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
389 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
390 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
394 static const struct clockgen_muxinfo t4240_hwa1 = {
396 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
397 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
398 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
399 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
400 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
402 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
403 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
407 static const struct clockgen_muxinfo t4240_hwa4 = {
409 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
410 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
411 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
412 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
413 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
417 static const struct clockgen_muxinfo t4240_hwa5 = {
419 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
420 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
421 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
422 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
423 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
424 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
428 #define RCWSR7_FM1_CLK_SEL 0x40000000
429 #define RCWSR7_FM2_CLK_SEL 0x20000000
430 #define RCWSR7_HWA_ASYNC_DIV 0x04000000
432 static void __init p2041_init_periph(struct clockgen *cg)
436 reg = ioread32be(&cg->guts->rcwsr[7]);
438 if (reg & RCWSR7_FM1_CLK_SEL)
439 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
441 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
444 static void __init p4080_init_periph(struct clockgen *cg)
448 reg = ioread32be(&cg->guts->rcwsr[7]);
450 if (reg & RCWSR7_FM1_CLK_SEL)
451 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
453 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
455 if (reg & RCWSR7_FM2_CLK_SEL)
456 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
458 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
461 static void __init p5020_init_periph(struct clockgen *cg)
466 reg = ioread32be(&cg->guts->rcwsr[7]);
467 if (reg & RCWSR7_HWA_ASYNC_DIV)
470 if (reg & RCWSR7_FM1_CLK_SEL)
471 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
473 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
476 static void __init p5040_init_periph(struct clockgen *cg)
481 reg = ioread32be(&cg->guts->rcwsr[7]);
482 if (reg & RCWSR7_HWA_ASYNC_DIV)
485 if (reg & RCWSR7_FM1_CLK_SEL)
486 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
488 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
490 if (reg & RCWSR7_FM2_CLK_SEL)
491 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
493 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
496 static void __init t1023_init_periph(struct clockgen *cg)
498 cg->fman[0] = cg->hwaccel[1];
501 static void __init t1040_init_periph(struct clockgen *cg)
503 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
506 static void __init t2080_init_periph(struct clockgen *cg)
508 cg->fman[0] = cg->hwaccel[0];
511 static void __init t4240_init_periph(struct clockgen *cg)
513 cg->fman[0] = cg->hwaccel[3];
514 cg->fman[1] = cg->hwaccel[4];
517 static const struct clockgen_chipinfo chipinfo[] = {
519 .compat = "fsl,b4420-clockgen",
520 .guts_compat = "fsl,b4860-device-config",
521 .init_periph = t2080_init_periph,
523 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
532 .flags = CG_PLL_8BIT,
535 .compat = "fsl,b4860-clockgen",
536 .guts_compat = "fsl,b4860-device-config",
537 .init_periph = t2080_init_periph,
539 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
548 .flags = CG_PLL_8BIT,
551 .compat = "fsl,ls1021a-clockgen",
561 .compat = "fsl,ls1028a-clockgen",
563 &clockgen2_cmux_cga12
566 &ls1028a_hwa1, &ls1028a_hwa2,
567 &ls1028a_hwa3, &ls1028a_hwa4
573 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
576 .compat = "fsl,ls1043a-clockgen",
577 .init_periph = t2080_init_periph,
582 &ls1043a_hwa1, &ls1043a_hwa2
588 .flags = CG_PLL_8BIT,
591 .compat = "fsl,ls1046a-clockgen",
592 .init_periph = t2080_init_periph,
597 &ls1046a_hwa1, &ls1046a_hwa2
603 .flags = CG_PLL_8BIT,
606 .compat = "fsl,ls1088a-clockgen",
608 &clockgen2_cmux_cga12
614 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
617 .compat = "fsl,ls1012a-clockgen",
627 .compat = "fsl,ls2080a-clockgen",
629 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
635 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
638 .compat = "fsl,p2041-clockgen",
639 .guts_compat = "fsl,qoriq-device-config-1.0",
640 .init_periph = p2041_init_periph,
642 &p2041_cmux_grp1, &p2041_cmux_grp2
650 .compat = "fsl,p3041-clockgen",
651 .guts_compat = "fsl,qoriq-device-config-1.0",
652 .init_periph = p2041_init_periph,
654 &p2041_cmux_grp1, &p2041_cmux_grp2
662 .compat = "fsl,p4080-clockgen",
663 .guts_compat = "fsl,qoriq-device-config-1.0",
664 .init_periph = p4080_init_periph,
666 &p4080_cmux_grp1, &p4080_cmux_grp2
669 0, 0, 0, 0, 1, 1, 1, 1, -1
674 .compat = "fsl,p5020-clockgen",
675 .guts_compat = "fsl,qoriq-device-config-1.0",
676 .init_periph = p5020_init_periph,
678 &p2041_cmux_grp1, &p2041_cmux_grp2
686 .compat = "fsl,p5040-clockgen",
687 .guts_compat = "fsl,p5040-device-config",
688 .init_periph = p5040_init_periph,
690 &p5040_cmux_grp1, &p5040_cmux_grp2
698 .compat = "fsl,t1023-clockgen",
699 .guts_compat = "fsl,t1023-device-config",
700 .init_periph = t1023_init_periph,
705 &t1023_hwa1, &t1023_hwa2
711 .flags = CG_PLL_8BIT,
714 .compat = "fsl,t1040-clockgen",
715 .guts_compat = "fsl,t1040-device-config",
716 .init_periph = t1040_init_periph,
724 .flags = CG_PLL_8BIT,
727 .compat = "fsl,t2080-clockgen",
728 .guts_compat = "fsl,t2080-device-config",
729 .init_periph = t2080_init_periph,
731 &clockgen2_cmux_cga12
734 &t2080_hwa1, &t2080_hwa2
740 .flags = CG_PLL_8BIT,
743 .compat = "fsl,t4240-clockgen",
744 .guts_compat = "fsl,t4240-device-config",
745 .init_periph = t4240_init_periph,
747 &clockgen2_cmux_cga, &clockgen2_cmux_cgb
750 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
756 .flags = CG_PLL_8BIT,
764 const struct clockgen_muxinfo *info;
766 u8 parent_to_clksel[NUM_MUX_PARENTS];
767 s8 clksel_to_parent[NUM_MUX_PARENTS];
771 #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
772 #define CLKSEL_MASK 0x78000000
773 #define CLKSEL_SHIFT 27
775 static int mux_set_parent(struct clk_hw *hw, u8 idx)
777 struct mux_hwclock *hwc = to_mux_hwclock(hw);
780 if (idx >= hwc->num_parents)
783 clksel = hwc->parent_to_clksel[idx];
784 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
789 static u8 mux_get_parent(struct clk_hw *hw)
791 struct mux_hwclock *hwc = to_mux_hwclock(hw);
795 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
797 ret = hwc->clksel_to_parent[clksel];
799 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
806 static const struct clk_ops cmux_ops = {
807 .get_parent = mux_get_parent,
808 .set_parent = mux_set_parent,
812 * Don't allow setting for now, as the clock options haven't been
813 * sanitized for additional restrictions.
815 static const struct clk_ops hwaccel_ops = {
816 .get_parent = mux_get_parent,
819 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
820 struct mux_hwclock *hwc,
825 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
828 pll = hwc->info->clksel[idx].pll;
829 div = hwc->info->clksel[idx].div;
831 return &cg->pll[pll].div[div];
834 static struct clk * __init create_mux_common(struct clockgen *cg,
835 struct mux_hwclock *hwc,
836 const struct clk_ops *ops,
837 unsigned long min_rate,
838 unsigned long max_rate,
839 unsigned long pct80_rate,
840 const char *fmt, int idx)
842 struct clk_init_data init = {};
844 const struct clockgen_pll_div *div;
845 const char *parent_names[NUM_MUX_PARENTS];
849 snprintf(name, sizeof(name), fmt, idx);
851 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
854 hwc->clksel_to_parent[i] = -1;
856 div = get_pll_div(cg, hwc, i);
860 rate = clk_get_rate(div->clk);
862 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
870 parent_names[j] = div->name;
871 hwc->parent_to_clksel[j] = i;
872 hwc->clksel_to_parent[i] = j;
878 init.parent_names = parent_names;
879 init.num_parents = hwc->num_parents = j;
881 hwc->hw.init = &init;
884 clk = clk_register(NULL, &hwc->hw);
886 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
895 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
897 struct mux_hwclock *hwc;
898 const struct clockgen_pll_div *div;
899 unsigned long plat_rate, min_rate;
900 u64 max_rate, pct80_rate;
903 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
907 if (cg->info.flags & CG_VER3)
908 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
910 hwc->reg = cg->regs + 0x20 * idx;
912 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
915 * Find the rate for the default clksel, and treat it as the
916 * maximum rated core frequency. If this is an incorrect
917 * assumption, certain clock options (possibly including the
918 * default clksel) may be inappropriately excluded on certain
921 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
922 div = get_pll_div(cg, hwc, clksel);
928 max_rate = clk_get_rate(div->clk);
929 pct80_rate = max_rate * 8;
930 do_div(pct80_rate, 10);
932 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
934 if (cg->info.flags & CG_CMUX_GE_PLAT)
935 min_rate = plat_rate;
937 min_rate = plat_rate / 2;
939 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
940 pct80_rate, "cg-cmux%d", idx);
943 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
945 struct mux_hwclock *hwc;
947 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
951 hwc->reg = cg->regs + 0x20 * idx + 0x10;
952 hwc->info = cg->info.hwaccel[idx];
954 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
955 "cg-hwaccel%d", idx);
958 static void __init create_muxes(struct clockgen *cg)
962 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
963 if (cg->info.cmux_to_group[i] < 0)
965 if (cg->info.cmux_to_group[i] >=
966 ARRAY_SIZE(cg->info.cmux_groups)) {
971 cg->cmux[i] = create_one_cmux(cg, i);
974 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
975 if (!cg->info.hwaccel[i])
978 cg->hwaccel[i] = create_one_hwaccel(cg, i);
982 static void __init clockgen_init(struct device_node *np);
985 * Legacy nodes may get probed before the parent clockgen node.
986 * It is assumed that device trees with legacy nodes will not
987 * contain a "clocks" property -- otherwise the input clocks may
988 * not be initialized at this point.
990 static void __init legacy_init_clockgen(struct device_node *np)
993 clockgen_init(of_get_parent(np));
997 static void __init core_mux_init(struct device_node *np)
1000 struct resource res;
1003 legacy_init_clockgen(np);
1005 if (of_address_to_resource(np, 0, &res))
1008 idx = (res.start & 0xf0) >> 5;
1009 clk = clockgen.cmux[idx];
1011 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
1013 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1019 static struct clk __init
1020 *sysclk_from_fixed(struct device_node *node, const char *name)
1024 if (of_property_read_u32(node, "clock-frequency", &rate))
1025 return ERR_PTR(-ENODEV);
1027 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
1030 static struct clk __init *input_clock(const char *name, struct clk *clk)
1032 const char *input_name;
1034 /* Register the input clock under the desired name. */
1035 input_name = __clk_get_name(clk);
1036 clk = clk_register_fixed_factor(NULL, name, input_name,
1039 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
1045 static struct clk __init *input_clock_by_name(const char *name,
1050 clk = of_clk_get_by_name(clockgen.node, dtname);
1054 return input_clock(name, clk);
1057 static struct clk __init *input_clock_by_index(const char *name, int idx)
1061 clk = of_clk_get(clockgen.node, 0);
1065 return input_clock(name, clk);
1068 static struct clk * __init create_sysclk(const char *name)
1070 struct device_node *sysclk;
1073 clk = sysclk_from_fixed(clockgen.node, name);
1077 clk = input_clock_by_name(name, "sysclk");
1081 clk = input_clock_by_index(name, 0);
1085 sysclk = of_get_child_by_name(clockgen.node, "sysclk");
1087 clk = sysclk_from_fixed(sysclk, name);
1092 pr_err("%s: No input sysclk\n", __func__);
1096 static struct clk * __init create_coreclk(const char *name)
1100 clk = input_clock_by_name(name, "coreclk");
1105 * This indicates a mix of legacy nodes with the new coreclk
1106 * mechanism, which should never happen. If this error occurs,
1107 * don't use the wrong input clock just because coreclk isn't
1110 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
1117 static void __init sysclk_init(struct device_node *node)
1121 legacy_init_clockgen(node);
1123 clk = clockgen.sysclk;
1125 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1128 #define PLL_KILL BIT(31)
1130 static void __init create_one_pll(struct clockgen *cg, int idx)
1134 struct clockgen_pll *pll = &cg->pll[idx];
1135 const char *input = "cg-sysclk";
1138 if (!(cg->info.pll_mask & (1 << idx)))
1141 if (cg->coreclk && idx != PLATFORM_PLL) {
1142 if (IS_ERR(cg->coreclk))
1145 input = "cg-coreclk";
1148 if (cg->info.flags & CG_VER3) {
1151 reg = cg->regs + 0x60080;
1154 reg = cg->regs + 0x80;
1157 reg = cg->regs + 0xa0;
1160 reg = cg->regs + 0x10080;
1163 reg = cg->regs + 0x100a0;
1166 WARN_ONCE(1, "index %d\n", idx);
1170 if (idx == PLATFORM_PLL)
1171 reg = cg->regs + 0xc00;
1173 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1176 /* Get the multiple of PLL */
1177 mult = cg_in(cg, reg);
1179 /* Check if this PLL is disabled */
1180 if (mult & PLL_KILL) {
1181 pr_debug("%s(): pll %p disabled\n", __func__, reg);
1185 if ((cg->info.flags & CG_VER3) ||
1186 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1187 mult = (mult & GENMASK(8, 1)) >> 1;
1189 mult = (mult & GENMASK(6, 1)) >> 1;
1191 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
1196 * For platform PLL, there are MAX_PLL_DIV divider clocks.
1197 * For core PLL, there are 4 divider clocks at most.
1199 if (idx != PLATFORM_PLL && i >= 4)
1202 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
1203 "cg-pll%d-div%d", idx, i + 1);
1205 clk = clk_register_fixed_factor(NULL,
1206 pll->div[i].name, input, 0, mult, i + 1);
1208 pr_err("%s: %s: register failed %ld\n",
1209 __func__, pll->div[i].name, PTR_ERR(clk));
1213 pll->div[i].clk = clk;
1214 ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
1216 pr_err("%s: %s: register to lookup table failed %d\n",
1217 __func__, pll->div[i].name, ret);
1222 static void __init create_plls(struct clockgen *cg)
1226 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1227 create_one_pll(cg, i);
1230 static void __init legacy_pll_init(struct device_node *np, int idx)
1232 struct clockgen_pll *pll;
1233 struct clk_onecell_data *onecell_data;
1234 struct clk **subclks;
1237 legacy_init_clockgen(np);
1239 pll = &clockgen.pll[idx];
1240 count = of_property_count_strings(np, "clock-output-names");
1242 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
1243 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
1247 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
1252 subclks[0] = pll->div[0].clk;
1253 subclks[1] = pll->div[1].clk;
1254 subclks[2] = pll->div[3].clk;
1256 subclks[0] = pll->div[0].clk;
1257 subclks[1] = pll->div[1].clk;
1258 subclks[2] = pll->div[2].clk;
1259 subclks[3] = pll->div[3].clk;
1262 onecell_data->clks = subclks;
1263 onecell_data->clk_num = count;
1265 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1267 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1274 kfree(onecell_data);
1280 static void __init pltfrm_pll_init(struct device_node *np)
1282 legacy_pll_init(np, PLATFORM_PLL);
1286 static void __init core_pll_init(struct device_node *np)
1288 struct resource res;
1291 if (of_address_to_resource(np, 0, &res))
1294 if ((res.start & 0xfff) == 0xc00) {
1296 * ls1021a devtree labels the platform PLL
1297 * with the core PLL compatible
1299 pltfrm_pll_init(np);
1301 idx = (res.start & 0xf0) >> 5;
1302 legacy_pll_init(np, CGA_PLL1 + idx);
1306 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
1308 struct clockgen *cg = data;
1310 struct clockgen_pll *pll;
1313 if (clkspec->args_count < 2) {
1314 pr_err("%s: insufficient phandle args\n", __func__);
1315 return ERR_PTR(-EINVAL);
1318 type = clkspec->args[0];
1319 idx = clkspec->args[1];
1328 if (idx >= ARRAY_SIZE(cg->cmux))
1330 clk = cg->cmux[idx];
1333 if (idx >= ARRAY_SIZE(cg->hwaccel))
1335 clk = cg->hwaccel[idx];
1338 if (idx >= ARRAY_SIZE(cg->fman))
1340 clk = cg->fman[idx];
1343 pll = &cg->pll[PLATFORM_PLL];
1344 if (idx >= ARRAY_SIZE(pll->div))
1346 clk = pll->div[idx].clk;
1360 return ERR_PTR(-ENOENT);
1364 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
1365 return ERR_PTR(-EINVAL);
1369 #include <asm/mpc85xx.h>
1371 static const u32 a4510_svrs[] __initconst = {
1372 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
1373 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
1374 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
1375 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
1376 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
1377 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
1378 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
1379 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
1380 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
1381 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
1382 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
1383 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
1384 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
1387 #define SVR_SECURITY 0x80000 /* The Security (E) bit */
1389 static bool __init has_erratum_a4510(void)
1391 u32 svr = mfspr(SPRN_SVR);
1394 svr &= ~SVR_SECURITY;
1396 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
1397 if (svr == a4510_svrs[i])
1404 static bool __init has_erratum_a4510(void)
1410 static void __init clockgen_init(struct device_node *np)
1413 bool is_old_ls1021a = false;
1415 /* May have already been called by a legacy probe */
1420 clockgen.regs = of_iomap(np, 0);
1421 if (!clockgen.regs &&
1422 of_device_is_compatible(of_root, "fsl,ls1021a")) {
1423 /* Compatibility hack for old, broken device trees */
1424 clockgen.regs = ioremap(0x1ee1000, 0x1000);
1425 is_old_ls1021a = true;
1427 if (!clockgen.regs) {
1428 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
1432 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
1433 if (of_device_is_compatible(np, chipinfo[i].compat))
1435 if (is_old_ls1021a &&
1436 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
1440 if (i == ARRAY_SIZE(chipinfo)) {
1441 pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
1444 clockgen.info = chipinfo[i];
1446 if (clockgen.info.guts_compat) {
1447 struct device_node *guts;
1449 guts = of_find_compatible_node(NULL, NULL,
1450 clockgen.info.guts_compat);
1452 clockgen.guts = of_iomap(guts, 0);
1453 if (!clockgen.guts) {
1454 pr_err("%s: Couldn't map %pOF regs\n", __func__,
1462 if (has_erratum_a4510())
1463 clockgen.info.flags |= CG_CMUX_GE_PLAT;
1465 clockgen.sysclk = create_sysclk("cg-sysclk");
1466 clockgen.coreclk = create_coreclk("cg-coreclk");
1467 create_plls(&clockgen);
1468 create_muxes(&clockgen);
1470 if (clockgen.info.init_periph)
1471 clockgen.info.init_periph(&clockgen);
1473 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1475 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1481 iounmap(clockgen.regs);
1482 clockgen.regs = NULL;
1485 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1486 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1487 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1488 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1489 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1490 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1491 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1492 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1493 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1494 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1495 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1496 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1497 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1498 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1499 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1500 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1501 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1502 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1503 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1504 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1507 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1508 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1509 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1510 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1511 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1512 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1513 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1514 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);