1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
4 * Pin compatible with the LMK0482x family
6 * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
8 * Copyright (c) 2020, Xiphos Systems Corp.
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/debugfs.h>
16 #include <linux/device.h>
17 #include <linux/gcd.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/module.h>
20 #include <linux/uaccess.h>
21 #include <linux/regmap.h>
22 #include <linux/spi/spi.h>
24 /* 0x000 - 0x00d System Functions */
25 #define LMK04832_REG_RST3W 0x000
26 #define LMK04832_BIT_RESET BIT(7)
27 #define LMK04832_BIT_SPI_3WIRE_DIS BIT(4)
28 #define LMK04832_REG_POWERDOWN 0x002
29 #define LMK04832_REG_ID_DEV_TYPE 0x003
30 #define LMK04832_REG_ID_PROD_MSB 0x004
31 #define LMK04832_REG_ID_PROD_LSB 0x005
32 #define LMK04832_REG_ID_MASKREV 0x006
33 #define LMK04832_REG_ID_VNDR_MSB 0x00c
34 #define LMK04832_REG_ID_VNDR_LSB 0x00d
36 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
37 #define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8)
38 #define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0)
39 #define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8)
40 #define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0)
41 #define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8)
42 #define LMK04832_BIT_CLKOUTX_Y_PD BIT(7)
43 #define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4)
44 #define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2)
45 #define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0)
46 #define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8)
47 #define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5)
48 #define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8)
49 #define LMK04832_BIT_DCLKX_Y_PD BIT(4)
50 #define LMK04832_BIT_DCLKX_Y_DCC BIT(2)
51 #define LMK04832_BIT_DCLKX_Y_HS BIT(0)
52 #define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8)
53 #define LMK04832_BIT_SCLK_PD BIT(4)
54 #define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2)
55 #define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8)
56 #define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8)
57 #define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0)
58 #define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8)
59 #define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f)
60 #define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00
61 #define LMK04832_VAL_CLKOUT_FMT_LVDS 0x01
62 #define LMK04832_VAL_CLKOUT_FMT_HSDS6 0x02
63 #define LMK04832_VAL_CLKOUT_FMT_HSDS8 0x03
64 #define LMK04832_VAL_CLKOUT_FMT_LVPECL1600 0x04
65 #define LMK04832_VAL_CLKOUT_FMT_LVPECL2000 0x05
66 #define LMK04832_VAL_CLKOUT_FMT_LCPECL 0x06
67 #define LMK04832_VAL_CLKOUT_FMT_CML16 0x07
68 #define LMK04832_VAL_CLKOUT_FMT_CML24 0x08
69 #define LMK04832_VAL_CLKOUT_FMT_CML32 0x09
70 #define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV 0x0a
71 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF 0x0b
72 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV 0x0c
73 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR 0x0d
74 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV 0x0e
75 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR 0x0f
77 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
78 #define LMK04832_REG_VCO_OSCOUT 0x138
79 #define LMK04832_BIT_VCO_MUX GENMASK(6, 5)
80 #define LMK04832_VAL_VCO_MUX_VCO0 0x00
81 #define LMK04832_VAL_VCO_MUX_VCO1 0x01
82 #define LMK04832_VAL_VCO_MUX_EXT 0x02
83 #define LMK04832_REG_SYSREF_OUT 0x139
84 #define LMK04832_BIT_SYSREF_REQ_EN BIT(6)
85 #define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0)
86 #define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00
87 #define LMK04832_VAL_SYSREF_MUX_RECLK 0x01
88 #define LMK04832_VAL_SYSREF_MUX_PULSER 0x02
89 #define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03
90 #define LMK04832_REG_SYSREF_DIV_MSB 0x13a
91 #define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0)
92 #define LMK04832_REG_SYSREF_DIV_LSB 0x13b
93 #define LMK04832_REG_SYSREF_DDLY_MSB 0x13c
94 #define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0)
95 #define LMK04832_REG_SYSREF_DDLY_LSB 0x13d
96 #define LMK04832_REG_SYSREF_PULSE_CNT 0x13e
97 #define LMK04832_REG_FB_CTRL 0x13f
98 #define LMK04832_BIT_PLL2_RCLK_MUX BIT(7)
99 #define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00
100 #define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN 0x01
101 #define LMK04832_BIT_PLL2_NCLK_MUX BIT(5)
102 #define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00
103 #define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX 0x01
104 #define LMK04832_BIT_FB_MUX_EN BIT(0)
105 #define LMK04832_REG_MAIN_PD 0x140
106 #define LMK04832_BIT_PLL1_PD BIT(7)
107 #define LMK04832_BIT_VCO_LDO_PD BIT(6)
108 #define LMK04832_BIT_VCO_PD BIT(5)
109 #define LMK04832_BIT_OSCIN_PD BIT(4)
110 #define LMK04832_BIT_SYSREF_GBL_PD BIT(3)
111 #define LMK04832_BIT_SYSREF_PD BIT(2)
112 #define LMK04832_BIT_SYSREF_DDLY_PD BIT(1)
113 #define LMK04832_BIT_SYSREF_PLSR_PD BIT(0)
114 #define LMK04832_REG_SYNC 0x143
115 #define LMK04832_BIT_SYNC_CLR BIT(7)
116 #define LMK04832_BIT_SYNC_1SHOT_EN BIT(6)
117 #define LMK04832_BIT_SYNC_POL BIT(5)
118 #define LMK04832_BIT_SYNC_EN BIT(4)
119 #define LMK04832_BIT_SYNC_MODE GENMASK(1, 0)
120 #define LMK04832_VAL_SYNC_MODE_OFF 0x00
121 #define LMK04832_VAL_SYNC_MODE_ON 0x01
122 #define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02
123 #define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03
124 #define LMK04832_REG_SYNC_DIS 0x144
126 /* 0x146 - 0x14a CLKin Control */
127 #define LMK04832_REG_CLKIN_SEL0 0x148
128 #define LMK04832_REG_CLKIN_SEL1 0x149
129 #define LMK04832_REG_CLKIN_RST 0x14a
130 #define LMK04832_BIT_SDIO_RDBK_TYPE BIT(6)
131 #define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3)
132 #define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK 0x06
133 #define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0)
134 #define LMK04832_VAL_CLKIN_SEL_TYPE_OUT 0x03
136 /* 0x14b - 0x152 Holdover */
138 /* 0x153 - 0x15f PLL1 Configuration */
140 /* 0x160 - 0x16e PLL2 Configuration */
141 #define LMK04832_REG_PLL2_R_MSB 0x160
142 #define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0)
143 #define LMK04832_REG_PLL2_R_LSB 0x161
144 #define LMK04832_REG_PLL2_MISC 0x162
145 #define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5)
146 #define LMK04832_BIT_PLL2_MISC_REF_2X_EN BIT(0)
147 #define LMK04832_REG_PLL2_N_CAL_0 0x163
148 #define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0)
149 #define LMK04832_REG_PLL2_N_CAL_1 0x164
150 #define LMK04832_REG_PLL2_N_CAL_2 0x165
151 #define LMK04832_REG_PLL2_N_0 0x166
152 #define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0)
153 #define LMK04832_REG_PLL2_N_1 0x167
154 #define LMK04832_REG_PLL2_N_2 0x168
155 #define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a
156 #define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b
157 #define LMK04832_REG_PLL2_LD 0x16e
158 #define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3)
159 #define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD 0x02
160 #define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0)
161 #define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP 0x03
163 /* 0x16F - 0x555 Misc Registers */
164 #define LMK04832_REG_PLL2_PD 0x173
165 #define LMK04832_BIT_PLL2_PRE_PD BIT(6)
166 #define LMK04832_BIT_PLL2_PD BIT(5)
167 #define LMK04832_REG_PLL1R_RST 0x177
168 #define LMK04832_REG_CLR_PLL_LOST 0x182
169 #define LMK04832_REG_RB_PLL_LD 0x183
170 #define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184
171 #define LMK04832_REG_RB_DAC_VAL_LSB 0x185
172 #define LMK04832_REG_RB_HOLDOVER 0x188
173 #define LMK04832_REG_SPI_LOCK 0x555
175 enum lmk04832_device_types {
180 * lmk04832_device_info - Holds static device information that is specific to
183 * pid: Product Identifier
184 * maskrev: IC version identifier
185 * num_channels: Number of available output channels (clkout count)
186 * vco0_range: {min, max} of the VCO0 operating range (in MHz)
187 * vco1_range: {min, max} of the VCO1 operating range (in MHz)
189 struct lmk04832_device_info {
193 unsigned int vco0_range[2];
194 unsigned int vco1_range[2];
197 static const struct lmk04832_device_info lmk04832_device_info[] = {
199 .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */
202 .vco0_range = { 2440, 2580 },
203 .vco1_range = { 2945, 3255 },
207 enum lmk04832_rdbk_type {
214 struct lmk04832 *lmk;
220 struct lmk04832 *lmk;
228 * struct lmk04832 - The LMK04832 device structure
230 * @dev: reference to a struct device, linked to the spi_device
231 * @regmap: struct regmap instance use to access the chip
232 * @sync_mode: operational mode for SYNC signal
233 * @sysref_mux: select SYSREF source
234 * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
236 * @sysref_ddly: SYSREF digital delay value
237 * @oscin: PLL2 input clock
238 * @vco: reference to the internal VCO clock
239 * @sclk: reference to the internal sysref clock (SCLK)
240 * @vco_rate: user provided VCO rate
241 * @reset_gpio: reference to the reset GPIO
242 * @dclk: list of internal device clock references.
243 * Each pair of clkout clocks share a single device clock (DCLKX_Y)
244 * @clkout: list of output clock references
245 * @clk_data: holds clkout related data like clk_hw* and number of clocks
249 struct regmap *regmap;
251 unsigned int sync_mode;
252 unsigned int sysref_mux;
253 unsigned int sysref_pulse_cnt;
254 unsigned int sysref_ddly;
259 unsigned int vco_rate;
261 struct gpio_desc *reset_gpio;
263 struct lmk_dclk *dclk;
264 struct lmk_clkout *clkout;
265 struct clk_hw_onecell_data *clk_data;
268 static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
271 case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV:
273 case LMK04832_REG_ID_VNDR_MSB:
275 case LMK04832_REG_ID_VNDR_LSB:
277 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
279 case LMK04832_REG_PLL2_LD:
281 case LMK04832_REG_PLL2_PD:
283 case LMK04832_REG_PLL1R_RST:
285 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
287 case LMK04832_REG_RB_HOLDOVER:
289 case LMK04832_REG_SPI_LOCK:
296 static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
299 case LMK04832_REG_RST3W:
301 case LMK04832_REG_POWERDOWN:
303 case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV:
305 case LMK04832_REG_ID_VNDR_MSB:
307 case LMK04832_REG_ID_VNDR_LSB:
309 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
311 case LMK04832_REG_PLL2_LD:
313 case LMK04832_REG_PLL2_PD:
315 case LMK04832_REG_PLL1R_RST:
317 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
319 case LMK04832_REG_RB_HOLDOVER:
321 case LMK04832_REG_SPI_LOCK:
328 static const struct regmap_config regmap_config = {
332 .use_single_read = 1,
333 .use_single_write = 1,
334 .read_flag_mask = 0x80,
335 .write_flag_mask = 0x00,
336 .readable_reg = lmk04832_regmap_rd_regs,
337 .writeable_reg = lmk04832_regmap_wr_regs,
338 .cache_type = REGCACHE_NONE,
339 .max_register = LMK04832_REG_SPI_LOCK,
342 static int lmk04832_vco_is_enabled(struct clk_hw *hw)
344 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
348 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
352 return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) |
353 FIELD_GET(LMK04832_BIT_VCO_PD, tmp) |
354 FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp));
357 static int lmk04832_vco_prepare(struct clk_hw *hw)
359 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
362 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
363 LMK04832_BIT_PLL2_PRE_PD |
364 LMK04832_BIT_PLL2_PD,
369 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
370 LMK04832_BIT_VCO_LDO_PD |
371 LMK04832_BIT_VCO_PD |
372 LMK04832_BIT_OSCIN_PD, 0x00);
375 static void lmk04832_vco_unprepare(struct clk_hw *hw)
377 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
379 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
380 LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD,
383 /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */
384 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
385 LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff);
388 static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
391 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
392 unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
393 unsigned int pll2_n, p, pll2_r;
394 unsigned int pll2_misc;
395 unsigned long vco_rate;
399 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc);
403 p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc);
405 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3);
409 pll2_n = FIELD_PREP(0x030000, tmp[0]) |
410 FIELD_PREP(0x00ff00, tmp[1]) |
411 FIELD_PREP(0x0000ff, tmp[2]);
413 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2);
417 pll2_r = FIELD_PREP(0x0f00, tmp[0]) |
418 FIELD_PREP(0x00ff, tmp[1]);
420 vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN,
421 pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
427 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
429 * @lmk: Reference to the lmk device
430 * @rate: Desired output rate for the VCO
432 * The LMK04832 has 2 internal VCO, each with independent operating ranges.
433 * Use the device_info structure to determine which VCO to use based on rate.
435 * Returns VCO_MUX value or negative errno.
437 static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
439 struct spi_device *spi = to_spi_device(lmk->dev);
440 const struct lmk04832_device_info *info;
441 unsigned long mhz = rate / 1000000;
443 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
445 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1])
446 return LMK04832_VAL_VCO_MUX_VCO0;
448 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1])
449 return LMK04832_VAL_VCO_MUX_VCO1;
451 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate);
456 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
458 * @prate: parent rate to the PLL2, usually OSCin
459 * @rate: Desired output rate for the VCO
460 * @n: reference to PLL2_N
461 * @p: reference to PLL2_P
462 * @r: reference to PLL2_R
464 * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is
465 * recommended in the datasheet because a higher phase detector frequencies
466 * makes the design of wider loop bandwidth filters possible.
468 * the VCO rate can be calculated using the following expression:
470 * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
472 * Returns vco rate or negative errno.
474 static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
475 unsigned int *n, unsigned int *p,
478 unsigned int pll2_n, pll2_p, pll2_r;
479 unsigned long num, div;
481 /* Set PLL2_P to a fixed value to simplify optimizations */
484 div = gcd(rate, prate);
486 num = DIV_ROUND_CLOSEST(rate, div);
487 pll2_r = DIV_ROUND_CLOSEST(prate, div);
492 pll2_r = pll2_r << 2;
496 if (pll2_n < 1 || pll2_n > 0x03ffff)
498 if (pll2_r < 1 || pll2_r > 0xfff)
505 return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r);
508 static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
509 unsigned long *prate)
511 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
512 unsigned int n, p, r;
516 ret = lmk04832_check_vco_ranges(lmk, rate);
520 vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
522 dev_err(lmk->dev, "PLL2 parmeters out of range\n");
526 if (rate != vco_rate)
532 static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
535 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
536 unsigned int n, p, r;
541 vco_mux = lmk04832_check_vco_ranges(lmk, rate);
545 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
546 LMK04832_BIT_VCO_MUX,
547 FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux));
551 vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
553 dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");
557 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB,
558 LMK04832_BIT_PLL2_R_MSB,
559 FIELD_GET(0x000700, r));
563 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB,
564 FIELD_GET(0x0000ff, r));
568 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
569 LMK04832_BIT_PLL2_MISC_P,
570 FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p));
575 * PLL2_N registers must be programmed after other PLL2 dividers are
576 * programed to ensure proper VCO frequency calibration
578 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
579 FIELD_GET(0x030000, n));
582 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1,
583 FIELD_GET(0x00ff00, n));
587 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
588 FIELD_GET(0x0000ff, n));
591 static const struct clk_ops lmk04832_vco_ops = {
592 .is_enabled = lmk04832_vco_is_enabled,
593 .prepare = lmk04832_vco_prepare,
594 .unprepare = lmk04832_vco_unprepare,
595 .recalc_rate = lmk04832_vco_recalc_rate,
596 .round_rate = lmk04832_vco_round_rate,
597 .set_rate = lmk04832_vco_set_rate,
601 * lmk04832_register_vco - Initialize the internal VCO and clock distribution
602 * path in PLL2 single loop mode.
604 static int lmk04832_register_vco(struct lmk04832 *lmk)
606 const char *parent_names[1];
607 struct clk_init_data init;
610 init.name = "lmk-vco";
611 parent_names[0] = __clk_get_name(lmk->oscin);
612 init.parent_names = parent_names;
614 init.ops = &lmk04832_vco_ops;
615 init.num_parents = 1;
617 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
618 LMK04832_BIT_VCO_MUX,
619 FIELD_PREP(LMK04832_BIT_VCO_MUX,
620 LMK04832_VAL_VCO_MUX_VCO1));
624 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL,
625 LMK04832_BIT_PLL2_RCLK_MUX |
626 LMK04832_BIT_PLL2_NCLK_MUX,
627 FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX,
628 LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)|
629 FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX,
630 LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P));
634 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
635 LMK04832_BIT_PLL2_MISC_REF_2X_EN,
636 LMK04832_BIT_PLL2_MISC_REF_2X_EN);
640 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD,
641 FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX,
642 LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) |
643 FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE,
644 LMK04832_VAL_PLL2_LD_TYPE_OUT_PP));
648 lmk->vco.init = &init;
649 return devm_clk_hw_register(lmk->dev, &lmk->vco);
652 static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
654 int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
655 unsigned int sclkx_y_ddly = 10;
656 unsigned int dclkx_y_ddly;
657 unsigned int dclkx_y_div;
658 unsigned int sysref_ddly;
659 unsigned int dclkx_y_hs;
660 unsigned int lsb, msb;
663 ret = regmap_update_bits(lmk->regmap,
664 LMK04832_REG_CLKOUT_CTRL2(id),
665 LMK04832_BIT_DCLKX_Y_DDLY_PD,
666 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
670 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
674 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
678 sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
680 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
684 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
688 dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
690 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
694 dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
696 dclkx_y_ddly = sysref_ddly + 1 -
697 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] -
698 dclkx_y_hs + sclkx_y_ddly;
700 if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
701 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
706 ret = regmap_write(lmk->regmap,
707 LMK04832_REG_SCLKX_Y_DDLY(id),
708 FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
712 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
713 FIELD_GET(0x00ff, dclkx_y_ddly));
717 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
718 "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
719 id, sysref_ddly, dclkx_y_ddly,
720 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
721 dclkx_y_hs, sclkx_y_ddly);
723 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
724 LMK04832_BIT_DCLKX_Y_DDLY_MSB,
725 FIELD_GET(0x0300, dclkx_y_ddly));
728 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
731 * @lmk: Reference to the lmk device
733 * The synchronization sequence:
734 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
735 * (8.3.3.1 How to enable SYSREF)
736 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
738 * Returns 0 or negative errno.
740 static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
745 /* 1. (optional) mute all sysref_outputs during synchronization */
746 /* 2. Enable and write device clock digital delay to applicable clocks */
747 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
748 LMK04832_BIT_SYSREF_DDLY_PD,
749 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
753 for (i = 0; i < lmk->clk_data->num; i += 2) {
754 ret = lmk04832_clkout_set_ddly(lmk, i);
760 * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
761 * and clear SYSREF_REQ_EN (see 6.)
763 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
764 LMK04832_BIT_SYSREF_REQ_EN |
765 LMK04832_BIT_SYSREF_MUX,
766 FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
767 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
768 LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
772 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
773 LMK04832_BIT_SYNC_MODE,
774 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
775 LMK04832_VAL_SYNC_MODE_ON));
779 /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
780 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
785 * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
786 * distribution path cycles (VCO cycles), then back to 0. In
787 * PLL2-only use case, this will be complete in less than one SPI
788 * transaction. If SYSREF local digital delay is not used, this step
791 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
792 LMK04832_BIT_SYNC_CLR,
793 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
797 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
798 LMK04832_BIT_SYNC_CLR,
799 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
804 * 6. Toggle SYNC_POL state between inverted and not inverted.
805 * If you use an external signal on the SYNC pin instead of toggling
806 * SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
807 * does not shift into continuous SYSREF mode.
809 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
810 LMK04832_BIT_SYNC_POL,
811 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
815 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
816 LMK04832_BIT_SYNC_POL,
817 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
821 /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
822 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
826 /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
827 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
828 LMK04832_BIT_SYSREF_MUX,
829 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
834 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
835 LMK04832_BIT_SYNC_MODE,
836 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
842 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
843 * during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
844 * or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
849 * 10. (optional) To reduce power consumption, after the synchronization
850 * event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
851 * digital delay counters (which are only used immediately after the
852 * SYNC pulse to delay the output by some number of VCO counts).
858 static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
860 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
864 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
868 return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp);
871 static int lmk04832_sclk_prepare(struct clk_hw *hw)
873 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
875 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
876 LMK04832_BIT_SYSREF_PD, 0x00);
879 static void lmk04832_sclk_unprepare(struct clk_hw *hw)
881 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
883 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
884 LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD);
887 static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw,
890 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
891 unsigned int sysref_div;
895 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2);
899 sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 |
902 return DIV_ROUND_CLOSEST(prate, sysref_div);
905 static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate,
906 unsigned long *prate)
908 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
909 unsigned long sclk_rate;
910 unsigned int sysref_div;
912 sysref_div = DIV_ROUND_CLOSEST(*prate, rate);
913 sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div);
915 if (sysref_div < 0x07 || sysref_div > 0x1fff) {
916 dev_err(lmk->dev, "SYSREF divider out of range\n");
920 if (rate != sclk_rate)
926 static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
929 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
930 unsigned int sysref_div;
933 sysref_div = DIV_ROUND_CLOSEST(prate, rate);
935 if (sysref_div < 0x07 || sysref_div > 0x1fff) {
936 dev_err(lmk->dev, "SYSREF divider out of range\n");
940 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB,
941 FIELD_GET(0x1f00, sysref_div));
945 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
946 FIELD_GET(0x00ff, sysref_div));
950 ret = lmk04832_sclk_sync_sequence(lmk);
952 dev_err(lmk->dev, "SYNC sequence failed\n");
957 static const struct clk_ops lmk04832_sclk_ops = {
958 .is_enabled = lmk04832_sclk_is_enabled,
959 .prepare = lmk04832_sclk_prepare,
960 .unprepare = lmk04832_sclk_unprepare,
961 .recalc_rate = lmk04832_sclk_recalc_rate,
962 .round_rate = lmk04832_sclk_round_rate,
963 .set_rate = lmk04832_sclk_set_rate,
966 static int lmk04832_register_sclk(struct lmk04832 *lmk)
968 const char *parent_names[1];
969 struct clk_init_data init;
972 init.name = "lmk-sclk";
973 parent_names[0] = clk_hw_get_name(&lmk->vco);
974 init.parent_names = parent_names;
976 init.ops = &lmk04832_sclk_ops;
977 init.flags = CLK_SET_RATE_PARENT;
978 init.num_parents = 1;
980 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
981 LMK04832_BIT_SYSREF_MUX,
982 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
987 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
988 FIELD_GET(0x00ff, lmk->sysref_ddly));
992 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
993 FIELD_GET(0x1f00, lmk->sysref_ddly));
997 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
998 ilog2(lmk->sysref_pulse_cnt));
1002 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
1003 LMK04832_BIT_SYSREF_DDLY_PD |
1004 LMK04832_BIT_SYSREF_PLSR_PD,
1005 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
1006 FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
1010 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
1011 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
1012 FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
1013 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
1017 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
1021 lmk->sclk.init = &init;
1022 return devm_clk_hw_register(lmk->dev, &lmk->sclk);
1025 static int lmk04832_dclk_is_enabled(struct clk_hw *hw)
1027 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1028 struct lmk04832 *lmk = dclk->lmk;
1032 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1037 return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp);
1040 static int lmk04832_dclk_prepare(struct clk_hw *hw)
1042 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1043 struct lmk04832 *lmk = dclk->lmk;
1045 return regmap_update_bits(lmk->regmap,
1046 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1047 LMK04832_BIT_DCLKX_Y_PD, 0x00);
1050 static void lmk04832_dclk_unprepare(struct clk_hw *hw)
1052 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1053 struct lmk04832 *lmk = dclk->lmk;
1055 regmap_update_bits(lmk->regmap,
1056 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1057 LMK04832_BIT_DCLKX_Y_PD, 0xff);
1060 static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
1061 unsigned long prate)
1063 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1064 struct lmk04832 *lmk = dclk->lmk;
1065 unsigned int dclk_div;
1066 unsigned int lsb, msb;
1070 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1075 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1080 dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
1081 rate = DIV_ROUND_CLOSEST(prate, dclk_div);
1086 static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
1087 unsigned long *prate)
1089 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1090 struct lmk04832 *lmk = dclk->lmk;
1091 unsigned long dclk_rate;
1092 unsigned int dclk_div;
1094 dclk_div = DIV_ROUND_CLOSEST(*prate, rate);
1095 dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div);
1097 if (dclk_div < 1 || dclk_div > 0x3ff) {
1098 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1102 if (rate != dclk_rate)
1108 static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
1109 unsigned long prate)
1111 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1112 struct lmk04832 *lmk = dclk->lmk;
1113 unsigned int dclk_div;
1116 dclk_div = DIV_ROUND_CLOSEST(prate, rate);
1118 if (dclk_div > 0x3ff) {
1119 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1123 /* Enable Duty Cycle Corretion */
1124 if (dclk_div == 1) {
1125 ret = regmap_update_bits(lmk->regmap,
1126 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1127 LMK04832_BIT_DCLKX_Y_DCC,
1128 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1));
1134 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
1135 * procedure requires to first program Divide-by-4 and then back to
1136 * Divide-by-2 or Divide-by-3 before doing SYNC.
1138 if (dclk_div == 2 || dclk_div == 3) {
1139 ret = regmap_update_bits(lmk->regmap,
1140 LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1141 LMK04832_BIT_DCLK_DIV_MSB, 0x00);
1145 ret = regmap_write(lmk->regmap,
1146 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
1151 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1152 FIELD_GET(0x0ff, dclk_div));
1156 ret = regmap_update_bits(lmk->regmap,
1157 LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1158 LMK04832_BIT_DCLK_DIV_MSB,
1159 FIELD_GET(0x300, dclk_div));
1163 ret = lmk04832_sclk_sync_sequence(lmk);
1165 dev_err(lmk->dev, "SYNC sequence failed\n");
1170 static const struct clk_ops lmk04832_dclk_ops = {
1171 .is_enabled = lmk04832_dclk_is_enabled,
1172 .prepare = lmk04832_dclk_prepare,
1173 .unprepare = lmk04832_dclk_unprepare,
1174 .recalc_rate = lmk04832_dclk_recalc_rate,
1175 .round_rate = lmk04832_dclk_round_rate,
1176 .set_rate = lmk04832_dclk_set_rate,
1179 static int lmk04832_clkout_is_enabled(struct clk_hw *hw)
1181 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1182 struct lmk04832 *lmk = clkout->lmk;
1183 unsigned int clkoutx_y_pd;
1184 unsigned int sclkx_y_pd;
1190 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1195 enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd);
1197 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1202 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1203 ret = regmap_read(lmk->regmap,
1204 LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1209 enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd);
1212 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1218 fmt = FIELD_GET(0xf0, tmp);
1220 fmt = FIELD_GET(0x0f, tmp);
1222 return enabled && !fmt;
1225 static int lmk04832_clkout_prepare(struct clk_hw *hw)
1227 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1228 struct lmk04832 *lmk = clkout->lmk;
1232 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN)
1233 dev_err(lmk->dev, "prepared %s but format is powerdown\n",
1234 clk_hw_get_name(hw));
1236 ret = regmap_update_bits(lmk->regmap,
1237 LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1238 LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
1242 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1247 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1248 ret = regmap_update_bits(lmk->regmap,
1249 LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1250 LMK04832_BIT_SCLK_PD, 0x00);
1255 return regmap_update_bits(lmk->regmap,
1256 LMK04832_REG_CLKOUT_FMT(clkout->id),
1257 LMK04832_BIT_CLKOUT_FMT(clkout->id),
1258 clkout->format << 4 * (clkout->id % 2));
1261 static void lmk04832_clkout_unprepare(struct clk_hw *hw)
1263 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1264 struct lmk04832 *lmk = clkout->lmk;
1266 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1267 LMK04832_BIT_CLKOUT_FMT(clkout->id),
1271 static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)
1273 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1274 struct lmk04832 *lmk = clkout->lmk;
1276 return regmap_update_bits(lmk->regmap,
1277 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1278 LMK04832_BIT_CLKOUT_SRC_MUX,
1279 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1283 static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)
1285 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1286 struct lmk04832 *lmk = clkout->lmk;
1290 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1295 return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp);
1298 static const struct clk_ops lmk04832_clkout_ops = {
1299 .is_enabled = lmk04832_clkout_is_enabled,
1300 .prepare = lmk04832_clkout_prepare,
1301 .unprepare = lmk04832_clkout_unprepare,
1302 .set_parent = lmk04832_clkout_set_parent,
1303 .get_parent = lmk04832_clkout_get_parent,
1306 static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
1308 char name[] = "lmk-clkoutXX";
1309 char dclk_name[] = "lmk-dclkXX_YY";
1310 const char *parent_names[2];
1311 struct clk_init_data init;
1312 int dclk_num = num / 2;
1316 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
1317 init.name = dclk_name;
1318 parent_names[0] = clk_hw_get_name(&lmk->vco);
1319 init.ops = &lmk04832_dclk_ops;
1320 init.flags = CLK_SET_RATE_PARENT;
1321 init.num_parents = 1;
1323 lmk->dclk[dclk_num].id = num;
1324 lmk->dclk[dclk_num].lmk = lmk;
1325 lmk->dclk[dclk_num].hw.init = &init;
1327 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw);
1331 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num);
1334 if (of_property_read_string_index(lmk->dev->of_node,
1335 "clock-output-names",
1337 sprintf(name, "lmk-clkout%02d", num);
1341 parent_names[0] = dclk_name;
1342 parent_names[1] = clk_hw_get_name(&lmk->sclk);
1343 init.parent_names = parent_names;
1344 init.ops = &lmk04832_clkout_ops;
1345 init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
1346 init.num_parents = ARRAY_SIZE(parent_names);
1348 lmk->clkout[num].id = num;
1349 lmk->clkout[num].lmk = lmk;
1350 lmk->clkout[num].hw.init = &init;
1351 lmk->clk_data->hws[num] = &lmk->clkout[num].hw;
1353 /* Set initial parent */
1354 regmap_update_bits(lmk->regmap,
1355 LMK04832_REG_CLKOUT_SRC_MUX(num),
1356 LMK04832_BIT_CLKOUT_SRC_MUX,
1357 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1358 lmk->clkout[num].sysref));
1360 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw);
1363 static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
1368 dev_info(lmk->dev, "setting up 4-wire mode\n");
1369 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
1370 LMK04832_BIT_SPI_3WIRE_DIS);
1375 case RDBK_CLKIN_SEL0:
1376 reg = LMK04832_REG_CLKIN_SEL0;
1378 case RDBK_CLKIN_SEL1:
1379 reg = LMK04832_REG_CLKIN_SEL1;
1382 reg = LMK04832_REG_CLKIN_RST;
1388 return regmap_write(lmk->regmap, reg,
1389 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
1390 LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
1391 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
1392 LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
1395 static int lmk04832_probe(struct spi_device *spi)
1397 const struct lmk04832_device_info *info;
1398 int rdbk_pin = RDBK_CLKIN_SEL1;
1399 struct device_node *child;
1400 struct lmk04832 *lmk;
1405 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
1407 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL);
1411 lmk->dev = &spi->dev;
1413 lmk->oscin = devm_clk_get(lmk->dev, "oscin");
1414 if (IS_ERR(lmk->oscin)) {
1415 dev_err(lmk->dev, "failed to get oscin clock\n");
1416 return PTR_ERR(lmk->oscin);
1419 ret = clk_prepare_enable(lmk->oscin);
1423 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1426 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
1427 sizeof(struct lmk_dclk), GFP_KERNEL);
1428 if (IS_ERR(lmk->dclk)) {
1429 ret = PTR_ERR(lmk->dclk);
1430 goto err_disable_oscin;
1433 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
1434 sizeof(*lmk->clkout), GFP_KERNEL);
1435 if (IS_ERR(lmk->clkout)) {
1436 ret = PTR_ERR(lmk->clkout);
1437 goto err_disable_oscin;
1440 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
1441 info->num_channels),
1443 if (IS_ERR(lmk->clk_data)) {
1444 ret = PTR_ERR(lmk->clk_data);
1445 goto err_disable_oscin;
1448 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
1450 lmk->sysref_ddly = 8;
1451 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
1453 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
1454 device_property_read_u32(lmk->dev, "ti,sysref-mux",
1457 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
1458 device_property_read_u32(lmk->dev, "ti,sync-mode",
1461 lmk->sysref_pulse_cnt = 4;
1462 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
1463 &lmk->sysref_pulse_cnt);
1465 for_each_child_of_node(lmk->dev->of_node, child) {
1468 ret = of_property_read_u32(child, "reg", ®);
1470 dev_err(lmk->dev, "missing reg property in child: %s\n",
1473 goto err_disable_oscin;
1476 of_property_read_u32(child, "ti,clkout-fmt",
1477 &lmk->clkout[reg].format);
1479 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0
1480 && reg != 8 && reg != 10)
1481 dev_err(lmk->dev, "invalid format for clkout%02d\n",
1484 lmk->clkout[reg].sysref =
1485 of_property_read_bool(child, "ti,clkout-sysref");
1488 lmk->regmap = devm_regmap_init_spi(spi, ®map_config);
1489 if (IS_ERR(lmk->regmap)) {
1490 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n",
1492 __func__, PTR_ERR(lmk->regmap));
1493 ret = PTR_ERR(lmk->regmap);
1494 goto err_disable_oscin;
1497 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
1499 if (!(spi->mode & SPI_3WIRE)) {
1500 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk",
1502 ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
1504 goto err_disable_oscin;
1507 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
1508 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) {
1509 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
1510 tmp[0] << 8 | tmp[1], tmp[2]);
1512 goto err_disable_oscin;
1515 ret = lmk04832_register_vco(lmk);
1517 dev_err(lmk->dev, "failed to init device clock path\n");
1518 goto err_disable_oscin;
1521 if (lmk->vco_rate) {
1522 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate);
1523 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
1525 dev_err(lmk->dev, "failed to set VCO rate\n");
1526 goto err_disable_vco;
1530 ret = lmk04832_register_sclk(lmk);
1532 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
1533 goto err_disable_vco;
1536 for (i = 0; i < info->num_channels; i++) {
1537 ret = lmk04832_register_clkout(lmk, i);
1539 dev_err(lmk->dev, "failed to register clk %d\n", i);
1540 goto err_disable_vco;
1544 lmk->clk_data->num = info->num_channels;
1545 ret = of_clk_add_hw_provider(lmk->dev->of_node, of_clk_hw_onecell_get,
1548 dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
1549 goto err_disable_vco;
1552 spi_set_drvdata(spi, lmk);
1557 clk_disable_unprepare(lmk->vco.clk);
1560 clk_disable_unprepare(lmk->oscin);
1565 static int lmk04832_remove(struct spi_device *spi)
1567 struct lmk04832 *lmk = spi_get_drvdata(spi);
1569 clk_disable_unprepare(lmk->oscin);
1570 of_clk_del_provider(spi->dev.of_node);
1574 static const struct spi_device_id lmk04832_id[] = {
1575 { "lmk04832", LMK04832 },
1578 MODULE_DEVICE_TABLE(spi, lmk04832_id);
1580 static const struct of_device_id lmk04832_of_id[] = {
1581 { .compatible = "ti,lmk04832" },
1584 MODULE_DEVICE_TABLE(of, lmk04832_of_id);
1586 static struct spi_driver lmk04832_driver = {
1589 .of_match_table = lmk04832_of_id,
1591 .probe = lmk04832_probe,
1592 .remove = lmk04832_remove,
1593 .id_table = lmk04832_id,
1595 module_spi_driver(lmk04832_driver);
1597 MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>");
1598 MODULE_DESCRIPTION("Texas Instruments LMK04832");
1599 MODULE_LICENSE("GPL v2");