2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Adjustable divider clock implementation
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
22 * DOC: basic adjustable divider clock that cannot gate
24 * Traits of this clock:
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
28 * parent - fixed parent. No clk_set_parent support
31 #define div_mask(width) ((1 << (width)) - 1)
33 static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
36 unsigned int maxdiv = 0, mask = div_mask(width);
37 const struct clk_div_table *clkt;
39 for (clkt = table; clkt->div; clkt++)
40 if (clkt->div > maxdiv && clkt->val <= mask)
45 static unsigned int _get_table_mindiv(const struct clk_div_table *table)
47 unsigned int mindiv = UINT_MAX;
48 const struct clk_div_table *clkt;
50 for (clkt = table; clkt->div; clkt++)
51 if (clkt->div < mindiv)
56 static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
59 if (flags & CLK_DIVIDER_ONE_BASED)
60 return div_mask(width);
61 if (flags & CLK_DIVIDER_POWER_OF_TWO)
62 return 1 << div_mask(width);
64 return _get_table_maxdiv(table, width);
65 return div_mask(width) + 1;
68 static unsigned int _get_table_div(const struct clk_div_table *table,
71 const struct clk_div_table *clkt;
73 for (clkt = table; clkt->div; clkt++)
79 static unsigned int _get_div(const struct clk_div_table *table,
80 unsigned int val, unsigned long flags, u8 width)
82 if (flags & CLK_DIVIDER_ONE_BASED)
84 if (flags & CLK_DIVIDER_POWER_OF_TWO)
86 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
87 return val ? val : div_mask(width) + 1;
89 return _get_table_div(table, val);
93 static unsigned int _get_table_val(const struct clk_div_table *table,
96 const struct clk_div_table *clkt;
98 for (clkt = table; clkt->div; clkt++)
104 static unsigned int _get_val(const struct clk_div_table *table,
105 unsigned int div, unsigned long flags, u8 width)
107 if (flags & CLK_DIVIDER_ONE_BASED)
109 if (flags & CLK_DIVIDER_POWER_OF_TWO)
111 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
112 return (div == div_mask(width) + 1) ? 0 : div;
114 return _get_table_val(table, div);
118 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
120 const struct clk_div_table *table,
123 struct clk_divider *divider = to_clk_divider(hw);
126 div = _get_div(table, val, flags, divider->width);
128 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
129 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
130 clk_hw_get_name(hw));
134 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
136 EXPORT_SYMBOL_GPL(divider_recalc_rate);
138 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
139 unsigned long parent_rate)
141 struct clk_divider *divider = to_clk_divider(hw);
144 val = clk_readl(divider->reg) >> divider->shift;
145 val &= div_mask(divider->width);
147 return divider_recalc_rate(hw, parent_rate, val, divider->table,
151 static bool _is_valid_table_div(const struct clk_div_table *table,
154 const struct clk_div_table *clkt;
156 for (clkt = table; clkt->div; clkt++)
157 if (clkt->div == div)
162 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
165 if (flags & CLK_DIVIDER_POWER_OF_TWO)
166 return is_power_of_2(div);
168 return _is_valid_table_div(table, div);
172 static int _round_up_table(const struct clk_div_table *table, int div)
174 const struct clk_div_table *clkt;
177 for (clkt = table; clkt->div; clkt++) {
178 if (clkt->div == div)
180 else if (clkt->div < div)
183 if ((clkt->div - div) < (up - div))
190 static int _round_down_table(const struct clk_div_table *table, int div)
192 const struct clk_div_table *clkt;
193 int down = _get_table_mindiv(table);
195 for (clkt = table; clkt->div; clkt++) {
196 if (clkt->div == div)
198 else if (clkt->div > div)
201 if ((div - clkt->div) < (div - down))
208 static int _div_round_up(const struct clk_div_table *table,
209 unsigned long parent_rate, unsigned long rate,
212 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
214 if (flags & CLK_DIVIDER_POWER_OF_TWO)
215 div = __roundup_pow_of_two(div);
217 div = _round_up_table(table, div);
222 static int _div_round_closest(const struct clk_div_table *table,
223 unsigned long parent_rate, unsigned long rate,
227 unsigned long up_rate, down_rate;
229 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
230 down = parent_rate / rate;
232 if (flags & CLK_DIVIDER_POWER_OF_TWO) {
233 up = __roundup_pow_of_two(up);
234 down = __rounddown_pow_of_two(down);
236 up = _round_up_table(table, up);
237 down = _round_down_table(table, down);
240 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
241 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
243 return (rate - up_rate) <= (down_rate - rate) ? up : down;
246 static int _div_round(const struct clk_div_table *table,
247 unsigned long parent_rate, unsigned long rate,
250 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
251 return _div_round_closest(table, parent_rate, rate, flags);
253 return _div_round_up(table, parent_rate, rate, flags);
256 static bool _is_best_div(unsigned long rate, unsigned long now,
257 unsigned long best, unsigned long flags)
259 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
260 return abs(rate - now) < abs(rate - best);
262 return now <= rate && now > best;
265 static int _next_div(const struct clk_div_table *table, int div,
270 if (flags & CLK_DIVIDER_POWER_OF_TWO)
271 return __roundup_pow_of_two(div);
273 return _round_up_table(table, div);
278 static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
279 unsigned long *best_parent_rate,
280 const struct clk_div_table *table, u8 width,
284 unsigned long parent_rate, best = 0, now, maxdiv;
285 unsigned long parent_rate_saved = *best_parent_rate;
290 maxdiv = _get_maxdiv(table, width, flags);
292 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
293 parent_rate = *best_parent_rate;
294 bestdiv = _div_round(table, parent_rate, rate, flags);
295 bestdiv = bestdiv == 0 ? 1 : bestdiv;
296 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
301 * The maximum divider we can use without overflowing
302 * unsigned long in rate * i below
304 maxdiv = min(ULONG_MAX / rate, maxdiv);
306 for (i = 1; i <= maxdiv; i = _next_div(table, i, flags)) {
307 if (!_is_valid_div(table, i, flags))
309 if (rate * i == parent_rate_saved) {
311 * It's the most ideal case if the requested rate can be
312 * divided from parent clock without needing to change
313 * parent rate, so return the divider immediately.
315 *best_parent_rate = parent_rate_saved;
318 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
320 now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
321 if (_is_best_div(rate, now, best, flags)) {
324 *best_parent_rate = parent_rate;
329 bestdiv = _get_maxdiv(table, width, flags);
330 *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
336 long divider_round_rate(struct clk_hw *hw, unsigned long rate,
337 unsigned long *prate, const struct clk_div_table *table,
338 u8 width, unsigned long flags)
342 div = clk_divider_bestdiv(hw, rate, prate, table, width, flags);
344 return DIV_ROUND_UP_ULL((u64)*prate, div);
346 EXPORT_SYMBOL_GPL(divider_round_rate);
348 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
349 unsigned long *prate)
351 struct clk_divider *divider = to_clk_divider(hw);
354 /* if read only, just return current value */
355 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
356 bestdiv = readl(divider->reg) >> divider->shift;
357 bestdiv &= div_mask(divider->width);
358 bestdiv = _get_div(divider->table, bestdiv, divider->flags,
360 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
363 return divider_round_rate(hw, rate, prate, divider->table,
364 divider->width, divider->flags);
367 int divider_get_val(unsigned long rate, unsigned long parent_rate,
368 const struct clk_div_table *table, u8 width,
371 unsigned int div, value;
373 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
375 if (!_is_valid_div(table, div, flags))
378 value = _get_val(table, div, flags, width);
380 return min_t(unsigned int, value, div_mask(width));
382 EXPORT_SYMBOL_GPL(divider_get_val);
384 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
385 unsigned long parent_rate)
387 struct clk_divider *divider = to_clk_divider(hw);
389 unsigned long flags = 0;
392 value = divider_get_val(rate, parent_rate, divider->table,
393 divider->width, divider->flags);
396 spin_lock_irqsave(divider->lock, flags);
398 __acquire(divider->lock);
400 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
401 val = div_mask(divider->width) << (divider->shift + 16);
403 val = clk_readl(divider->reg);
404 val &= ~(div_mask(divider->width) << divider->shift);
406 val |= value << divider->shift;
407 clk_writel(val, divider->reg);
410 spin_unlock_irqrestore(divider->lock, flags);
412 __release(divider->lock);
417 const struct clk_ops clk_divider_ops = {
418 .recalc_rate = clk_divider_recalc_rate,
419 .round_rate = clk_divider_round_rate,
420 .set_rate = clk_divider_set_rate,
422 EXPORT_SYMBOL_GPL(clk_divider_ops);
424 const struct clk_ops clk_divider_ro_ops = {
425 .recalc_rate = clk_divider_recalc_rate,
426 .round_rate = clk_divider_round_rate,
428 EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
430 static struct clk *_register_divider(struct device *dev, const char *name,
431 const char *parent_name, unsigned long flags,
432 void __iomem *reg, u8 shift, u8 width,
433 u8 clk_divider_flags, const struct clk_div_table *table,
436 struct clk_divider *div;
438 struct clk_init_data init;
440 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
441 if (width + shift > 16) {
442 pr_warn("divider value exceeds LOWORD field\n");
443 return ERR_PTR(-EINVAL);
447 /* allocate the divider */
448 div = kzalloc(sizeof(*div), GFP_KERNEL);
450 return ERR_PTR(-ENOMEM);
453 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
454 init.ops = &clk_divider_ro_ops;
456 init.ops = &clk_divider_ops;
457 init.flags = flags | CLK_IS_BASIC;
458 init.parent_names = (parent_name ? &parent_name: NULL);
459 init.num_parents = (parent_name ? 1 : 0);
461 /* struct clk_divider assignments */
465 div->flags = clk_divider_flags;
467 div->hw.init = &init;
470 /* register the clock */
471 clk = clk_register(dev, &div->hw);
480 * clk_register_divider - register a divider clock with the clock framework
481 * @dev: device registering this clock
482 * @name: name of this clock
483 * @parent_name: name of clock's parent
484 * @flags: framework-specific flags
485 * @reg: register address to adjust divider
486 * @shift: number of bits to shift the bitfield
487 * @width: width of the bitfield
488 * @clk_divider_flags: divider-specific flags for this clock
489 * @lock: shared register lock for this clock
491 struct clk *clk_register_divider(struct device *dev, const char *name,
492 const char *parent_name, unsigned long flags,
493 void __iomem *reg, u8 shift, u8 width,
494 u8 clk_divider_flags, spinlock_t *lock)
496 return _register_divider(dev, name, parent_name, flags, reg, shift,
497 width, clk_divider_flags, NULL, lock);
499 EXPORT_SYMBOL_GPL(clk_register_divider);
502 * clk_register_divider_table - register a table based divider clock with
503 * the clock framework
504 * @dev: device registering this clock
505 * @name: name of this clock
506 * @parent_name: name of clock's parent
507 * @flags: framework-specific flags
508 * @reg: register address to adjust divider
509 * @shift: number of bits to shift the bitfield
510 * @width: width of the bitfield
511 * @clk_divider_flags: divider-specific flags for this clock
512 * @table: array of divider/value pairs ending with a div set to 0
513 * @lock: shared register lock for this clock
515 struct clk *clk_register_divider_table(struct device *dev, const char *name,
516 const char *parent_name, unsigned long flags,
517 void __iomem *reg, u8 shift, u8 width,
518 u8 clk_divider_flags, const struct clk_div_table *table,
521 return _register_divider(dev, name, parent_name, flags, reg, shift,
522 width, clk_divider_flags, table, lock);
524 EXPORT_SYMBOL_GPL(clk_register_divider_table);
526 void clk_unregister_divider(struct clk *clk)
528 struct clk_divider *div;
531 hw = __clk_get_hw(clk);
535 div = to_clk_divider(hw);
540 EXPORT_SYMBOL_GPL(clk_unregister_divider);