1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010,2015 Broadcom
4 * Copyright (C) 2012 Stephen Warren
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
11 * oscillator running at 19.2Mhz. After the oscillator there are 5
12 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
13 * and "HDMI displays". Those 5 PLLs each can divide their output to
14 * produce up to 4 channels. Finally, there is the level of clocks to
15 * be consumed by other hardware components (like "H264" or "HDMI
16 * state machine"), which divide off of some subset of the PLL
19 * All of the clocks in the tree are exposed in the DT, because the DT
20 * may want to make assignments of the final layer of clocks to the
21 * PLL channels, and some components of the hardware will actually
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
27 #include <linux/clk-provider.h>
28 #include <linux/clkdev.h>
29 #include <linux/clk.h>
30 #include <linux/debugfs.h>
31 #include <linux/delay.h>
33 #include <linux/module.h>
34 #include <linux/of_device.h>
35 #include <linux/platform_device.h>
36 #include <linux/slab.h>
37 #include <dt-bindings/clock/bcm2835.h>
39 #define CM_PASSWORD 0x5a000000
41 #define CM_GNRICCTL 0x000
42 #define CM_GNRICDIV 0x004
43 # define CM_DIV_FRAC_BITS 12
44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
46 #define CM_VPUCTL 0x008
47 #define CM_VPUDIV 0x00c
48 #define CM_SYSCTL 0x010
49 #define CM_SYSDIV 0x014
50 #define CM_PERIACTL 0x018
51 #define CM_PERIADIV 0x01c
52 #define CM_PERIICTL 0x020
53 #define CM_PERIIDIV 0x024
54 #define CM_H264CTL 0x028
55 #define CM_H264DIV 0x02c
56 #define CM_ISPCTL 0x030
57 #define CM_ISPDIV 0x034
58 #define CM_V3DCTL 0x038
59 #define CM_V3DDIV 0x03c
60 #define CM_CAM0CTL 0x040
61 #define CM_CAM0DIV 0x044
62 #define CM_CAM1CTL 0x048
63 #define CM_CAM1DIV 0x04c
64 #define CM_CCP2CTL 0x050
65 #define CM_CCP2DIV 0x054
66 #define CM_DSI0ECTL 0x058
67 #define CM_DSI0EDIV 0x05c
68 #define CM_DSI0PCTL 0x060
69 #define CM_DSI0PDIV 0x064
70 #define CM_DPICTL 0x068
71 #define CM_DPIDIV 0x06c
72 #define CM_GP0CTL 0x070
73 #define CM_GP0DIV 0x074
74 #define CM_GP1CTL 0x078
75 #define CM_GP1DIV 0x07c
76 #define CM_GP2CTL 0x080
77 #define CM_GP2DIV 0x084
78 #define CM_HSMCTL 0x088
79 #define CM_HSMDIV 0x08c
80 #define CM_OTPCTL 0x090
81 #define CM_OTPDIV 0x094
82 #define CM_PCMCTL 0x098
83 #define CM_PCMDIV 0x09c
84 #define CM_PWMCTL 0x0a0
85 #define CM_PWMDIV 0x0a4
86 #define CM_SLIMCTL 0x0a8
87 #define CM_SLIMDIV 0x0ac
88 #define CM_SMICTL 0x0b0
89 #define CM_SMIDIV 0x0b4
90 /* no definition for 0x0b8 and 0x0bc */
91 #define CM_TCNTCTL 0x0c0
92 # define CM_TCNT_SRC1_SHIFT 12
93 #define CM_TCNTCNT 0x0c4
94 #define CM_TECCTL 0x0c8
95 #define CM_TECDIV 0x0cc
96 #define CM_TD0CTL 0x0d0
97 #define CM_TD0DIV 0x0d4
98 #define CM_TD1CTL 0x0d8
99 #define CM_TD1DIV 0x0dc
100 #define CM_TSENSCTL 0x0e0
101 #define CM_TSENSDIV 0x0e4
102 #define CM_TIMERCTL 0x0e8
103 #define CM_TIMERDIV 0x0ec
104 #define CM_UARTCTL 0x0f0
105 #define CM_UARTDIV 0x0f4
106 #define CM_VECCTL 0x0f8
107 #define CM_VECDIV 0x0fc
108 #define CM_PULSECTL 0x190
109 #define CM_PULSEDIV 0x194
110 #define CM_SDCCTL 0x1a8
111 #define CM_SDCDIV 0x1ac
112 #define CM_ARMCTL 0x1b0
113 #define CM_AVEOCTL 0x1b8
114 #define CM_AVEODIV 0x1bc
115 #define CM_EMMCCTL 0x1c0
116 #define CM_EMMCDIV 0x1c4
117 #define CM_EMMC2CTL 0x1d0
118 #define CM_EMMC2DIV 0x1d4
120 /* General bits for the CM_*CTL regs */
121 # define CM_ENABLE BIT(4)
122 # define CM_KILL BIT(5)
123 # define CM_GATE_BIT 6
124 # define CM_GATE BIT(CM_GATE_BIT)
125 # define CM_BUSY BIT(7)
126 # define CM_BUSYD BIT(8)
127 # define CM_FRAC BIT(9)
128 # define CM_SRC_SHIFT 0
129 # define CM_SRC_BITS 4
130 # define CM_SRC_MASK 0xf
131 # define CM_SRC_GND 0
132 # define CM_SRC_OSC 1
133 # define CM_SRC_TESTDEBUG0 2
134 # define CM_SRC_TESTDEBUG1 3
135 # define CM_SRC_PLLA_CORE 4
136 # define CM_SRC_PLLA_PER 4
137 # define CM_SRC_PLLC_CORE0 5
138 # define CM_SRC_PLLC_PER 5
139 # define CM_SRC_PLLC_CORE1 8
140 # define CM_SRC_PLLD_CORE 6
141 # define CM_SRC_PLLD_PER 6
142 # define CM_SRC_PLLH_AUX 7
143 # define CM_SRC_PLLC_CORE1 8
144 # define CM_SRC_PLLC_CORE2 9
146 #define CM_OSCCOUNT 0x100
148 #define CM_PLLA 0x104
149 # define CM_PLL_ANARST BIT(8)
150 # define CM_PLLA_HOLDPER BIT(7)
151 # define CM_PLLA_LOADPER BIT(6)
152 # define CM_PLLA_HOLDCORE BIT(5)
153 # define CM_PLLA_LOADCORE BIT(4)
154 # define CM_PLLA_HOLDCCP2 BIT(3)
155 # define CM_PLLA_LOADCCP2 BIT(2)
156 # define CM_PLLA_HOLDDSI0 BIT(1)
157 # define CM_PLLA_LOADDSI0 BIT(0)
159 #define CM_PLLC 0x108
160 # define CM_PLLC_HOLDPER BIT(7)
161 # define CM_PLLC_LOADPER BIT(6)
162 # define CM_PLLC_HOLDCORE2 BIT(5)
163 # define CM_PLLC_LOADCORE2 BIT(4)
164 # define CM_PLLC_HOLDCORE1 BIT(3)
165 # define CM_PLLC_LOADCORE1 BIT(2)
166 # define CM_PLLC_HOLDCORE0 BIT(1)
167 # define CM_PLLC_LOADCORE0 BIT(0)
169 #define CM_PLLD 0x10c
170 # define CM_PLLD_HOLDPER BIT(7)
171 # define CM_PLLD_LOADPER BIT(6)
172 # define CM_PLLD_HOLDCORE BIT(5)
173 # define CM_PLLD_LOADCORE BIT(4)
174 # define CM_PLLD_HOLDDSI1 BIT(3)
175 # define CM_PLLD_LOADDSI1 BIT(2)
176 # define CM_PLLD_HOLDDSI0 BIT(1)
177 # define CM_PLLD_LOADDSI0 BIT(0)
179 #define CM_PLLH 0x110
180 # define CM_PLLH_LOADRCAL BIT(2)
181 # define CM_PLLH_LOADAUX BIT(1)
182 # define CM_PLLH_LOADPIX BIT(0)
184 #define CM_LOCK 0x114
185 # define CM_LOCK_FLOCKH BIT(12)
186 # define CM_LOCK_FLOCKD BIT(11)
187 # define CM_LOCK_FLOCKC BIT(10)
188 # define CM_LOCK_FLOCKB BIT(9)
189 # define CM_LOCK_FLOCKA BIT(8)
191 #define CM_EVENT 0x118
192 #define CM_DSI1ECTL 0x158
193 #define CM_DSI1EDIV 0x15c
194 #define CM_DSI1PCTL 0x160
195 #define CM_DSI1PDIV 0x164
196 #define CM_DFTCTL 0x168
197 #define CM_DFTDIV 0x16c
199 #define CM_PLLB 0x170
200 # define CM_PLLB_HOLDARM BIT(1)
201 # define CM_PLLB_LOADARM BIT(0)
203 #define A2W_PLLA_CTRL 0x1100
204 #define A2W_PLLC_CTRL 0x1120
205 #define A2W_PLLD_CTRL 0x1140
206 #define A2W_PLLH_CTRL 0x1160
207 #define A2W_PLLB_CTRL 0x11e0
208 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
209 # define A2W_PLL_CTRL_PWRDN BIT(16)
210 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
211 # define A2W_PLL_CTRL_PDIV_SHIFT 12
212 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
213 # define A2W_PLL_CTRL_NDIV_SHIFT 0
215 #define A2W_PLLA_ANA0 0x1010
216 #define A2W_PLLC_ANA0 0x1030
217 #define A2W_PLLD_ANA0 0x1050
218 #define A2W_PLLH_ANA0 0x1070
219 #define A2W_PLLB_ANA0 0x10f0
221 #define A2W_PLL_KA_SHIFT 7
222 #define A2W_PLL_KA_MASK GENMASK(9, 7)
223 #define A2W_PLL_KI_SHIFT 19
224 #define A2W_PLL_KI_MASK GENMASK(21, 19)
225 #define A2W_PLL_KP_SHIFT 15
226 #define A2W_PLL_KP_MASK GENMASK(18, 15)
228 #define A2W_PLLH_KA_SHIFT 19
229 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
230 #define A2W_PLLH_KI_LOW_SHIFT 22
231 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
232 #define A2W_PLLH_KI_HIGH_SHIFT 0
233 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
234 #define A2W_PLLH_KP_SHIFT 1
235 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
237 #define A2W_XOSC_CTRL 0x1190
238 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
239 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
240 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
241 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
242 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
243 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
244 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
245 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
247 #define A2W_PLLA_FRAC 0x1200
248 #define A2W_PLLC_FRAC 0x1220
249 #define A2W_PLLD_FRAC 0x1240
250 #define A2W_PLLH_FRAC 0x1260
251 #define A2W_PLLB_FRAC 0x12e0
252 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
253 # define A2W_PLL_FRAC_BITS 20
255 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
256 #define A2W_PLL_DIV_BITS 8
257 #define A2W_PLL_DIV_SHIFT 0
259 #define A2W_PLLA_DSI0 0x1300
260 #define A2W_PLLA_CORE 0x1400
261 #define A2W_PLLA_PER 0x1500
262 #define A2W_PLLA_CCP2 0x1600
264 #define A2W_PLLC_CORE2 0x1320
265 #define A2W_PLLC_CORE1 0x1420
266 #define A2W_PLLC_PER 0x1520
267 #define A2W_PLLC_CORE0 0x1620
269 #define A2W_PLLD_DSI0 0x1340
270 #define A2W_PLLD_CORE 0x1440
271 #define A2W_PLLD_PER 0x1540
272 #define A2W_PLLD_DSI1 0x1640
274 #define A2W_PLLH_AUX 0x1360
275 #define A2W_PLLH_RCAL 0x1460
276 #define A2W_PLLH_PIX 0x1560
277 #define A2W_PLLH_STS 0x1660
279 #define A2W_PLLH_CTRLR 0x1960
280 #define A2W_PLLH_FRACR 0x1a60
281 #define A2W_PLLH_AUXR 0x1b60
282 #define A2W_PLLH_RCALR 0x1c60
283 #define A2W_PLLH_PIXR 0x1d60
284 #define A2W_PLLH_STSR 0x1e60
286 #define A2W_PLLB_ARM 0x13e0
287 #define A2W_PLLB_SP0 0x14e0
288 #define A2W_PLLB_SP1 0x15e0
289 #define A2W_PLLB_SP2 0x16e0
291 #define LOCK_TIMEOUT_NS 100000000
292 #define BCM2835_MAX_FB_RATE 1750000000u
294 #define SOC_BCM2835 BIT(0)
295 #define SOC_BCM2711 BIT(1)
296 #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
299 * Names of clocks used within the driver that need to be replaced
300 * with an external parent's name. This array is in the order that
301 * the clocks node in the DT references external clocks.
303 static const char *const cprman_parent_names[] = {
313 struct bcm2835_cprman {
316 spinlock_t regs_lock; /* spinlock for all clocks */
320 * Real names of cprman clock parents looked up through
321 * of_clk_get_parent_name(), which will be used in the
322 * parent_names[] arrays for clock registration.
324 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
327 struct clk_hw_onecell_data onecell;
330 struct cprman_plat_data {
334 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
336 writel(CM_PASSWORD | val, cprman->regs + reg);
339 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
341 return readl(cprman->regs + reg);
344 /* Does a cycle of measuring a clock through the TCNT clock, which may
345 * source from many other clocks in the system.
347 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
350 u32 osccount = 19200; /* 1ms */
354 spin_lock(&cprman->regs_lock);
356 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
358 cprman_write(cprman, CM_TCNTCTL,
359 (tcnt_mux & CM_SRC_MASK) |
360 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
362 cprman_write(cprman, CM_OSCCOUNT, osccount);
364 /* do a kind delay at the start */
367 /* Finish off whatever is left of OSCCOUNT */
368 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
369 while (cprman_read(cprman, CM_OSCCOUNT)) {
370 if (ktime_after(ktime_get(), timeout)) {
371 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
378 /* Wait for BUSY to clear. */
379 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
380 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
381 if (ktime_after(ktime_get(), timeout)) {
382 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
389 count = cprman_read(cprman, CM_TCNTCNT);
391 cprman_write(cprman, CM_TCNTCTL, 0);
394 spin_unlock(&cprman->regs_lock);
399 static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
400 const struct debugfs_reg32 *regs,
401 size_t nregs, struct dentry *dentry)
403 struct debugfs_regset32 *regset;
405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
410 regset->nregs = nregs;
411 regset->base = cprman->regs + base;
413 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
416 struct bcm2835_pll_data {
422 u32 reference_enable_mask;
423 /* Bit in CM_LOCK to indicate when the PLL has locked. */
427 const struct bcm2835_pll_ana_bits *ana;
429 unsigned long min_rate;
430 unsigned long max_rate;
432 * Highest rate for the VCO before we have to use the
435 unsigned long max_fb_rate;
438 struct bcm2835_pll_ana_bits {
448 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
451 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
452 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
453 .mask3 = A2W_PLL_KA_MASK,
454 .set3 = (2 << A2W_PLL_KA_SHIFT),
455 .fb_prediv_mask = BIT(14),
458 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
459 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
460 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
461 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
462 .set1 = (6 << A2W_PLLH_KP_SHIFT),
465 .fb_prediv_mask = BIT(11),
468 struct bcm2835_pll_divider_data {
470 const char *source_pll;
481 struct bcm2835_clock_data {
484 const char *const *parents;
487 /* Bitmap encoding which parents accept rate change propagation. */
488 unsigned int set_rate_parent;
493 /* Number of integer bits in the divider */
495 /* Number of fractional bits in the divider */
507 struct bcm2835_gate_data {
516 struct bcm2835_cprman *cprman;
517 const struct bcm2835_pll_data *data;
520 static int bcm2835_pll_is_on(struct clk_hw *hw)
522 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
523 struct bcm2835_cprman *cprman = pll->cprman;
524 const struct bcm2835_pll_data *data = pll->data;
526 return cprman_read(cprman, data->a2w_ctrl_reg) &
527 A2W_PLL_CTRL_PRST_DISABLE;
530 static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,
531 const struct bcm2835_pll_data *data)
534 * On BCM2711 there isn't a pre-divisor available in the PLL feedback
535 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed
536 * for to for VCO RANGE bits.
538 if (cprman->soc & SOC_BCM2711)
541 return data->ana->fb_prediv_mask;
544 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
545 unsigned long parent_rate,
546 u32 *ndiv, u32 *fdiv)
550 div = (u64)rate << A2W_PLL_FRAC_BITS;
551 do_div(div, parent_rate);
553 *ndiv = div >> A2W_PLL_FRAC_BITS;
554 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
557 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
558 u32 ndiv, u32 fdiv, u32 pdiv)
565 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
567 return rate >> A2W_PLL_FRAC_BITS;
570 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
571 unsigned long *parent_rate)
573 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
574 const struct bcm2835_pll_data *data = pll->data;
577 rate = clamp(rate, data->min_rate, data->max_rate);
579 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
581 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
584 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
585 unsigned long parent_rate)
587 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
588 struct bcm2835_cprman *cprman = pll->cprman;
589 const struct bcm2835_pll_data *data = pll->data;
590 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
591 u32 ndiv, pdiv, fdiv;
594 if (parent_rate == 0)
597 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
598 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
599 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
600 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
601 bcm2835_pll_get_prediv_mask(cprman, data);
608 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
611 static void bcm2835_pll_off(struct clk_hw *hw)
613 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
614 struct bcm2835_cprman *cprman = pll->cprman;
615 const struct bcm2835_pll_data *data = pll->data;
617 spin_lock(&cprman->regs_lock);
618 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
619 cprman_write(cprman, data->a2w_ctrl_reg,
620 cprman_read(cprman, data->a2w_ctrl_reg) |
622 spin_unlock(&cprman->regs_lock);
625 static int bcm2835_pll_on(struct clk_hw *hw)
627 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
628 struct bcm2835_cprman *cprman = pll->cprman;
629 const struct bcm2835_pll_data *data = pll->data;
632 cprman_write(cprman, data->a2w_ctrl_reg,
633 cprman_read(cprman, data->a2w_ctrl_reg) &
634 ~A2W_PLL_CTRL_PWRDN);
636 /* Take the PLL out of reset. */
637 spin_lock(&cprman->regs_lock);
638 cprman_write(cprman, data->cm_ctrl_reg,
639 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
640 spin_unlock(&cprman->regs_lock);
642 /* Wait for the PLL to lock. */
643 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
644 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
645 if (ktime_after(ktime_get(), timeout)) {
646 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
647 clk_hw_get_name(hw));
654 cprman_write(cprman, data->a2w_ctrl_reg,
655 cprman_read(cprman, data->a2w_ctrl_reg) |
656 A2W_PLL_CTRL_PRST_DISABLE);
662 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
667 * ANA register setup is done as a series of writes to
668 * ANA3-ANA0, in that order. This lets us write all 4
669 * registers as a single cycle of the serdes interface (taking
670 * 100 xosc clocks), whereas if we were to update ana0, 1, and
671 * 3 individually through their partial-write registers, each
672 * would be their own serdes cycle.
674 for (i = 3; i >= 0; i--)
675 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
678 static int bcm2835_pll_set_rate(struct clk_hw *hw,
679 unsigned long rate, unsigned long parent_rate)
681 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
682 struct bcm2835_cprman *cprman = pll->cprman;
683 const struct bcm2835_pll_data *data = pll->data;
684 u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);
685 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
686 u32 ndiv, fdiv, a2w_ctl;
690 if (rate > data->max_fb_rate) {
691 use_fb_prediv = true;
694 use_fb_prediv = false;
697 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
699 for (i = 3; i >= 0; i--)
700 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
702 was_using_prediv = ana[1] & prediv_mask;
704 ana[0] &= ~data->ana->mask0;
705 ana[0] |= data->ana->set0;
706 ana[1] &= ~data->ana->mask1;
707 ana[1] |= data->ana->set1;
708 ana[3] &= ~data->ana->mask3;
709 ana[3] |= data->ana->set3;
711 if (was_using_prediv && !use_fb_prediv) {
712 ana[1] &= ~prediv_mask;
713 do_ana_setup_first = true;
714 } else if (!was_using_prediv && use_fb_prediv) {
715 ana[1] |= prediv_mask;
716 do_ana_setup_first = false;
718 do_ana_setup_first = true;
721 /* Unmask the reference clock from the oscillator. */
722 spin_lock(&cprman->regs_lock);
723 cprman_write(cprman, A2W_XOSC_CTRL,
724 cprman_read(cprman, A2W_XOSC_CTRL) |
725 data->reference_enable_mask);
726 spin_unlock(&cprman->regs_lock);
728 if (do_ana_setup_first)
729 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
731 /* Set the PLL multiplier from the oscillator. */
732 cprman_write(cprman, data->frac_reg, fdiv);
734 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
735 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
736 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
737 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
738 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
739 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
741 if (!do_ana_setup_first)
742 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
747 static void bcm2835_pll_debug_init(struct clk_hw *hw,
748 struct dentry *dentry)
750 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
751 struct bcm2835_cprman *cprman = pll->cprman;
752 const struct bcm2835_pll_data *data = pll->data;
753 struct debugfs_reg32 *regs;
755 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
759 regs[0].name = "cm_ctrl";
760 regs[0].offset = data->cm_ctrl_reg;
761 regs[1].name = "a2w_ctrl";
762 regs[1].offset = data->a2w_ctrl_reg;
763 regs[2].name = "frac";
764 regs[2].offset = data->frac_reg;
765 regs[3].name = "ana0";
766 regs[3].offset = data->ana_reg_base + 0 * 4;
767 regs[4].name = "ana1";
768 regs[4].offset = data->ana_reg_base + 1 * 4;
769 regs[5].name = "ana2";
770 regs[5].offset = data->ana_reg_base + 2 * 4;
771 regs[6].name = "ana3";
772 regs[6].offset = data->ana_reg_base + 3 * 4;
774 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
777 static const struct clk_ops bcm2835_pll_clk_ops = {
778 .is_prepared = bcm2835_pll_is_on,
779 .prepare = bcm2835_pll_on,
780 .unprepare = bcm2835_pll_off,
781 .recalc_rate = bcm2835_pll_get_rate,
782 .set_rate = bcm2835_pll_set_rate,
783 .round_rate = bcm2835_pll_round_rate,
784 .debug_init = bcm2835_pll_debug_init,
787 struct bcm2835_pll_divider {
788 struct clk_divider div;
789 struct bcm2835_cprman *cprman;
790 const struct bcm2835_pll_divider_data *data;
793 static struct bcm2835_pll_divider *
794 bcm2835_pll_divider_from_hw(struct clk_hw *hw)
796 return container_of(hw, struct bcm2835_pll_divider, div.hw);
799 static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
801 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
802 struct bcm2835_cprman *cprman = divider->cprman;
803 const struct bcm2835_pll_divider_data *data = divider->data;
805 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
808 static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,
809 struct clk_rate_request *req)
811 return clk_divider_ops.determine_rate(hw, req);
814 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
815 unsigned long parent_rate)
817 return clk_divider_ops.recalc_rate(hw, parent_rate);
820 static void bcm2835_pll_divider_off(struct clk_hw *hw)
822 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
823 struct bcm2835_cprman *cprman = divider->cprman;
824 const struct bcm2835_pll_divider_data *data = divider->data;
826 spin_lock(&cprman->regs_lock);
827 cprman_write(cprman, data->cm_reg,
828 (cprman_read(cprman, data->cm_reg) &
829 ~data->load_mask) | data->hold_mask);
830 cprman_write(cprman, data->a2w_reg,
831 cprman_read(cprman, data->a2w_reg) |
832 A2W_PLL_CHANNEL_DISABLE);
833 spin_unlock(&cprman->regs_lock);
836 static int bcm2835_pll_divider_on(struct clk_hw *hw)
838 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
839 struct bcm2835_cprman *cprman = divider->cprman;
840 const struct bcm2835_pll_divider_data *data = divider->data;
842 spin_lock(&cprman->regs_lock);
843 cprman_write(cprman, data->a2w_reg,
844 cprman_read(cprman, data->a2w_reg) &
845 ~A2W_PLL_CHANNEL_DISABLE);
847 cprman_write(cprman, data->cm_reg,
848 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
849 spin_unlock(&cprman->regs_lock);
854 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
856 unsigned long parent_rate)
858 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
859 struct bcm2835_cprman *cprman = divider->cprman;
860 const struct bcm2835_pll_divider_data *data = divider->data;
861 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
863 div = DIV_ROUND_UP_ULL(parent_rate, rate);
865 div = min(div, max_div);
869 cprman_write(cprman, data->a2w_reg, div);
870 cm = cprman_read(cprman, data->cm_reg);
871 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
872 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
877 static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
878 struct dentry *dentry)
880 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
881 struct bcm2835_cprman *cprman = divider->cprman;
882 const struct bcm2835_pll_divider_data *data = divider->data;
883 struct debugfs_reg32 *regs;
885 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
890 regs[0].offset = data->cm_reg;
891 regs[1].name = "a2w";
892 regs[1].offset = data->a2w_reg;
894 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
897 static const struct clk_ops bcm2835_pll_divider_clk_ops = {
898 .is_prepared = bcm2835_pll_divider_is_on,
899 .prepare = bcm2835_pll_divider_on,
900 .unprepare = bcm2835_pll_divider_off,
901 .recalc_rate = bcm2835_pll_divider_get_rate,
902 .set_rate = bcm2835_pll_divider_set_rate,
903 .determine_rate = bcm2835_pll_divider_determine_rate,
904 .debug_init = bcm2835_pll_divider_debug_init,
908 * The CM dividers do fixed-point division, so we can't use the
909 * generic integer divider code like the PLL dividers do (and we can't
910 * fake it by having some fixed shifts preceding it in the clock tree,
911 * because we'd run out of bits in a 32-bit unsigned long).
913 struct bcm2835_clock {
915 struct bcm2835_cprman *cprman;
916 const struct bcm2835_clock_data *data;
919 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
921 return container_of(hw, struct bcm2835_clock, hw);
924 static int bcm2835_clock_is_on(struct clk_hw *hw)
926 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
927 struct bcm2835_cprman *cprman = clock->cprman;
928 const struct bcm2835_clock_data *data = clock->data;
930 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
933 static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
935 unsigned long parent_rate)
937 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
938 const struct bcm2835_clock_data *data = clock->data;
939 u32 unused_frac_mask =
940 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
941 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
942 u32 div, mindiv, maxdiv;
946 div &= ~unused_frac_mask;
948 /* different clamping limits apply for a mash clock */
949 if (data->is_mash_clock) {
950 /* clamp to min divider of 2 */
951 mindiv = 2 << CM_DIV_FRAC_BITS;
952 /* clamp to the highest possible integer divider */
953 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
955 /* clamp to min divider of 1 */
956 mindiv = 1 << CM_DIV_FRAC_BITS;
957 /* clamp to the highest possible fractional divider */
958 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
959 CM_DIV_FRAC_BITS - data->frac_bits);
962 /* apply the clamping limits */
963 div = max_t(u32, div, mindiv);
964 div = min_t(u32, div, maxdiv);
969 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
970 unsigned long parent_rate,
973 const struct bcm2835_clock_data *data = clock->data;
976 if (data->int_bits == 0 && data->frac_bits == 0)
980 * The divisor is a 12.12 fixed point field, but only some of
981 * the bits are populated in any given clock.
983 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
984 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
989 temp = (u64)parent_rate << data->frac_bits;
996 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
997 unsigned long parent_rate)
999 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1000 struct bcm2835_cprman *cprman = clock->cprman;
1001 const struct bcm2835_clock_data *data = clock->data;
1004 if (data->int_bits == 0 && data->frac_bits == 0)
1007 div = cprman_read(cprman, data->div_reg);
1009 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1012 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1014 struct bcm2835_cprman *cprman = clock->cprman;
1015 const struct bcm2835_clock_data *data = clock->data;
1016 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1018 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1019 if (ktime_after(ktime_get(), timeout)) {
1020 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1021 clk_hw_get_name(&clock->hw));
1028 static void bcm2835_clock_off(struct clk_hw *hw)
1030 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1031 struct bcm2835_cprman *cprman = clock->cprman;
1032 const struct bcm2835_clock_data *data = clock->data;
1034 spin_lock(&cprman->regs_lock);
1035 cprman_write(cprman, data->ctl_reg,
1036 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1037 spin_unlock(&cprman->regs_lock);
1039 /* BUSY will remain high until the divider completes its cycle. */
1040 bcm2835_clock_wait_busy(clock);
1043 static int bcm2835_clock_on(struct clk_hw *hw)
1045 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1046 struct bcm2835_cprman *cprman = clock->cprman;
1047 const struct bcm2835_clock_data *data = clock->data;
1049 spin_lock(&cprman->regs_lock);
1050 cprman_write(cprman, data->ctl_reg,
1051 cprman_read(cprman, data->ctl_reg) |
1054 spin_unlock(&cprman->regs_lock);
1056 /* Debug code to measure the clock once it's turned on to see
1057 * if it's ticking at the rate we expect.
1059 if (data->tcnt_mux && false) {
1060 dev_info(cprman->dev,
1061 "clk %s: rate %ld, measure %ld\n",
1063 clk_hw_get_rate(hw),
1064 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1070 static int bcm2835_clock_set_rate(struct clk_hw *hw,
1071 unsigned long rate, unsigned long parent_rate)
1073 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1074 struct bcm2835_cprman *cprman = clock->cprman;
1075 const struct bcm2835_clock_data *data = clock->data;
1076 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
1079 spin_lock(&cprman->regs_lock);
1082 * Setting up frac support
1084 * In principle it is recommended to stop/start the clock first,
1085 * but as we set CLK_SET_RATE_GATE during registration of the
1086 * clock this requirement should be take care of by the
1089 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1090 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1091 cprman_write(cprman, data->ctl_reg, ctl);
1093 cprman_write(cprman, data->div_reg, div);
1095 spin_unlock(&cprman->regs_lock);
1101 bcm2835_clk_is_pllc(struct clk_hw *hw)
1106 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1109 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1113 unsigned long *prate,
1114 unsigned long *avgrate)
1116 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1117 struct bcm2835_cprman *cprman = clock->cprman;
1118 const struct bcm2835_clock_data *data = clock->data;
1119 unsigned long best_rate = 0;
1120 u32 curdiv, mindiv, maxdiv;
1121 struct clk_hw *parent;
1123 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1125 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1126 *prate = clk_hw_get_rate(parent);
1127 *div = bcm2835_clock_choose_div(hw, rate, *prate);
1129 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1131 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1132 unsigned long high, low;
1133 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1135 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1137 int_div += CM_DIV_FRAC_MASK + 1;
1138 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1142 * Return a value which is the maximum deviation
1143 * below the ideal rate, for use as a metric.
1145 return *avgrate - max(*avgrate - low, high - *avgrate);
1150 if (data->frac_bits)
1151 dev_warn(cprman->dev,
1152 "frac bits are not used when propagating rate change");
1154 /* clamp to min divider of 2 if we're dealing with a mash clock */
1155 mindiv = data->is_mash_clock ? 2 : 1;
1156 maxdiv = BIT(data->int_bits) - 1;
1158 /* TODO: Be smart, and only test a subset of the available divisors. */
1159 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1160 unsigned long tmp_rate;
1162 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1164 if (curdiv == mindiv ||
1165 (tmp_rate > best_rate && tmp_rate <= rate))
1166 best_rate = tmp_rate;
1168 if (best_rate == rate)
1172 *div = curdiv << CM_DIV_FRAC_BITS;
1173 *prate = curdiv * best_rate;
1174 *avgrate = best_rate;
1179 static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1180 struct clk_rate_request *req)
1182 struct clk_hw *parent, *best_parent = NULL;
1183 bool current_parent_is_pllc;
1184 unsigned long rate, best_rate = 0;
1185 unsigned long prate, best_prate = 0;
1186 unsigned long avgrate, best_avgrate = 0;
1190 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1193 * Select parent clock that results in the closest but lower rate
1195 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1196 parent = clk_hw_get_parent_by_index(hw, i);
1201 * Don't choose a PLLC-derived clock as our parent
1202 * unless it had been manually set that way. PLLC's
1203 * frequency gets adjusted by the firmware due to
1204 * over-temp or under-voltage conditions, without
1205 * prior notification to our clock consumer.
1207 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1210 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1213 if (abs(req->rate - rate) < abs(req->rate - best_rate)) {
1214 best_parent = parent;
1217 best_avgrate = avgrate;
1224 req->best_parent_hw = best_parent;
1225 req->best_parent_rate = best_prate;
1227 req->rate = best_avgrate;
1232 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1234 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1235 struct bcm2835_cprman *cprman = clock->cprman;
1236 const struct bcm2835_clock_data *data = clock->data;
1237 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1239 cprman_write(cprman, data->ctl_reg, src);
1243 static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1245 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1246 struct bcm2835_cprman *cprman = clock->cprman;
1247 const struct bcm2835_clock_data *data = clock->data;
1248 u32 src = cprman_read(cprman, data->ctl_reg);
1250 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1253 static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1264 static void bcm2835_clock_debug_init(struct clk_hw *hw,
1265 struct dentry *dentry)
1267 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1268 struct bcm2835_cprman *cprman = clock->cprman;
1269 const struct bcm2835_clock_data *data = clock->data;
1271 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1272 bcm2835_debugfs_clock_reg32,
1273 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1277 static const struct clk_ops bcm2835_clock_clk_ops = {
1278 .is_prepared = bcm2835_clock_is_on,
1279 .prepare = bcm2835_clock_on,
1280 .unprepare = bcm2835_clock_off,
1281 .recalc_rate = bcm2835_clock_get_rate,
1282 .set_rate = bcm2835_clock_set_rate,
1283 .determine_rate = bcm2835_clock_determine_rate,
1284 .set_parent = bcm2835_clock_set_parent,
1285 .get_parent = bcm2835_clock_get_parent,
1286 .debug_init = bcm2835_clock_debug_init,
1289 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1295 * The VPU clock can never be disabled (it doesn't have an ENABLE
1296 * bit), so it gets its own set of clock ops.
1298 static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1299 .is_prepared = bcm2835_vpu_clock_is_on,
1300 .recalc_rate = bcm2835_clock_get_rate,
1301 .set_rate = bcm2835_clock_set_rate,
1302 .determine_rate = bcm2835_clock_determine_rate,
1303 .set_parent = bcm2835_clock_set_parent,
1304 .get_parent = bcm2835_clock_get_parent,
1305 .debug_init = bcm2835_clock_debug_init,
1308 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1311 const struct bcm2835_pll_data *pll_data = data;
1312 struct bcm2835_pll *pll;
1313 struct clk_init_data init;
1316 memset(&init, 0, sizeof(init));
1318 /* All of the PLLs derive from the external oscillator. */
1319 init.parent_names = &cprman->real_parent_names[0];
1320 init.num_parents = 1;
1321 init.name = pll_data->name;
1322 init.ops = &bcm2835_pll_clk_ops;
1323 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1325 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1329 pll->cprman = cprman;
1330 pll->data = pll_data;
1331 pll->hw.init = &init;
1333 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1341 static struct clk_hw *
1342 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1345 const struct bcm2835_pll_divider_data *divider_data = data;
1346 struct bcm2835_pll_divider *divider;
1347 struct clk_init_data init;
1348 const char *divider_name;
1351 if (divider_data->fixed_divider != 1) {
1352 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1353 "%s_prediv", divider_data->name);
1357 divider_name = divider_data->name;
1360 memset(&init, 0, sizeof(init));
1362 init.parent_names = ÷r_data->source_pll;
1363 init.num_parents = 1;
1364 init.name = divider_name;
1365 init.ops = &bcm2835_pll_divider_clk_ops;
1366 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1368 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1372 divider->div.reg = cprman->regs + divider_data->a2w_reg;
1373 divider->div.shift = A2W_PLL_DIV_SHIFT;
1374 divider->div.width = A2W_PLL_DIV_BITS;
1375 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1376 divider->div.lock = &cprman->regs_lock;
1377 divider->div.hw.init = &init;
1378 divider->div.table = NULL;
1380 divider->cprman = cprman;
1381 divider->data = divider_data;
1383 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
1385 return ERR_PTR(ret);
1388 * PLLH's channels have a fixed divide by 10 afterwards, which
1389 * is what our consumers are actually using.
1391 if (divider_data->fixed_divider != 1) {
1392 return clk_hw_register_fixed_factor(cprman->dev,
1395 CLK_SET_RATE_PARENT,
1397 divider_data->fixed_divider);
1400 return ÷r->div.hw;
1403 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1406 const struct bcm2835_clock_data *clock_data = data;
1407 struct bcm2835_clock *clock;
1408 struct clk_init_data init;
1409 const char *parents[1 << CM_SRC_BITS];
1414 * Replace our strings referencing parent clocks with the
1415 * actual clock-output-name of the parent.
1417 for (i = 0; i < clock_data->num_mux_parents; i++) {
1418 parents[i] = clock_data->parents[i];
1420 ret = match_string(cprman_parent_names,
1421 ARRAY_SIZE(cprman_parent_names),
1424 parents[i] = cprman->real_parent_names[ret];
1427 memset(&init, 0, sizeof(init));
1428 init.parent_names = parents;
1429 init.num_parents = clock_data->num_mux_parents;
1430 init.name = clock_data->name;
1431 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1434 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1435 * rate changes on at least of the parents.
1437 if (clock_data->set_rate_parent)
1438 init.flags |= CLK_SET_RATE_PARENT;
1440 if (clock_data->is_vpu_clock) {
1441 init.ops = &bcm2835_vpu_clock_clk_ops;
1443 init.ops = &bcm2835_clock_clk_ops;
1444 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1446 /* If the clock wasn't actually enabled at boot, it's not
1449 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
1450 init.flags &= ~CLK_IS_CRITICAL;
1453 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1457 clock->cprman = cprman;
1458 clock->data = clock_data;
1459 clock->hw.init = &init;
1461 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1463 return ERR_PTR(ret);
1467 static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1470 const struct bcm2835_gate_data *gate_data = data;
1472 return clk_hw_register_gate(cprman->dev, gate_data->name,
1474 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1475 cprman->regs + gate_data->ctl_reg,
1476 CM_GATE_BIT, 0, &cprman->regs_lock);
1479 struct bcm2835_clk_desc {
1480 struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
1482 unsigned int supported;
1486 /* assignment helper macros for different clock types */
1487 #define _REGISTER(f, s, ...) { .clk_register = f, \
1489 .data = __VA_ARGS__ }
1490 #define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
1492 &(struct bcm2835_pll_data) \
1494 #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1496 &(struct bcm2835_pll_divider_data) \
1498 #define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
1500 &(struct bcm2835_clock_data) \
1502 #define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
1504 &(struct bcm2835_gate_data) \
1507 /* parent mux arrays plus helper macros */
1509 /* main oscillator parent mux */
1510 static const char *const bcm2835_clock_osc_parents[] = {
1517 #define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
1519 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1520 .parents = bcm2835_clock_osc_parents, \
1523 /* main peripherial parent mux */
1524 static const char *const bcm2835_clock_per_parents[] = {
1535 #define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
1537 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1538 .parents = bcm2835_clock_per_parents, \
1542 * Restrict clock sources for the PCM peripheral to the oscillator and
1543 * PLLD_PER because other source may have varying rates or be switched
1546 * Prevent other sources from being selected by replacing their names in
1547 * the list of potential parents with dummy entries (entry index is
1550 static const char *const bcm2835_pcm_per_parents[] = {
1561 #define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
1563 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1564 .parents = bcm2835_pcm_per_parents, \
1567 /* main vpu parent mux */
1568 static const char *const bcm2835_clock_vpu_parents[] = {
1581 #define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
1583 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1584 .parents = bcm2835_clock_vpu_parents, \
1588 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
1589 * analog PHY. The _inv variants are generated internally to cprman,
1590 * but we don't use them so they aren't hooked up.
1592 static const char *const bcm2835_clock_dsi0_parents[] = {
1605 static const char *const bcm2835_clock_dsi1_parents[] = {
1618 #define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
1620 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1621 .parents = bcm2835_clock_dsi0_parents, \
1624 #define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
1626 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1627 .parents = bcm2835_clock_dsi1_parents, \
1631 * the real definition of all the pll, pll_dividers and clocks
1632 * these make use of the above REGISTER_* macros
1634 static const struct bcm2835_clk_desc clk_desc_array[] = {
1635 /* the PLL + PLL dividers */
1638 * PLLA is the auxiliary PLL, used to drive the CCP2
1639 * (Compact Camera Port 2) transmitter clock.
1641 * It is in the PX LDO power domain, which is on when the
1642 * AUDIO domain is on.
1644 [BCM2835_PLLA] = REGISTER_PLL(
1647 .cm_ctrl_reg = CM_PLLA,
1648 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1649 .frac_reg = A2W_PLLA_FRAC,
1650 .ana_reg_base = A2W_PLLA_ANA0,
1651 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1652 .lock_mask = CM_LOCK_FLOCKA,
1654 .ana = &bcm2835_ana_default,
1656 .min_rate = 600000000u,
1657 .max_rate = 2400000000u,
1658 .max_fb_rate = BCM2835_MAX_FB_RATE),
1659 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1661 .name = "plla_core",
1662 .source_pll = "plla",
1664 .a2w_reg = A2W_PLLA_CORE,
1665 .load_mask = CM_PLLA_LOADCORE,
1666 .hold_mask = CM_PLLA_HOLDCORE,
1668 .flags = CLK_SET_RATE_PARENT),
1669 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1672 .source_pll = "plla",
1674 .a2w_reg = A2W_PLLA_PER,
1675 .load_mask = CM_PLLA_LOADPER,
1676 .hold_mask = CM_PLLA_HOLDPER,
1678 .flags = CLK_SET_RATE_PARENT),
1679 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1681 .name = "plla_dsi0",
1682 .source_pll = "plla",
1684 .a2w_reg = A2W_PLLA_DSI0,
1685 .load_mask = CM_PLLA_LOADDSI0,
1686 .hold_mask = CM_PLLA_HOLDDSI0,
1687 .fixed_divider = 1),
1688 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1690 .name = "plla_ccp2",
1691 .source_pll = "plla",
1693 .a2w_reg = A2W_PLLA_CCP2,
1694 .load_mask = CM_PLLA_LOADCCP2,
1695 .hold_mask = CM_PLLA_HOLDCCP2,
1697 .flags = CLK_SET_RATE_PARENT),
1699 /* PLLB is used for the ARM's clock. */
1700 [BCM2835_PLLB] = REGISTER_PLL(
1703 .cm_ctrl_reg = CM_PLLB,
1704 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1705 .frac_reg = A2W_PLLB_FRAC,
1706 .ana_reg_base = A2W_PLLB_ANA0,
1707 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1708 .lock_mask = CM_LOCK_FLOCKB,
1710 .ana = &bcm2835_ana_default,
1712 .min_rate = 600000000u,
1713 .max_rate = 3000000000u,
1714 .max_fb_rate = BCM2835_MAX_FB_RATE,
1715 .flags = CLK_GET_RATE_NOCACHE),
1716 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1719 .source_pll = "pllb",
1721 .a2w_reg = A2W_PLLB_ARM,
1722 .load_mask = CM_PLLB_LOADARM,
1723 .hold_mask = CM_PLLB_HOLDARM,
1725 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
1728 * PLLC is the core PLL, used to drive the core VPU clock.
1730 * It is in the PX LDO power domain, which is on when the
1731 * AUDIO domain is on.
1733 [BCM2835_PLLC] = REGISTER_PLL(
1736 .cm_ctrl_reg = CM_PLLC,
1737 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1738 .frac_reg = A2W_PLLC_FRAC,
1739 .ana_reg_base = A2W_PLLC_ANA0,
1740 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1741 .lock_mask = CM_LOCK_FLOCKC,
1743 .ana = &bcm2835_ana_default,
1745 .min_rate = 600000000u,
1746 .max_rate = 3000000000u,
1747 .max_fb_rate = BCM2835_MAX_FB_RATE),
1748 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1750 .name = "pllc_core0",
1751 .source_pll = "pllc",
1753 .a2w_reg = A2W_PLLC_CORE0,
1754 .load_mask = CM_PLLC_LOADCORE0,
1755 .hold_mask = CM_PLLC_HOLDCORE0,
1757 .flags = CLK_SET_RATE_PARENT),
1758 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1760 .name = "pllc_core1",
1761 .source_pll = "pllc",
1763 .a2w_reg = A2W_PLLC_CORE1,
1764 .load_mask = CM_PLLC_LOADCORE1,
1765 .hold_mask = CM_PLLC_HOLDCORE1,
1767 .flags = CLK_SET_RATE_PARENT),
1768 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1770 .name = "pllc_core2",
1771 .source_pll = "pllc",
1773 .a2w_reg = A2W_PLLC_CORE2,
1774 .load_mask = CM_PLLC_LOADCORE2,
1775 .hold_mask = CM_PLLC_HOLDCORE2,
1777 .flags = CLK_SET_RATE_PARENT),
1778 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1781 .source_pll = "pllc",
1783 .a2w_reg = A2W_PLLC_PER,
1784 .load_mask = CM_PLLC_LOADPER,
1785 .hold_mask = CM_PLLC_HOLDPER,
1787 .flags = CLK_SET_RATE_PARENT),
1790 * PLLD is the display PLL, used to drive DSI display panels.
1792 * It is in the PX LDO power domain, which is on when the
1793 * AUDIO domain is on.
1795 [BCM2835_PLLD] = REGISTER_PLL(
1798 .cm_ctrl_reg = CM_PLLD,
1799 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1800 .frac_reg = A2W_PLLD_FRAC,
1801 .ana_reg_base = A2W_PLLD_ANA0,
1802 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1803 .lock_mask = CM_LOCK_FLOCKD,
1805 .ana = &bcm2835_ana_default,
1807 .min_rate = 600000000u,
1808 .max_rate = 2400000000u,
1809 .max_fb_rate = BCM2835_MAX_FB_RATE),
1810 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1812 .name = "plld_core",
1813 .source_pll = "plld",
1815 .a2w_reg = A2W_PLLD_CORE,
1816 .load_mask = CM_PLLD_LOADCORE,
1817 .hold_mask = CM_PLLD_HOLDCORE,
1819 .flags = CLK_SET_RATE_PARENT),
1821 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
1822 * Otherwise this could cause firmware lookups. That's why we mark
1825 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1828 .source_pll = "plld",
1830 .a2w_reg = A2W_PLLD_PER,
1831 .load_mask = CM_PLLD_LOADPER,
1832 .hold_mask = CM_PLLD_HOLDPER,
1834 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1835 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1837 .name = "plld_dsi0",
1838 .source_pll = "plld",
1840 .a2w_reg = A2W_PLLD_DSI0,
1841 .load_mask = CM_PLLD_LOADDSI0,
1842 .hold_mask = CM_PLLD_HOLDDSI0,
1843 .fixed_divider = 1),
1844 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1846 .name = "plld_dsi1",
1847 .source_pll = "plld",
1849 .a2w_reg = A2W_PLLD_DSI1,
1850 .load_mask = CM_PLLD_LOADDSI1,
1851 .hold_mask = CM_PLLD_HOLDDSI1,
1852 .fixed_divider = 1),
1855 * PLLH is used to supply the pixel clock or the AUX clock for the
1858 * It is in the HDMI power domain.
1860 [BCM2835_PLLH] = REGISTER_PLL(
1863 .cm_ctrl_reg = CM_PLLH,
1864 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1865 .frac_reg = A2W_PLLH_FRAC,
1866 .ana_reg_base = A2W_PLLH_ANA0,
1867 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1868 .lock_mask = CM_LOCK_FLOCKH,
1870 .ana = &bcm2835_ana_pllh,
1872 .min_rate = 600000000u,
1873 .max_rate = 3000000000u,
1874 .max_fb_rate = BCM2835_MAX_FB_RATE),
1875 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1877 .name = "pllh_rcal",
1878 .source_pll = "pllh",
1880 .a2w_reg = A2W_PLLH_RCAL,
1881 .load_mask = CM_PLLH_LOADRCAL,
1883 .fixed_divider = 10,
1884 .flags = CLK_SET_RATE_PARENT),
1885 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1888 .source_pll = "pllh",
1890 .a2w_reg = A2W_PLLH_AUX,
1891 .load_mask = CM_PLLH_LOADAUX,
1894 .flags = CLK_SET_RATE_PARENT),
1895 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1898 .source_pll = "pllh",
1900 .a2w_reg = A2W_PLLH_PIX,
1901 .load_mask = CM_PLLH_LOADPIX,
1903 .fixed_divider = 10,
1904 .flags = CLK_SET_RATE_PARENT),
1908 /* clocks with oscillator parent mux */
1910 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1911 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1914 .ctl_reg = CM_OTPCTL,
1915 .div_reg = CM_OTPDIV,
1920 * Used for a 1Mhz clock for the system clocksource, and also used
1921 * bythe watchdog timer and the camera pulse generator.
1923 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1926 .ctl_reg = CM_TIMERCTL,
1927 .div_reg = CM_TIMERDIV,
1931 * Clock for the temperature sensor.
1932 * Generally run at 2Mhz, max 5Mhz.
1934 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1937 .ctl_reg = CM_TSENSCTL,
1938 .div_reg = CM_TSENSDIV,
1941 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1944 .ctl_reg = CM_TECCTL,
1945 .div_reg = CM_TECDIV,
1949 /* clocks with vpu parent mux */
1950 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1953 .ctl_reg = CM_H264CTL,
1954 .div_reg = CM_H264DIV,
1958 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1961 .ctl_reg = CM_ISPCTL,
1962 .div_reg = CM_ISPDIV,
1968 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1969 * in the SDRAM controller can't be used.
1971 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1974 .ctl_reg = CM_SDCCTL,
1975 .div_reg = CM_SDCDIV,
1979 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1982 .ctl_reg = CM_V3DCTL,
1983 .div_reg = CM_V3DDIV,
1988 * VPU clock. This doesn't have an enable bit, since it drives
1989 * the bus for everything else, and is special so it doesn't need
1990 * to be gated for rate changes. It is also known as "clk_audio"
1991 * in various hardware documentation.
1993 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
1996 .ctl_reg = CM_VPUCTL,
1997 .div_reg = CM_VPUDIV,
2000 .flags = CLK_IS_CRITICAL,
2001 .is_vpu_clock = true,
2004 /* clocks with per parent mux */
2005 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
2008 .ctl_reg = CM_AVEOCTL,
2009 .div_reg = CM_AVEODIV,
2013 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
2016 .ctl_reg = CM_CAM0CTL,
2017 .div_reg = CM_CAM0DIV,
2021 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
2024 .ctl_reg = CM_CAM1CTL,
2025 .div_reg = CM_CAM1DIV,
2029 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
2032 .ctl_reg = CM_DFTCTL,
2033 .div_reg = CM_DFTDIV,
2036 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
2039 .ctl_reg = CM_DPICTL,
2040 .div_reg = CM_DPIDIV,
2045 /* Arasan EMMC clock */
2046 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2049 .ctl_reg = CM_EMMCCTL,
2050 .div_reg = CM_EMMCDIV,
2055 /* EMMC2 clock (only available for BCM2711) */
2056 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
2059 .ctl_reg = CM_EMMC2CTL,
2060 .div_reg = CM_EMMC2DIV,
2065 /* General purpose (GPIO) clocks */
2066 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2069 .ctl_reg = CM_GP0CTL,
2070 .div_reg = CM_GP0DIV,
2073 .is_mash_clock = true,
2075 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2078 .ctl_reg = CM_GP1CTL,
2079 .div_reg = CM_GP1DIV,
2082 .flags = CLK_IS_CRITICAL,
2083 .is_mash_clock = true,
2085 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2088 .ctl_reg = CM_GP2CTL,
2089 .div_reg = CM_GP2DIV,
2092 .flags = CLK_IS_CRITICAL),
2094 /* HDMI state machine */
2095 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2098 .ctl_reg = CM_HSMCTL,
2099 .div_reg = CM_HSMDIV,
2103 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2106 .ctl_reg = CM_PCMCTL,
2107 .div_reg = CM_PCMDIV,
2110 .is_mash_clock = true,
2113 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2116 .ctl_reg = CM_PWMCTL,
2117 .div_reg = CM_PWMDIV,
2120 .is_mash_clock = true,
2122 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2125 .ctl_reg = CM_SLIMCTL,
2126 .div_reg = CM_SLIMDIV,
2129 .is_mash_clock = true,
2131 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2134 .ctl_reg = CM_SMICTL,
2135 .div_reg = CM_SMIDIV,
2139 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2142 .ctl_reg = CM_UARTCTL,
2143 .div_reg = CM_UARTDIV,
2148 /* TV encoder clock. Only operating frequency is 108Mhz. */
2149 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2152 .ctl_reg = CM_VECCTL,
2153 .div_reg = CM_VECDIV,
2157 * Allow rate change propagation only on PLLH_AUX which is
2158 * assigned index 7 in the parent array.
2160 .set_rate_parent = BIT(7),
2164 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2167 .ctl_reg = CM_DSI0ECTL,
2168 .div_reg = CM_DSI0EDIV,
2172 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2175 .ctl_reg = CM_DSI1ECTL,
2176 .div_reg = CM_DSI1EDIV,
2180 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2183 .ctl_reg = CM_DSI0PCTL,
2184 .div_reg = CM_DSI0PDIV,
2188 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2191 .ctl_reg = CM_DSI1PCTL,
2192 .div_reg = CM_DSI1PDIV,
2200 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2201 * you have the debug bit set in the power manager, which we
2202 * don't bother exposing) are individual gates off of the
2203 * non-stop vpu clock.
2205 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2207 .name = "peri_image",
2209 .ctl_reg = CM_PERIICTL),
2213 * Permanently take a reference on the parent of the SDRAM clock.
2215 * While the SDRAM is being driven by its dedicated PLL most of the
2216 * time, there is a little loop running in the firmware that
2217 * periodically switches the SDRAM to using our CM clock to do PVT
2218 * recalibration, with the assumption that the previously configured
2219 * SDRAM parent is still enabled and running.
2221 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2223 struct clk *parent = clk_get_parent(sdc);
2226 return PTR_ERR(parent);
2228 return clk_prepare_enable(parent);
2231 static int bcm2835_clk_probe(struct platform_device *pdev)
2233 struct device *dev = &pdev->dev;
2234 struct clk_hw **hws;
2235 struct bcm2835_cprman *cprman;
2236 const struct bcm2835_clk_desc *desc;
2237 const size_t asize = ARRAY_SIZE(clk_desc_array);
2238 const struct cprman_plat_data *pdata;
2242 pdata = of_device_get_match_data(&pdev->dev);
2246 cprman = devm_kzalloc(dev,
2247 struct_size(cprman, onecell.hws, asize),
2252 spin_lock_init(&cprman->regs_lock);
2254 cprman->regs = devm_platform_ioremap_resource(pdev, 0);
2255 if (IS_ERR(cprman->regs))
2256 return PTR_ERR(cprman->regs);
2258 memcpy(cprman->real_parent_names, cprman_parent_names,
2259 sizeof(cprman_parent_names));
2260 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2261 ARRAY_SIZE(cprman_parent_names));
2264 * Make sure the external oscillator has been registered.
2266 * The other (DSI) clocks are not present on older device
2267 * trees, which we still need to support for backwards
2270 if (!cprman->real_parent_names[0])
2273 platform_set_drvdata(pdev, cprman);
2275 cprman->onecell.num = asize;
2276 cprman->soc = pdata->soc;
2277 hws = cprman->onecell.hws;
2279 for (i = 0; i < asize; i++) {
2280 desc = &clk_desc_array[i];
2281 if (desc->clk_register && desc->data &&
2282 (desc->supported & pdata->soc)) {
2283 hws[i] = desc->clk_register(cprman, desc->data);
2287 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2291 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2295 static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2299 static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2303 static const struct of_device_id bcm2835_clk_of_match[] = {
2304 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2305 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2308 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2310 static struct platform_driver bcm2835_clk_driver = {
2312 .name = "bcm2835-clk",
2313 .of_match_table = bcm2835_clk_of_match,
2315 .probe = bcm2835_clk_probe,
2318 builtin_platform_driver(bcm2835_clk_driver);
2320 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2321 MODULE_DESCRIPTION("BCM2835 clock driver");
2322 MODULE_LICENSE("GPL");