1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Broadcom
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <dt-bindings/clock/bcm2835-aux.h>
12 #define BCM2835_AUXIRQ 0x00
13 #define BCM2835_AUXENB 0x04
15 static int bcm2835_aux_clk_probe(struct platform_device *pdev)
17 struct device *dev = &pdev->dev;
18 struct clk_hw_onecell_data *onecell;
20 struct clk *parent_clk;
22 void __iomem *reg, *gate;
24 parent_clk = devm_clk_get(dev, NULL);
25 if (IS_ERR(parent_clk))
26 return PTR_ERR(parent_clk);
27 parent = __clk_get_name(parent_clk);
29 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
30 reg = devm_ioremap_resource(dev, res);
34 onecell = devm_kmalloc(dev,
35 struct_size(onecell, hws,
36 BCM2835_AUX_CLOCK_COUNT),
40 onecell->num = BCM2835_AUX_CLOCK_COUNT;
42 gate = reg + BCM2835_AUXENB;
43 onecell->hws[BCM2835_AUX_CLOCK_UART] =
44 clk_hw_register_gate(dev, "aux_uart", parent, 0, gate, 0, 0, NULL);
46 onecell->hws[BCM2835_AUX_CLOCK_SPI1] =
47 clk_hw_register_gate(dev, "aux_spi1", parent, 0, gate, 1, 0, NULL);
49 onecell->hws[BCM2835_AUX_CLOCK_SPI2] =
50 clk_hw_register_gate(dev, "aux_spi2", parent, 0, gate, 2, 0, NULL);
52 return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
56 static const struct of_device_id bcm2835_aux_clk_of_match[] = {
57 { .compatible = "brcm,bcm2835-aux", },
60 MODULE_DEVICE_TABLE(of, bcm2835_aux_clk_of_match);
62 static struct platform_driver bcm2835_aux_clk_driver = {
64 .name = "bcm2835-aux-clk",
65 .of_match_table = bcm2835_aux_clk_of_match,
67 .probe = bcm2835_aux_clk_probe,
69 builtin_platform_driver(bcm2835_aux_clk_driver);
71 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
72 MODULE_DESCRIPTION("BCM2835 auxiliary peripheral clock driver");
73 MODULE_LICENSE("GPL");