1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
7 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/slab.h>
15 #include <dt-bindings/clock/at91.h>
19 #define SAMA7G5_INIT_TABLE(_table, _count) \
22 for (_i = 0; _i < (_count); _i++) \
26 #define SAMA7G5_FILL_TABLE(_to, _from, _count) \
29 for (_i = 0; _i < (_count); _i++) { \
30 (_to)[_i] = (_from)[_i]; \
34 static DEFINE_SPINLOCK(pmc_pll_lock);
35 static DEFINE_SPINLOCK(pmc_mck0_lock);
36 static DEFINE_SPINLOCK(pmc_mckX_lock);
39 * PLL clocks identifiers
40 * @PLL_ID_CPU: CPU PLL identifier
41 * @PLL_ID_SYS: System PLL identifier
42 * @PLL_ID_DDR: DDR PLL identifier
43 * @PLL_ID_IMG: Image subsystem PLL identifier
44 * @PLL_ID_BAUD: Baud PLL identifier
45 * @PLL_ID_AUDIO: Audio PLL identifier
46 * @PLL_ID_ETH: Ethernet PLL identifier
60 * PLL type identifiers
61 * @PLL_TYPE_FRAC: fractional PLL identifier
62 * @PLL_TYPE_DIV: divider PLL identifier
69 /* Layout for fractional PLLs. */
70 static const struct clk_pll_layout pll_layout_frac = {
71 .mul_mask = GENMASK(31, 24),
72 .frac_mask = GENMASK(21, 0),
77 /* Layout for DIVPMC dividers. */
78 static const struct clk_pll_layout pll_layout_divpmc = {
79 .div_mask = GENMASK(7, 0),
80 .endiv_mask = BIT(29),
85 /* Layout for DIVIO dividers. */
86 static const struct clk_pll_layout pll_layout_divio = {
87 .div_mask = GENMASK(19, 12),
88 .endiv_mask = BIT(30),
94 * CPU PLL output range.
95 * Notice: The upper limit has been setup to 1000000002 due to hardware
96 * block which cannot output exactly 1GHz.
98 static const struct clk_range cpu_pll_outputs[] = {
99 { .min = 2343750, .max = 1000000002 },
102 /* PLL output range. */
103 static const struct clk_range pll_outputs[] = {
104 { .min = 2343750, .max = 1200000000 },
107 /* CPU PLL characteristics. */
108 static const struct clk_pll_characteristics cpu_pll_characteristics = {
109 .input = { .min = 12000000, .max = 50000000 },
110 .num_output = ARRAY_SIZE(cpu_pll_outputs),
111 .output = cpu_pll_outputs,
114 /* PLL characteristics. */
115 static const struct clk_pll_characteristics pll_characteristics = {
116 .input = { .min = 12000000, .max = 50000000 },
117 .num_output = ARRAY_SIZE(pll_outputs),
118 .output = pll_outputs,
122 * PLL clocks description
126 * @c: clock characteristics
129 * @eid: export index in sama7g5->chws[] array
131 static const struct {
134 const struct clk_pll_layout *l;
135 const struct clk_pll_characteristics *c;
139 } sama7g5_plls[][PLL_ID_MAX] = {
141 { .n = "cpupll_fracck",
143 .l = &pll_layout_frac,
144 .c = &cpu_pll_characteristics,
147 * This feeds cpupll_divpmcck which feeds CPU. It should
150 .f = CLK_IS_CRITICAL, },
152 { .n = "cpupll_divpmcck",
153 .p = "cpupll_fracck",
154 .l = &pll_layout_divpmc,
155 .c = &cpu_pll_characteristics,
157 /* This feeds CPU. It should not be disabled. */
158 .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
159 .eid = PMC_CPUPLL, },
163 { .n = "syspll_fracck",
165 .l = &pll_layout_frac,
166 .c = &pll_characteristics,
169 * This feeds syspll_divpmcck which may feed critial parts
170 * of the systems like timers. Therefore it should not be
173 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
175 { .n = "syspll_divpmcck",
176 .p = "syspll_fracck",
177 .l = &pll_layout_divpmc,
178 .c = &pll_characteristics,
181 * This may feed critial parts of the systems like timers.
182 * Therefore it should not be disabled.
184 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
185 .eid = PMC_SYSPLL, },
189 { .n = "ddrpll_fracck",
191 .l = &pll_layout_frac,
192 .c = &pll_characteristics,
195 * This feeds ddrpll_divpmcck which feeds DDR. It should not
198 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
200 { .n = "ddrpll_divpmcck",
201 .p = "ddrpll_fracck",
202 .l = &pll_layout_divpmc,
203 .c = &pll_characteristics,
205 /* This feeds DDR. It should not be disabled. */
206 .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
210 { .n = "imgpll_fracck",
212 .l = &pll_layout_frac,
213 .c = &pll_characteristics,
215 .f = CLK_SET_RATE_GATE, },
217 { .n = "imgpll_divpmcck",
218 .p = "imgpll_fracck",
219 .l = &pll_layout_divpmc,
220 .c = &pll_characteristics,
222 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
223 CLK_SET_RATE_PARENT, },
227 { .n = "baudpll_fracck",
229 .l = &pll_layout_frac,
230 .c = &pll_characteristics,
232 .f = CLK_SET_RATE_GATE, },
234 { .n = "baudpll_divpmcck",
235 .p = "baudpll_fracck",
236 .l = &pll_layout_divpmc,
237 .c = &pll_characteristics,
239 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
240 CLK_SET_RATE_PARENT, },
244 { .n = "audiopll_fracck",
246 .l = &pll_layout_frac,
247 .c = &pll_characteristics,
249 .f = CLK_SET_RATE_GATE, },
251 { .n = "audiopll_divpmcck",
252 .p = "audiopll_fracck",
253 .l = &pll_layout_divpmc,
254 .c = &pll_characteristics,
256 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
258 .eid = PMC_AUDIOPMCPLL, },
260 { .n = "audiopll_diviock",
261 .p = "audiopll_fracck",
262 .l = &pll_layout_divio,
263 .c = &pll_characteristics,
265 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
267 .eid = PMC_AUDIOIOPLL, },
271 { .n = "ethpll_fracck",
273 .l = &pll_layout_frac,
274 .c = &pll_characteristics,
276 .f = CLK_SET_RATE_GATE, },
278 { .n = "ethpll_divpmcck",
279 .p = "ethpll_fracck",
280 .l = &pll_layout_divpmc,
281 .c = &pll_characteristics,
283 .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
284 CLK_SET_RATE_PARENT, },
289 * Master clock (MCK[1..4]) description
291 * @ep: extra parents names array
292 * @ep_chg_chg_id: index in parents array that specifies the changeable
294 * @ep_count: extra parents count
295 * @ep_mux_table: mux table for extra parents
297 * @c: true if clock is critical and cannot be disabled
299 static const struct {
310 .ep = { "syspll_divpmcck", },
311 .ep_mux_table = { 5, },
313 .ep_chg_id = INT_MIN,
318 .ep = { "ddrpll_divpmcck", },
319 .ep_mux_table = { 6, },
321 .ep_chg_id = INT_MIN,
326 .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", },
327 .ep_mux_table = { 5, 6, 7, },
333 .ep = { "syspll_divpmcck", },
334 .ep_mux_table = { 5, },
336 .ep_chg_id = INT_MIN,
341 * System clock description
343 * @p: clock parent name
346 static const struct {
350 } sama7g5_systemck[] = {
351 { .n = "pck0", .p = "prog0", .id = 8, },
352 { .n = "pck1", .p = "prog1", .id = 9, },
353 { .n = "pck2", .p = "prog2", .id = 10, },
354 { .n = "pck3", .p = "prog3", .id = 11, },
355 { .n = "pck4", .p = "prog4", .id = 12, },
356 { .n = "pck5", .p = "prog5", .id = 13, },
357 { .n = "pck6", .p = "prog6", .id = 14, },
358 { .n = "pck7", .p = "prog7", .id = 15, },
361 /* Mux table for programmable clocks. */
362 static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
365 * Peripheral clock description
367 * @p: clock parent name
368 * @r: clock range values
370 * @chgp: index in parent array of the changeable parent
372 static const struct {
378 } sama7g5_periphck[] = {
379 { .n = "pioA_clk", .p = "mck0", .id = 11, },
380 { .n = "sfr_clk", .p = "mck1", .id = 19, },
381 { .n = "hsmc_clk", .p = "mck1", .id = 21, },
382 { .n = "xdmac0_clk", .p = "mck1", .id = 22, },
383 { .n = "xdmac1_clk", .p = "mck1", .id = 23, },
384 { .n = "xdmac2_clk", .p = "mck1", .id = 24, },
385 { .n = "acc_clk", .p = "mck1", .id = 25, },
386 { .n = "aes_clk", .p = "mck1", .id = 27, },
387 { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, },
388 { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, },
389 { .n = "cpkcc_clk", .p = "mck0", .id = 32, },
390 { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, .chgp = 1, },
391 { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, .chgp = 1, },
392 { .n = "eic_clk", .p = "mck1", .id = 37, },
393 { .n = "flex0_clk", .p = "mck1", .id = 38, },
394 { .n = "flex1_clk", .p = "mck1", .id = 39, },
395 { .n = "flex2_clk", .p = "mck1", .id = 40, },
396 { .n = "flex3_clk", .p = "mck1", .id = 41, },
397 { .n = "flex4_clk", .p = "mck1", .id = 42, },
398 { .n = "flex5_clk", .p = "mck1", .id = 43, },
399 { .n = "flex6_clk", .p = "mck1", .id = 44, },
400 { .n = "flex7_clk", .p = "mck1", .id = 45, },
401 { .n = "flex8_clk", .p = "mck1", .id = 46, },
402 { .n = "flex9_clk", .p = "mck1", .id = 47, },
403 { .n = "flex10_clk", .p = "mck1", .id = 48, },
404 { .n = "flex11_clk", .p = "mck1", .id = 49, },
405 { .n = "gmac0_clk", .p = "mck1", .id = 51, },
406 { .n = "gmac1_clk", .p = "mck1", .id = 52, },
407 { .n = "icm_clk", .p = "mck1", .id = 55, },
408 { .n = "isc_clk", .p = "mck3", .id = 56, .r = { .max = 266000000, }, .chgp = 1, },
409 { .n = "i2smcc0_clk", .p = "mck1", .id = 57, .r = { .max = 200000000, }, },
410 { .n = "i2smcc1_clk", .p = "mck1", .id = 58, .r = { .max = 200000000, }, },
411 { .n = "matrix_clk", .p = "mck1", .id = 60, },
412 { .n = "mcan0_clk", .p = "mck1", .id = 61, .r = { .max = 200000000, }, },
413 { .n = "mcan1_clk", .p = "mck1", .id = 62, .r = { .max = 200000000, }, },
414 { .n = "mcan2_clk", .p = "mck1", .id = 63, .r = { .max = 200000000, }, },
415 { .n = "mcan3_clk", .p = "mck1", .id = 64, .r = { .max = 200000000, }, },
416 { .n = "mcan4_clk", .p = "mck1", .id = 65, .r = { .max = 200000000, }, },
417 { .n = "mcan5_clk", .p = "mck1", .id = 66, .r = { .max = 200000000, }, },
418 { .n = "pdmc0_clk", .p = "mck1", .id = 68, .r = { .max = 200000000, }, },
419 { .n = "pdmc1_clk", .p = "mck1", .id = 69, .r = { .max = 200000000, }, },
420 { .n = "pit64b0_clk", .p = "mck1", .id = 70, },
421 { .n = "pit64b1_clk", .p = "mck1", .id = 71, },
422 { .n = "pit64b2_clk", .p = "mck1", .id = 72, },
423 { .n = "pit64b3_clk", .p = "mck1", .id = 73, },
424 { .n = "pit64b4_clk", .p = "mck1", .id = 74, },
425 { .n = "pit64b5_clk", .p = "mck1", .id = 75, },
426 { .n = "pwm_clk", .p = "mck1", .id = 77, },
427 { .n = "qspi0_clk", .p = "mck1", .id = 78, },
428 { .n = "qspi1_clk", .p = "mck1", .id = 79, },
429 { .n = "sdmmc0_clk", .p = "mck1", .id = 80, },
430 { .n = "sdmmc1_clk", .p = "mck1", .id = 81, },
431 { .n = "sdmmc2_clk", .p = "mck1", .id = 82, },
432 { .n = "sha_clk", .p = "mck1", .id = 83, },
433 { .n = "spdifrx_clk", .p = "mck1", .id = 84, .r = { .max = 200000000, }, },
434 { .n = "spdiftx_clk", .p = "mck1", .id = 85, .r = { .max = 200000000, }, },
435 { .n = "ssc0_clk", .p = "mck1", .id = 86, .r = { .max = 200000000, }, },
436 { .n = "ssc1_clk", .p = "mck1", .id = 87, .r = { .max = 200000000, }, },
437 { .n = "tcb0_ch0_clk", .p = "mck1", .id = 88, .r = { .max = 200000000, }, },
438 { .n = "tcb0_ch1_clk", .p = "mck1", .id = 89, .r = { .max = 200000000, }, },
439 { .n = "tcb0_ch2_clk", .p = "mck1", .id = 90, .r = { .max = 200000000, }, },
440 { .n = "tcb1_ch0_clk", .p = "mck1", .id = 91, .r = { .max = 200000000, }, },
441 { .n = "tcb1_ch1_clk", .p = "mck1", .id = 92, .r = { .max = 200000000, }, },
442 { .n = "tcb1_ch2_clk", .p = "mck1", .id = 93, .r = { .max = 200000000, }, },
443 { .n = "tcpca_clk", .p = "mck1", .id = 94, },
444 { .n = "tcpcb_clk", .p = "mck1", .id = 95, },
445 { .n = "tdes_clk", .p = "mck1", .id = 96, },
446 { .n = "trng_clk", .p = "mck1", .id = 97, },
447 { .n = "udphsa_clk", .p = "mck1", .id = 104, },
448 { .n = "udphsb_clk", .p = "mck1", .id = 105, },
449 { .n = "uhphs_clk", .p = "mck1", .id = 106, },
453 * Generic clock description
456 * @pp_mux_table: PLL parents mux table
457 * @r: clock output range
458 * @pp_chg_id: id in parrent array of changeable PLL parent
459 * @pp_count: PLL parents count
462 static const struct {
465 const char pp_mux_table[8];
473 .r = { .max = 100000000, },
474 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", },
475 .pp_mux_table = { 5, 7, 9, },
477 .pp_chg_id = INT_MIN, },
481 .r = { .max = 200000000 },
482 .pp = { "audiopll_divpmcck", },
483 .pp_mux_table = { 9, },
489 .r = { .max = 27000000 },
490 .pp = { "ddrpll_divpmcck", "imgpll_divpmcck", },
491 .pp_mux_table = { 6, 7, },
493 .pp_chg_id = INT_MIN, },
497 .r = { .max = 200000000 },
498 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
499 .pp_mux_table = { 5, 8, },
501 .pp_chg_id = INT_MIN, },
505 .r = { .max = 200000000 },
506 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
507 .pp_mux_table = { 5, 8, },
509 .pp_chg_id = INT_MIN, },
513 .r = { .max = 200000000 },
514 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
515 .pp_mux_table = { 5, 8, },
517 .pp_chg_id = INT_MIN, },
521 .r = { .max = 200000000 },
522 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
523 .pp_mux_table = { 5, 8, },
525 .pp_chg_id = INT_MIN, },
529 .r = { .max = 200000000 },
530 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
531 .pp_mux_table = { 5, 8, },
533 .pp_chg_id = INT_MIN, },
537 .r = { .max = 200000000 },
538 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
539 .pp_mux_table = { 5, 8, },
541 .pp_chg_id = INT_MIN, },
545 .r = { .max = 200000000 },
546 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
547 .pp_mux_table = { 5, 8, },
549 .pp_chg_id = INT_MIN, },
553 .r = { .max = 200000000 },
554 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
555 .pp_mux_table = { 5, 8, },
557 .pp_chg_id = INT_MIN, },
561 .r = { .max = 200000000 },
562 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
563 .pp_mux_table = { 5, 8, },
565 .pp_chg_id = INT_MIN, },
569 .r = { .max = 200000000 },
570 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
571 .pp_mux_table = { 5, 8, },
573 .pp_chg_id = INT_MIN, },
575 { .n = "flex10_gclk",
577 .r = { .max = 200000000 },
578 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
579 .pp_mux_table = { 5, 8, },
581 .pp_chg_id = INT_MIN, },
583 { .n = "flex11_gclk",
585 .r = { .max = 200000000 },
586 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
587 .pp_mux_table = { 5, 8, },
589 .pp_chg_id = INT_MIN, },
593 .r = { .max = 125000000 },
594 .pp = { "ethpll_divpmcck", },
595 .pp_mux_table = { 10, },
601 .r = { .max = 50000000 },
602 .pp = { "ethpll_divpmcck", },
603 .pp_mux_table = { 10, },
605 .pp_chg_id = INT_MIN, },
607 { .n = "gmac0_tsu_gclk",
609 .r = { .max = 300000000 },
610 .pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
611 .pp_mux_table = { 9, 10, },
613 .pp_chg_id = INT_MIN, },
615 { .n = "gmac1_tsu_gclk",
617 .r = { .max = 300000000 },
618 .pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
619 .pp_mux_table = { 9, 10, },
621 .pp_chg_id = INT_MIN, },
623 { .n = "i2smcc0_gclk",
625 .r = { .max = 100000000 },
626 .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
627 .pp_mux_table = { 5, 9, },
631 { .n = "i2smcc1_gclk",
633 .r = { .max = 100000000 },
634 .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
635 .pp_mux_table = { 5, 9, },
641 .r = { .max = 200000000 },
642 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
643 .pp_mux_table = { 5, 8, },
645 .pp_chg_id = INT_MIN, },
649 .r = { .max = 200000000 },
650 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
651 .pp_mux_table = { 5, 8, },
653 .pp_chg_id = INT_MIN, },
657 .r = { .max = 200000000 },
658 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
659 .pp_mux_table = { 5, 8, },
661 .pp_chg_id = INT_MIN, },
665 .r = { .max = 200000000 },
666 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
667 .pp_mux_table = { 5, 8, },
669 .pp_chg_id = INT_MIN, },
673 .r = { .max = 200000000 },
674 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
675 .pp_mux_table = { 5, 8, },
677 .pp_chg_id = INT_MIN, },
681 .r = { .max = 200000000 },
682 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
683 .pp_mux_table = { 5, 8, },
685 .pp_chg_id = INT_MIN, },
689 .r = { .max = 50000000 },
690 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
691 .pp_mux_table = { 5, 8, },
693 .pp_chg_id = INT_MIN, },
697 .r = { .max = 50000000, },
698 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
699 .pp_mux_table = { 5, 8, },
701 .pp_chg_id = INT_MIN, },
703 { .n = "pit64b0_gclk",
705 .r = { .max = 200000000 },
706 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
707 "audiopll_divpmcck", "ethpll_divpmcck", },
708 .pp_mux_table = { 5, 7, 8, 9, 10, },
710 .pp_chg_id = INT_MIN, },
712 { .n = "pit64b1_gclk",
714 .r = { .max = 200000000 },
715 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
716 "audiopll_divpmcck", "ethpll_divpmcck", },
717 .pp_mux_table = { 5, 7, 8, 9, 10, },
719 .pp_chg_id = INT_MIN, },
721 { .n = "pit64b2_gclk",
723 .r = { .max = 200000000 },
724 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
725 "audiopll_divpmcck", "ethpll_divpmcck", },
726 .pp_mux_table = { 5, 7, 8, 9, 10, },
728 .pp_chg_id = INT_MIN, },
730 { .n = "pit64b3_gclk",
732 .r = { .max = 200000000 },
733 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
734 "audiopll_divpmcck", "ethpll_divpmcck", },
735 .pp_mux_table = { 5, 7, 8, 9, 10, },
737 .pp_chg_id = INT_MIN, },
739 { .n = "pit64b4_gclk",
741 .r = { .max = 200000000 },
742 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
743 "audiopll_divpmcck", "ethpll_divpmcck", },
744 .pp_mux_table = { 5, 7, 8, 9, 10, },
746 .pp_chg_id = INT_MIN, },
748 { .n = "pit64b5_gclk",
750 .r = { .max = 200000000 },
751 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
752 "audiopll_divpmcck", "ethpll_divpmcck", },
753 .pp_mux_table = { 5, 7, 8, 9, 10, },
755 .pp_chg_id = INT_MIN, },
759 .r = { .max = 200000000 },
760 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
761 .pp_mux_table = { 5, 8, },
763 .pp_chg_id = INT_MIN, },
767 .r = { .max = 200000000 },
768 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
769 .pp_mux_table = { 5, 8, },
771 .pp_chg_id = INT_MIN, },
773 { .n = "sdmmc0_gclk",
775 .r = { .max = 208000000 },
776 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
777 .pp_mux_table = { 5, 8, },
781 { .n = "sdmmc1_gclk",
783 .r = { .max = 208000000 },
784 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
785 .pp_mux_table = { 5, 8, },
789 { .n = "sdmmc2_gclk",
791 .r = { .max = 208000000 },
792 .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
793 .pp_mux_table = { 5, 8, },
797 { .n = "spdifrx_gclk",
799 .r = { .max = 150000000 },
800 .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
801 .pp_mux_table = { 5, 9, },
805 { .n = "spdiftx_gclk",
807 .r = { .max = 25000000 },
808 .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
809 .pp_mux_table = { 5, 9, },
813 { .n = "tcb0_ch0_gclk",
815 .r = { .max = 200000000 },
816 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
817 "audiopll_divpmcck", "ethpll_divpmcck", },
818 .pp_mux_table = { 5, 7, 8, 9, 10, },
820 .pp_chg_id = INT_MIN, },
822 { .n = "tcb1_ch0_gclk",
824 .r = { .max = 200000000 },
825 .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
826 "audiopll_divpmcck", "ethpll_divpmcck", },
827 .pp_mux_table = { 5, 7, 8, 9, 10, },
829 .pp_chg_id = INT_MIN, },
833 .r = { .max = 32768, },
834 .pp_chg_id = INT_MIN, },
838 .r = { .max = 32768, },
839 .pp_chg_id = INT_MIN, },
842 /* MCK0 characteristics. */
843 static const struct clk_master_characteristics mck0_characteristics = {
844 .output = { .min = 50000000, .max = 200000000 },
845 .divisors = { 1, 2, 4, 3, 5 },
850 static const struct clk_master_layout mck0_layout = {
856 /* Programmable clock layout. */
857 static const struct clk_programmable_layout programmable_layout = {
865 /* Peripheral clock layout. */
866 static const struct clk_pcr_layout sama7g5_pcr_layout = {
869 .gckcss_mask = GENMASK(12, 8),
870 .pid_mask = GENMASK(6, 0),
873 static void __init sama7g5_pmc_setup(struct device_node *np)
875 const char *td_slck_name, *md_slck_name, *mainxtal_name;
876 struct pmc_data *sama7g5_pmc;
877 const char *parent_names[10];
878 void **alloc_mem = NULL;
879 int alloc_mem_size = 0;
880 struct regmap *regmap;
885 i = of_property_match_string(np, "clock-names", "td_slck");
889 td_slck_name = of_clk_get_parent_name(np, i);
891 i = of_property_match_string(np, "clock-names", "md_slck");
895 md_slck_name = of_clk_get_parent_name(np, i);
897 i = of_property_match_string(np, "clock-names", "main_xtal");
901 mainxtal_name = of_clk_get_parent_name(np, i);
903 regmap = device_node_to_regmap(np);
907 sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
908 nck(sama7g5_systemck),
909 nck(sama7g5_periphck),
910 nck(sama7g5_gck), 8);
914 alloc_mem = kmalloc(sizeof(void *) *
915 (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)),
920 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
925 bypass = of_property_read_bool(np, "atmel,osc-bypass");
927 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
932 parent_names[0] = "main_rc_osc";
933 parent_names[1] = "main_osc";
934 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
938 sama7g5_pmc->chws[PMC_MAIN] = hw;
940 for (i = 0; i < PLL_ID_MAX; i++) {
941 for (j = 0; j < 3; j++) {
942 struct clk_hw *parent_hw;
944 if (!sama7g5_plls[i][j].n)
947 switch (sama7g5_plls[i][j].t) {
949 if (!strcmp(sama7g5_plls[i][j].p, "mainck"))
950 parent_hw = sama7g5_pmc->chws[PMC_MAIN];
952 parent_hw = __clk_get_hw(of_clk_get_by_name(np,
953 sama7g5_plls[i][j].p));
955 hw = sam9x60_clk_register_frac_pll(regmap,
956 &pmc_pll_lock, sama7g5_plls[i][j].n,
957 sama7g5_plls[i][j].p, parent_hw, i,
958 sama7g5_plls[i][j].c,
959 sama7g5_plls[i][j].l,
960 sama7g5_plls[i][j].f);
964 hw = sam9x60_clk_register_div_pll(regmap,
965 &pmc_pll_lock, sama7g5_plls[i][j].n,
966 sama7g5_plls[i][j].p, i,
967 sama7g5_plls[i][j].c,
968 sama7g5_plls[i][j].l,
969 sama7g5_plls[i][j].f);
979 if (sama7g5_plls[i][j].eid)
980 sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw;
984 parent_names[0] = "cpupll_divpmcck";
985 hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
986 &mck0_layout, &mck0_characteristics,
988 CLK_SET_RATE_PARENT, 0);
992 sama7g5_pmc->chws[PMC_CPU] = hw;
994 hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
995 &mck0_layout, &mck0_characteristics,
1000 sama7g5_pmc->chws[PMC_MCK] = hw;
1002 parent_names[0] = md_slck_name;
1003 parent_names[1] = td_slck_name;
1004 parent_names[2] = "mainck";
1005 for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
1006 u8 num_parents = 3 + sama7g5_mckx[i].ep_count;
1009 mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
1014 SAMA7G5_INIT_TABLE(mux_table, 3);
1015 SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
1016 sama7g5_mckx[i].ep_count);
1017 SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep,
1018 sama7g5_mckx[i].ep_count);
1020 hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
1021 num_parents, parent_names, mux_table,
1022 &pmc_mckX_lock, sama7g5_mckx[i].id,
1024 sama7g5_mckx[i].ep_chg_id);
1028 alloc_mem[alloc_mem_size++] = mux_table;
1031 hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal");
1035 sama7g5_pmc->chws[PMC_UTMI] = hw;
1037 parent_names[0] = md_slck_name;
1038 parent_names[1] = td_slck_name;
1039 parent_names[2] = "mainck";
1040 parent_names[3] = "syspll_divpmcck";
1041 parent_names[4] = "ddrpll_divpmcck";
1042 parent_names[5] = "imgpll_divpmcck";
1043 parent_names[6] = "baudpll_divpmcck";
1044 parent_names[7] = "audiopll_divpmcck";
1045 parent_names[8] = "ethpll_divpmcck";
1046 for (i = 0; i < 8; i++) {
1049 snprintf(name, sizeof(name), "prog%d", i);
1051 hw = at91_clk_register_programmable(regmap, name, parent_names,
1053 &programmable_layout,
1054 sama7g5_prog_mux_table);
1058 sama7g5_pmc->pchws[i] = hw;
1061 for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) {
1062 hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n,
1063 sama7g5_systemck[i].p,
1064 sama7g5_systemck[i].id);
1068 sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw;
1071 for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) {
1072 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
1073 &sama7g5_pcr_layout,
1074 sama7g5_periphck[i].n,
1075 sama7g5_periphck[i].p,
1076 sama7g5_periphck[i].id,
1077 &sama7g5_periphck[i].r,
1078 sama7g5_periphck[i].chgp ? 0 :
1083 sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw;
1086 parent_names[0] = md_slck_name;
1087 parent_names[1] = td_slck_name;
1088 parent_names[2] = "mainck";
1089 for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
1090 u8 num_parents = 3 + sama7g5_gck[i].pp_count;
1093 mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
1098 SAMA7G5_INIT_TABLE(mux_table, 3);
1099 SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
1100 sama7g5_gck[i].pp_count);
1101 SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp,
1102 sama7g5_gck[i].pp_count);
1104 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
1105 &sama7g5_pcr_layout,
1107 parent_names, mux_table,
1111 sama7g5_gck[i].pp_chg_id);
1115 sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw;
1116 alloc_mem[alloc_mem_size++] = mux_table;
1119 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc);
1125 for (i = 0; i < alloc_mem_size; i++)
1126 kfree(alloc_mem[i]);
1133 /* Some clks are used for a clocksource */
1134 CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup);