drivers/clk/at91/sama5d4.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/clk-provider.h>
   3 #include <linux/mfd/syscon.h>
   4 #include <linux/slab.h>
   5
   6 #include <dt-bindings/clock/at91.h>
   7
   8 #include "pmc.h"
   9
  10 static DEFINE_SPINLOCK(mck_lock);
  11
  12 static const struct clk_master_characteristics mck_characteristics = {
  13         .output = { .min = 125000000, .max = 200000000 },
  14         .divisors = { 1, 2, 4, 3 },
  15 };
  16
  17 static u8 plla_out[] = { 0 };
  18
  19 static u16 plla_icpll[] = { 0 };
  20
  21 static const struct clk_range plla_outputs[] = {
  22         { .min = 600000000, .max = 1200000000 },
  23 };
  24
  25 static const struct clk_pll_characteristics plla_characteristics = {
  26         .input = { .min = 12000000, .max = 12000000 },
  27         .num_output = ARRAY_SIZE(plla_outputs),
  28         .output = plla_outputs,
  29         .icpll = plla_icpll,
  30         .out = plla_out,
  31 };
  32
  33 static const struct clk_pcr_layout sama5d4_pcr_layout = {
  34         .offset = 0x10c,
  35         .cmd = BIT(12),
  36         .pid_mask = GENMASK(6, 0),
  37 };
  38
  39 static const struct {
  40         char *n;
  41         char *p;
  42         u8 id;
  43 } sama5d4_systemck[] = {
  44         { .n = "ddrck", .p = "masterck_div", .id = 2 },
  45         { .n = "lcdck", .p = "masterck_div", .id = 3 },
  46         { .n = "smdck", .p = "smdclk",       .id = 4 },
  47         { .n = "uhpck", .p = "usbck",        .id = 6 },
  48         { .n = "udpck", .p = "usbck",        .id = 7 },
  49         { .n = "pck0",  .p = "prog0",        .id = 8 },
  50         { .n = "pck1",  .p = "prog1",        .id = 9 },
  51         { .n = "pck2",  .p = "prog2",        .id = 10 },
  52 };
  53
  54 static const struct {
  55         char *n;
  56         u8 id;
  57 } sama5d4_periph32ck[] = {
  58         { .n = "pioD_clk", .id = 5 },
  59         { .n = "usart0_clk", .id = 6 },
  60         { .n = "usart1_clk", .id = 7 },
  61         { .n = "icm_clk", .id = 9 },
  62         { .n = "aes_clk", .id = 12 },
  63         { .n = "tdes_clk", .id = 14 },
  64         { .n = "sha_clk", .id = 15 },
  65         { .n = "matrix1_clk", .id = 17 },
  66         { .n = "hsmc_clk", .id = 22 },
  67         { .n = "pioA_clk", .id = 23 },
  68         { .n = "pioB_clk", .id = 24 },
  69         { .n = "pioC_clk", .id = 25 },
  70         { .n = "pioE_clk", .id = 26 },
  71         { .n = "uart0_clk", .id = 27 },
  72         { .n = "uart1_clk", .id = 28 },
  73         { .n = "usart2_clk", .id = 29 },
  74         { .n = "usart3_clk", .id = 30 },
  75         { .n = "usart4_clk", .id = 31 },
  76         { .n = "twi0_clk", .id = 32 },
  77         { .n = "twi1_clk", .id = 33 },
  78         { .n = "twi2_clk", .id = 34 },
  79         { .n = "mci0_clk", .id = 35 },
  80         { .n = "mci1_clk", .id = 36 },
  81         { .n = "spi0_clk", .id = 37 },
  82         { .n = "spi1_clk", .id = 38 },
  83         { .n = "spi2_clk", .id = 39 },
  84         { .n = "tcb0_clk", .id = 40 },
  85         { .n = "tcb1_clk", .id = 41 },
  86         { .n = "tcb2_clk", .id = 42 },
  87         { .n = "pwm_clk", .id = 43 },
  88         { .n = "adc_clk", .id = 44 },
  89         { .n = "dbgu_clk", .id = 45 },
  90         { .n = "uhphs_clk", .id = 46 },
  91         { .n = "udphs_clk", .id = 47 },
  92         { .n = "ssc0_clk", .id = 48 },
  93         { .n = "ssc1_clk", .id = 49 },
  94         { .n = "trng_clk", .id = 53 },
  95         { .n = "macb0_clk", .id = 54 },
  96         { .n = "macb1_clk", .id = 55 },
  97         { .n = "fuse_clk", .id = 57 },
  98         { .n = "securam_clk", .id = 59 },
  99         { .n = "smd_clk", .id = 61 },
 100         { .n = "twi3_clk", .id = 62 },
 101         { .n = "catb_clk", .id = 63 },
 102 };
 103
 104 static const struct {
 105         char *n;
 106         u8 id;
 107 } sama5d4_periphck[] = {
 108         { .n = "dma0_clk", .id = 8 },
 109         { .n = "cpkcc_clk", .id = 10 },
 110         { .n = "aesb_clk", .id = 13 },
 111         { .n = "mpddr_clk", .id = 16 },
 112         { .n = "matrix0_clk", .id = 18 },
 113         { .n = "vdec_clk", .id = 19 },
 114         { .n = "dma1_clk", .id = 50 },
 115         { .n = "lcdc_clk", .id = 51 },
 116         { .n = "isi_clk", .id = 52 },
 117 };
 118
 119 static void __init sama5d4_pmc_setup(struct device_node *np)
 120 {
 121         struct clk_range range = CLK_RANGE(0, 0);
 122         const char *slck_name, *mainxtal_name;
 123         struct pmc_data *sama5d4_pmc;
 124         const char *parent_names[5];
 125         struct regmap *regmap;
 126         struct clk_hw *hw;
 127         int i;
 128         bool bypass;
 129
 130         i = of_property_match_string(np, "clock-names", "slow_clk");
 131         if (i < 0)
 132                 return;
 133
 134         slck_name = of_clk_get_parent_name(np, i);
 135
 136         i = of_property_match_string(np, "clock-names", "main_xtal");
 137         if (i < 0)
 138                 return;
 139         mainxtal_name = of_clk_get_parent_name(np, i);
 140
 141         regmap = device_node_to_regmap(np);
 142         if (IS_ERR(regmap))
 143                 return;
 144
 145         sama5d4_pmc = pmc_data_allocate(PMC_PLLACK + 1,
 146                                         nck(sama5d4_systemck),
 147                                         nck(sama5d4_periph32ck), 0, 3);
 148         if (!sama5d4_pmc)
 149                 return;
 150
 151         hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
 152                                            100000000);
 153         if (IS_ERR(hw))
 154                 goto err_free;
 155
 156         bypass = of_property_read_bool(np, "atmel,osc-bypass");
 157
 158         hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
 159                                         bypass);
 160         if (IS_ERR(hw))
 161                 goto err_free;
 162
 163         parent_names[0] = "main_rc_osc";
 164         parent_names[1] = "main_osc";
 165         hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
 166         if (IS_ERR(hw))
 167                 goto err_free;
 168
 169         hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
 170                                    &sama5d3_pll_layout, &plla_characteristics);
 171         if (IS_ERR(hw))
 172                 goto err_free;
 173
 174         hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
 175         if (IS_ERR(hw))
 176                 goto err_free;
 177
 178         sama5d4_pmc->chws[PMC_PLLACK] = hw;
 179
 180         hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
 181         if (IS_ERR(hw))
 182                 goto err_free;
 183
 184         sama5d4_pmc->chws[PMC_UTMI] = hw;
 185
 186         parent_names[0] = slck_name;
 187         parent_names[1] = "mainck";
 188         parent_names[2] = "plladivck";
 189         parent_names[3] = "utmick";
 190         hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
 191                                            parent_names,
 192                                            &at91sam9x5_master_layout,
 193                                            &mck_characteristics, &mck_lock,
 194                                            CLK_SET_RATE_GATE, INT_MIN);
 195         if (IS_ERR(hw))
 196                 goto err_free;
 197
 198         hw = at91_clk_register_master_div(regmap, "masterck_div",
 199                                           "masterck_pres",
 200                                           &at91sam9x5_master_layout,
 201                                           &mck_characteristics, &mck_lock,
 202                                           CLK_SET_RATE_GATE, 0);
 203         if (IS_ERR(hw))
 204                 goto err_free;
 205
 206         sama5d4_pmc->chws[PMC_MCK] = hw;
 207
 208         hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
 209         if (IS_ERR(hw))
 210                 goto err_free;
 211
 212         sama5d4_pmc->chws[PMC_MCK2] = hw;
 213
 214         parent_names[0] = "plladivck";
 215         parent_names[1] = "utmick";
 216         hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
 217         if (IS_ERR(hw))
 218                 goto err_free;
 219
 220         parent_names[0] = "plladivck";
 221         parent_names[1] = "utmick";
 222         hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
 223         if (IS_ERR(hw))
 224                 goto err_free;
 225
 226         parent_names[0] = slck_name;
 227         parent_names[1] = "mainck";
 228         parent_names[2] = "plladivck";
 229         parent_names[3] = "utmick";
 230         parent_names[4] = "masterck_div";
 231         for (i = 0; i < 3; i++) {
 232                 char name[6];
 233
 234                 snprintf(name, sizeof(name), "prog%d", i);
 235
 236                 hw = at91_clk_register_programmable(regmap, name,
 237                                                     parent_names, 5, i,
 238                                                     &at91sam9x5_programmable_layout,
 239                                                     NULL);
 240                 if (IS_ERR(hw))
 241                         goto err_free;
 242
 243                 sama5d4_pmc->pchws[i] = hw;
 244         }
 245
 246         for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {
 247                 hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,
 248                                               sama5d4_systemck[i].p,
 249                                               sama5d4_systemck[i].id);
 250                 if (IS_ERR(hw))
 251                         goto err_free;
 252
 253                 sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw;
 254         }
 255
 256         for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) {
 257                 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 258                                                          &sama5d4_pcr_layout,
 259                                                          sama5d4_periphck[i].n,
 260                                                          "masterck_div",
 261                                                          sama5d4_periphck[i].id,
 262                                                          &range, INT_MIN);
 263                 if (IS_ERR(hw))
 264                         goto err_free;
 265
 266                 sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw;
 267         }
 268
 269         for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) {
 270                 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 271                                                          &sama5d4_pcr_layout,
 272                                                          sama5d4_periph32ck[i].n,
 273                                                          "h32mxck",
 274                                                          sama5d4_periph32ck[i].id,
 275                                                          &range, INT_MIN);
 276                 if (IS_ERR(hw))
 277                         goto err_free;
 278
 279                 sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw;
 280         }
 281
 282         of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc);
 283
 284         return;
 285
 286 err_free:
 287         kfree(sama5d4_pmc);
 288 }
 289
 290 CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);