1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
6 #include <dt-bindings/clock/at91.h>
10 static const struct clk_master_characteristics mck_characteristics = {
11 .output = { .min = 124000000, .max = 166000000 },
12 .divisors = { 1, 2, 4, 3 },
15 static u8 plla_out[] = { 0 };
17 static u16 plla_icpll[] = { 0 };
19 static const struct clk_range plla_outputs[] = {
20 { .min = 600000000, .max = 1200000000 },
23 static const struct clk_pll_characteristics plla_characteristics = {
24 .input = { .min = 12000000, .max = 24000000 },
25 .num_output = ARRAY_SIZE(plla_outputs),
26 .output = plla_outputs,
31 static const struct clk_pcr_layout sama5d2_pcr_layout = {
34 .gckcss_mask = GENMASK(10, 8),
35 .pid_mask = GENMASK(6, 0),
42 } sama5d2_systemck[] = {
43 { .n = "ddrck", .p = "masterck", .id = 2 },
44 { .n = "lcdck", .p = "masterck", .id = 3 },
45 { .n = "uhpck", .p = "usbck", .id = 6 },
46 { .n = "udpck", .p = "usbck", .id = 7 },
47 { .n = "pck0", .p = "prog0", .id = 8 },
48 { .n = "pck1", .p = "prog1", .id = 9 },
49 { .n = "pck2", .p = "prog2", .id = 10 },
50 { .n = "iscck", .p = "masterck", .id = 18 },
57 } sama5d2_periph32ck[] = {
58 { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, },
59 { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, },
60 { .n = "matrix1_clk", .id = 14, },
61 { .n = "hsmc_clk", .id = 17, },
62 { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, },
63 { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, },
64 { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, },
65 { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, },
66 { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, },
67 { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, },
68 { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, },
69 { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, },
70 { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, },
71 { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, },
72 { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, },
73 { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
74 { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, },
75 { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, },
76 { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, },
77 { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
78 { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
79 { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
80 { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
81 { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
82 { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, },
83 { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, },
84 { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, },
85 { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
86 { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
87 { .n = "securam_clk", .id = 51, },
88 { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
89 { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
90 { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
91 { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
92 { .n = "ptc_clk", .id = 58, .r = { .min = 0, .max = 83000000 }, },
93 { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
99 } sama5d2_periphck[] = {
100 { .n = "dma0_clk", .id = 6, },
101 { .n = "dma1_clk", .id = 7, },
102 { .n = "aes_clk", .id = 9, },
103 { .n = "aesb_clk", .id = 10, },
104 { .n = "sha_clk", .id = 12, },
105 { .n = "mpddr_clk", .id = 13, },
106 { .n = "matrix0_clk", .id = 15, },
107 { .n = "sdmmc0_hclk", .id = 31, },
108 { .n = "sdmmc1_hclk", .id = 32, },
109 { .n = "lcdc_clk", .id = 45, },
110 { .n = "isc_clk", .id = 46, },
111 { .n = "qspi0_clk", .id = 52, },
112 { .n = "qspi1_clk", .id = 53, },
115 static const struct {
121 { .n = "sdmmc0_gclk", .id = 31, },
122 { .n = "sdmmc1_gclk", .id = 32, },
123 { .n = "tcb0_gclk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
124 { .n = "tcb1_gclk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
125 { .n = "pwm_gclk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
126 { .n = "isc_gclk", .id = 46, },
127 { .n = "pdmic_gclk", .id = 48, },
128 { .n = "i2s0_gclk", .id = 54, .pll = true },
129 { .n = "i2s1_gclk", .id = 55, .pll = true },
130 { .n = "can0_gclk", .id = 56, .r = { .min = 0, .max = 80000000 }, },
131 { .n = "can1_gclk", .id = 57, .r = { .min = 0, .max = 80000000 }, },
132 { .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 100000000 },
136 static const struct clk_programmable_layout sama5d2_programmable_layout = {
144 static void __init sama5d2_pmc_setup(struct device_node *np)
146 struct clk_range range = CLK_RANGE(0, 0);
147 const char *slck_name, *mainxtal_name;
148 struct pmc_data *sama5d2_pmc;
149 const char *parent_names[6];
150 struct regmap *regmap, *regmap_sfr;
155 i = of_property_match_string(np, "clock-names", "slow_clk");
159 slck_name = of_clk_get_parent_name(np, i);
161 i = of_property_match_string(np, "clock-names", "main_xtal");
164 mainxtal_name = of_clk_get_parent_name(np, i);
166 regmap = device_node_to_regmap(np);
170 sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPLLCK + 1,
171 nck(sama5d2_systemck),
172 nck(sama5d2_periph32ck),
173 nck(sama5d2_gck), 3);
177 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
182 bypass = of_property_read_bool(np, "atmel,osc-bypass");
184 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
189 parent_names[0] = "main_rc_osc";
190 parent_names[1] = "main_osc";
191 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
195 sama5d2_pmc->chws[PMC_MAIN] = hw;
197 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
198 &sama5d3_pll_layout, &plla_characteristics);
202 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
206 sama5d2_pmc->chws[PMC_PLLACK] = hw;
208 hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
213 hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
218 hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
223 sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw;
225 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
226 if (IS_ERR(regmap_sfr))
229 hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
233 sama5d2_pmc->chws[PMC_UTMI] = hw;
235 parent_names[0] = slck_name;
236 parent_names[1] = "mainck";
237 parent_names[2] = "plladivck";
238 parent_names[3] = "utmick";
239 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
240 &at91sam9x5_master_layout,
241 &mck_characteristics);
245 sama5d2_pmc->chws[PMC_MCK] = hw;
247 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
251 sama5d2_pmc->chws[PMC_MCK2] = hw;
253 parent_names[0] = "plladivck";
254 parent_names[1] = "utmick";
255 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
259 parent_names[0] = slck_name;
260 parent_names[1] = "mainck";
261 parent_names[2] = "plladivck";
262 parent_names[3] = "utmick";
263 parent_names[4] = "masterck";
264 parent_names[5] = "audiopll_pmcck";
265 for (i = 0; i < 3; i++) {
268 snprintf(name, sizeof(name), "prog%d", i);
270 hw = at91_clk_register_programmable(regmap, name,
272 &sama5d2_programmable_layout);
276 sama5d2_pmc->pchws[i] = hw;
279 for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
280 hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
281 sama5d2_systemck[i].p,
282 sama5d2_systemck[i].id);
286 sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
289 for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
290 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
292 sama5d2_periphck[i].n,
294 sama5d2_periphck[i].id,
299 sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
302 for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
303 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
305 sama5d2_periph32ck[i].n,
307 sama5d2_periph32ck[i].id,
308 &sama5d2_periph32ck[i].r);
312 sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
315 parent_names[0] = slck_name;
316 parent_names[1] = "mainck";
317 parent_names[2] = "plladivck";
318 parent_names[3] = "utmick";
319 parent_names[4] = "masterck";
320 parent_names[5] = "audiopll_pmcck";
321 for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
322 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
332 sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
336 parent_names[0] = "i2s0_clk";
337 parent_names[1] = "i2s0_gclk";
338 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
343 sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
345 parent_names[0] = "i2s1_clk";
346 parent_names[1] = "i2s1_gclk";
347 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
352 sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
355 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
362 CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);