1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
6 #include <dt-bindings/clock/at91.h>
10 static DEFINE_SPINLOCK(pmc_pll_lock);
12 static const struct clk_master_characteristics mck_characteristics = {
13 .output = { .min = 140000000, .max = 200000000 },
14 .divisors = { 1, 2, 4, 3 },
18 static const struct clk_master_layout sam9x60_master_layout = {
24 static const struct clk_range plla_outputs[] = {
25 { .min = 300000000, .max = 600000000 },
28 static const struct clk_pll_characteristics plla_characteristics = {
29 .input = { .min = 12000000, .max = 48000000 },
30 .num_output = ARRAY_SIZE(plla_outputs),
31 .output = plla_outputs,
34 static const struct clk_range upll_outputs[] = {
35 { .min = 300000000, .max = 500000000 },
38 static const struct clk_pll_characteristics upll_characteristics = {
39 .input = { .min = 12000000, .max = 48000000 },
40 .num_output = ARRAY_SIZE(upll_outputs),
41 .output = upll_outputs,
45 static const struct clk_programmable_layout sam9x60_programmable_layout = {
53 static const struct clk_pcr_layout sam9x60_pcr_layout = {
56 .gckcss_mask = GENMASK(12, 8),
57 .pid_mask = GENMASK(6, 0),
64 } sam9x60_systemck[] = {
65 { .n = "ddrck", .p = "masterck", .id = 2 },
66 { .n = "uhpck", .p = "usbck", .id = 6 },
67 { .n = "pck0", .p = "prog0", .id = 8 },
68 { .n = "pck1", .p = "prog1", .id = 9 },
69 { .n = "qspick", .p = "masterck", .id = 19 },
75 } sam9x60_periphck[] = {
76 { .n = "pioA_clk", .id = 2, },
77 { .n = "pioB_clk", .id = 3, },
78 { .n = "pioC_clk", .id = 4, },
79 { .n = "flex0_clk", .id = 5, },
80 { .n = "flex1_clk", .id = 6, },
81 { .n = "flex2_clk", .id = 7, },
82 { .n = "flex3_clk", .id = 8, },
83 { .n = "flex6_clk", .id = 9, },
84 { .n = "flex7_clk", .id = 10, },
85 { .n = "flex8_clk", .id = 11, },
86 { .n = "sdmmc0_clk", .id = 12, },
87 { .n = "flex4_clk", .id = 13, },
88 { .n = "flex5_clk", .id = 14, },
89 { .n = "flex9_clk", .id = 15, },
90 { .n = "flex10_clk", .id = 16, },
91 { .n = "tcb0_clk", .id = 17, },
92 { .n = "pwm_clk", .id = 18, },
93 { .n = "adc_clk", .id = 19, },
94 { .n = "dma0_clk", .id = 20, },
95 { .n = "matrix_clk", .id = 21, },
96 { .n = "uhphs_clk", .id = 22, },
97 { .n = "udphs_clk", .id = 23, },
98 { .n = "macb0_clk", .id = 24, },
99 { .n = "lcd_clk", .id = 25, },
100 { .n = "sdmmc1_clk", .id = 26, },
101 { .n = "macb1_clk", .id = 27, },
102 { .n = "ssc_clk", .id = 28, },
103 { .n = "can0_clk", .id = 29, },
104 { .n = "can1_clk", .id = 30, },
105 { .n = "flex11_clk", .id = 32, },
106 { .n = "flex12_clk", .id = 33, },
107 { .n = "i2s_clk", .id = 34, },
108 { .n = "qspi_clk", .id = 35, },
109 { .n = "gfx2d_clk", .id = 36, },
110 { .n = "pit64b_clk", .id = 37, },
111 { .n = "trng_clk", .id = 38, },
112 { .n = "aes_clk", .id = 39, },
113 { .n = "tdes_clk", .id = 40, },
114 { .n = "sha_clk", .id = 41, },
115 { .n = "classd_clk", .id = 42, },
116 { .n = "isi_clk", .id = 43, },
117 { .n = "pioD_clk", .id = 44, },
118 { .n = "tcb1_clk", .id = 45, },
119 { .n = "dbgu_clk", .id = 47, },
120 { .n = "mpddr_clk", .id = 49, },
123 static const struct {
128 { .n = "flex0_gclk", .id = 5, },
129 { .n = "flex1_gclk", .id = 6, },
130 { .n = "flex2_gclk", .id = 7, },
131 { .n = "flex3_gclk", .id = 8, },
132 { .n = "flex6_gclk", .id = 9, },
133 { .n = "flex7_gclk", .id = 10, },
134 { .n = "flex8_gclk", .id = 11, },
135 { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },
136 { .n = "flex4_gclk", .id = 13, },
137 { .n = "flex5_gclk", .id = 14, },
138 { .n = "flex9_gclk", .id = 15, },
139 { .n = "flex10_gclk", .id = 16, },
140 { .n = "tcb0_gclk", .id = 17, },
141 { .n = "adc_gclk", .id = 19, },
142 { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, },
143 { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },
144 { .n = "flex11_gclk", .id = 32, },
145 { .n = "flex12_gclk", .id = 33, },
146 { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, },
147 { .n = "pit64b_gclk", .id = 37, },
148 { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, },
149 { .n = "tcb1_gclk", .id = 45, },
150 { .n = "dbgu_gclk", .id = 47, },
153 static void __init sam9x60_pmc_setup(struct device_node *np)
155 struct clk_range range = CLK_RANGE(0, 0);
156 const char *td_slck_name, *md_slck_name, *mainxtal_name;
157 struct pmc_data *sam9x60_pmc;
158 const char *parent_names[6];
159 struct regmap *regmap;
164 i = of_property_match_string(np, "clock-names", "td_slck");
168 td_slck_name = of_clk_get_parent_name(np, i);
170 i = of_property_match_string(np, "clock-names", "md_slck");
174 md_slck_name = of_clk_get_parent_name(np, i);
176 i = of_property_match_string(np, "clock-names", "main_xtal");
179 mainxtal_name = of_clk_get_parent_name(np, i);
181 regmap = syscon_node_to_regmap(np);
185 sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1,
186 nck(sam9x60_systemck),
187 nck(sam9x60_periphck),
188 nck(sam9x60_gck), 8);
192 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 24000000,
197 bypass = of_property_read_bool(np, "atmel,osc-bypass");
199 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
204 parent_names[0] = "main_rc_osc";
205 parent_names[1] = "main_osc";
206 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
210 sam9x60_pmc->chws[PMC_MAIN] = hw;
212 hw = sam9x60_clk_register_pll(regmap, &pmc_pll_lock, "pllack",
213 "mainck", 0, &plla_characteristics);
217 sam9x60_pmc->chws[PMC_PLLACK] = hw;
219 hw = sam9x60_clk_register_pll(regmap, &pmc_pll_lock, "upllck",
220 "main_osc", 1, &upll_characteristics);
224 sam9x60_pmc->chws[PMC_UTMI] = hw;
226 parent_names[0] = md_slck_name;
227 parent_names[1] = "mainck";
228 parent_names[2] = "pllack";
229 hw = at91_clk_register_master(regmap, "masterck", 3, parent_names,
230 &sam9x60_master_layout,
231 &mck_characteristics);
235 sam9x60_pmc->chws[PMC_MCK] = hw;
237 parent_names[0] = "pllack";
238 parent_names[1] = "upllck";
239 parent_names[2] = "main_osc";
240 hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
244 parent_names[0] = md_slck_name;
245 parent_names[1] = td_slck_name;
246 parent_names[2] = "mainck";
247 parent_names[3] = "masterck";
248 parent_names[4] = "pllack";
249 parent_names[5] = "upllck";
250 for (i = 0; i < 8; i++) {
253 snprintf(name, sizeof(name), "prog%d", i);
255 hw = at91_clk_register_programmable(regmap, name,
257 &sam9x60_programmable_layout);
261 sam9x60_pmc->pchws[i] = hw;
264 for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
265 hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,
266 sam9x60_systemck[i].p,
267 sam9x60_systemck[i].id);
271 sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw;
274 for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
275 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
277 sam9x60_periphck[i].n,
279 sam9x60_periphck[i].id,
284 sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw;
287 for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
288 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
298 sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw;
301 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc);
308 /* Some clks are used for a clocksource */
309 CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);