1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
8 #include <linux/clk/at91_pmc.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/syscore_ops.h>
15 #include <asm/proc-fns.h>
17 #include <dt-bindings/clock/at91.h>
21 #define PMC_MAX_IDS 128
22 #define PMC_MAX_PCKS 8
24 int of_at91_get_clk_range(struct device_node *np, const char *propname,
25 struct clk_range *range)
30 ret = of_property_read_u32_index(np, propname, 0, &min);
34 ret = of_property_read_u32_index(np, propname, 1, &max);
45 EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
47 struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data)
49 unsigned int type = clkspec->args[0];
50 unsigned int idx = clkspec->args[1];
51 struct pmc_data *pmc_data = data;
55 if (idx < pmc_data->ncore)
56 return pmc_data->chws[idx];
59 if (idx < pmc_data->nsystem)
60 return pmc_data->shws[idx];
62 case PMC_TYPE_PERIPHERAL:
63 if (idx < pmc_data->nperiph)
64 return pmc_data->phws[idx];
67 if (idx < pmc_data->ngck)
68 return pmc_data->ghws[idx];
74 pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx);
76 return ERR_PTR(-EINVAL);
79 struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
80 unsigned int nperiph, unsigned int ngck)
82 unsigned int num_clks = ncore + nsystem + nperiph + ngck;
83 struct pmc_data *pmc_data;
85 pmc_data = kzalloc(struct_size(pmc_data, hwtable, num_clks),
90 pmc_data->ncore = ncore;
91 pmc_data->chws = pmc_data->hwtable;
93 pmc_data->nsystem = nsystem;
94 pmc_data->shws = pmc_data->chws + ncore;
96 pmc_data->nperiph = nperiph;
97 pmc_data->phws = pmc_data->shws + nsystem;
99 pmc_data->ngck = ngck;
100 pmc_data->ghws = pmc_data->phws + nperiph;
106 static struct regmap *pmcreg;
108 static u8 registered_ids[PMC_MAX_IDS];
109 static u8 registered_pcks[PMC_MAX_PCKS];
123 u32 pcr[PMC_MAX_IDS];
126 u32 pckr[PMC_MAX_PCKS];
130 * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
131 * without alteration in the table, and 0 is for unused clocks.
133 void pmc_register_id(u8 id)
137 for (i = 0; i < PMC_MAX_IDS; i++) {
138 if (registered_ids[i] == 0) {
139 registered_ids[i] = id;
142 if (registered_ids[i] == id)
148 * As Programmable Clock 0 is valid on AT91 chips, there is an offset
149 * of 1 between the stored value and the real clock ID.
151 void pmc_register_pck(u8 pck)
155 for (i = 0; i < PMC_MAX_PCKS; i++) {
156 if (registered_pcks[i] == 0) {
157 registered_pcks[i] = pck + 1;
160 if (registered_pcks[i] == (pck + 1))
165 static int pmc_suspend(void)
170 regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
171 regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
172 regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
173 regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
174 regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
175 regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
176 regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
177 regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
178 regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
179 regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
181 for (i = 0; registered_ids[i]; i++) {
182 regmap_write(pmcreg, AT91_PMC_PCR,
183 (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
184 regmap_read(pmcreg, AT91_PMC_PCR,
185 &pmc_cache.pcr[registered_ids[i]]);
187 for (i = 0; registered_pcks[i]; i++) {
188 num = registered_pcks[i] - 1;
189 regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
195 static bool pmc_ready(unsigned int mask)
199 regmap_read(pmcreg, AT91_PMC_SR, &status);
201 return ((status & mask) == mask) ? 1 : 0;
204 static void pmc_resume(void)
209 u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
211 regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
212 if (pmc_cache.mckr != tmp)
213 pr_warn("MCKR was not configured properly by the firmware\n");
214 regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
215 if (pmc_cache.pllar != tmp)
216 pr_warn("PLLAR was not configured properly by the firmware\n");
218 regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
219 regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
220 regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
221 regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
222 regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
223 regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
224 regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
225 regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
227 for (i = 0; registered_ids[i]; i++) {
228 regmap_write(pmcreg, AT91_PMC_PCR,
229 pmc_cache.pcr[registered_ids[i]] |
232 for (i = 0; registered_pcks[i]; i++) {
233 num = registered_pcks[i] - 1;
234 regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
237 if (pmc_cache.uckr & AT91_PMC_UPLLEN)
238 mask |= AT91_PMC_LOCKU;
240 while (!pmc_ready(mask))
244 static struct syscore_ops pmc_syscore_ops = {
245 .suspend = pmc_suspend,
246 .resume = pmc_resume,
249 static const struct of_device_id sama5d2_pmc_dt_ids[] = {
250 { .compatible = "atmel,sama5d2-pmc" },
254 static int __init pmc_register_ops(void)
256 struct device_node *np;
258 np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
262 pmcreg = device_node_to_regmap(np);
265 return PTR_ERR(pmcreg);
267 register_syscore_ops(&pmc_syscore_ops);
271 /* This has to happen before arch_initcall because of the tcb_clksrc driver */
272 postcore_initcall(pmc_register_ops);