1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
5 #include <linux/mfd/syscon.h>
6 #include <linux/regmap.h>
7 #include <linux/slab.h>
11 #define MASTER_SOURCE_MAX 4
13 #define PERIPHERAL_AT91RM9200 0
14 #define PERIPHERAL_AT91SAM9X5 1
16 #define PERIPHERAL_MAX 64
18 #define PERIPHERAL_ID_MIN 2
20 #define PROG_SOURCE_MAX 5
23 #define SYSTEM_MAX_ID 31
25 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
26 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
29 const char *name = np->name;
30 const char *parent_name;
31 struct regmap *regmap;
33 regmap = syscon_node_to_regmap(of_get_parent(np));
37 parent_name = of_clk_get_parent_name(np, 0);
39 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
43 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
45 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
46 "atmel,sama5d2-clk-audio-pll-frac",
47 of_sama5d2_clk_audio_pll_frac_setup);
49 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
52 const char *name = np->name;
53 const char *parent_name;
54 struct regmap *regmap;
56 regmap = syscon_node_to_regmap(of_get_parent(np));
60 parent_name = of_clk_get_parent_name(np, 0);
62 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
66 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
68 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
69 "atmel,sama5d2-clk-audio-pll-pad",
70 of_sama5d2_clk_audio_pll_pad_setup);
72 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
75 const char *name = np->name;
76 const char *parent_name;
77 struct regmap *regmap;
79 regmap = syscon_node_to_regmap(of_get_parent(np));
83 parent_name = of_clk_get_parent_name(np, 0);
85 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
89 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
91 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
92 "atmel,sama5d2-clk-audio-pll-pmc",
93 of_sama5d2_clk_audio_pll_pmc_setup);
94 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
96 static const struct clk_pcr_layout dt_pcr_layout = {
99 .pid_mask = GENMASK(5, 0),
100 .div_mask = GENMASK(17, 16),
101 .gckcss_mask = GENMASK(10, 8),
104 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK
105 #define GENERATED_SOURCE_MAX 6
107 #define GCK_ID_I2S0 54
108 #define GCK_ID_I2S1 55
109 #define GCK_ID_CLASSD 59
111 static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
117 unsigned int num_parents;
118 const char *parent_names[GENERATED_SOURCE_MAX];
119 struct device_node *gcknp;
120 struct clk_range range = CLK_RANGE(0, 0);
121 struct regmap *regmap;
123 num_parents = of_clk_get_parent_count(np);
124 if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
127 of_clk_parent_fill(np, parent_names, num_parents);
129 num = of_get_child_count(np);
130 if (!num || num > PERIPHERAL_MAX)
133 regmap = syscon_node_to_regmap(of_get_parent(np));
137 for_each_child_of_node(np, gcknp) {
138 bool pll_audio = false;
140 if (of_property_read_u32(gcknp, "reg", &id))
143 if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
146 if (of_property_read_string(np, "clock-output-names", &name))
149 of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
152 if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
153 (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
154 id == GCK_ID_CLASSD))
157 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
158 &dt_pcr_layout, name,
159 parent_names, num_parents,
160 id, pll_audio, &range);
164 of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
167 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
168 of_sama5d2_clk_generated_setup);
169 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
171 #ifdef CONFIG_HAVE_AT91_H32MX
172 static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
175 const char *name = np->name;
176 const char *parent_name;
177 struct regmap *regmap;
179 regmap = syscon_node_to_regmap(of_get_parent(np));
183 parent_name = of_clk_get_parent_name(np, 0);
185 hw = at91_clk_register_h32mx(regmap, name, parent_name);
189 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
191 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
192 of_sama5d4_clk_h32mx_setup);
193 #endif /* CONFIG_HAVE_AT91_H32MX */
195 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
198 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
200 struct regmap *regmap_sfr;
202 const char *parent_names[2];
203 struct device_node *i2s_mux_np;
207 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
208 if (IS_ERR(regmap_sfr))
211 for_each_child_of_node(np, i2s_mux_np) {
212 if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
215 if (bus_id > I2S_BUS_NR)
218 ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
222 hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
223 parent_names, 2, bus_id);
227 of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
230 CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
231 of_sama5d2_clk_i2s_mux_setup);
232 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
234 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
237 const char *name = np->name;
238 const char *parent_name;
239 struct regmap *regmap;
242 of_property_read_string(np, "clock-output-names", &name);
243 bypass = of_property_read_bool(np, "atmel,osc-bypass");
244 parent_name = of_clk_get_parent_name(np, 0);
246 regmap = syscon_node_to_regmap(of_get_parent(np));
250 hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
254 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
256 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
257 of_at91rm9200_clk_main_osc_setup);
259 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
264 const char *name = np->name;
265 struct regmap *regmap;
267 of_property_read_string(np, "clock-output-names", &name);
268 of_property_read_u32(np, "clock-frequency", &frequency);
269 of_property_read_u32(np, "clock-accuracy", &accuracy);
271 regmap = syscon_node_to_regmap(of_get_parent(np));
275 hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
279 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
281 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
282 of_at91sam9x5_clk_main_rc_osc_setup);
284 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
287 const char *parent_name;
288 const char *name = np->name;
289 struct regmap *regmap;
291 parent_name = of_clk_get_parent_name(np, 0);
292 of_property_read_string(np, "clock-output-names", &name);
294 regmap = syscon_node_to_regmap(of_get_parent(np));
298 hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
302 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
304 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
305 of_at91rm9200_clk_main_setup);
307 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
310 const char *parent_names[2];
311 unsigned int num_parents;
312 const char *name = np->name;
313 struct regmap *regmap;
315 num_parents = of_clk_get_parent_count(np);
316 if (num_parents == 0 || num_parents > 2)
319 of_clk_parent_fill(np, parent_names, num_parents);
320 regmap = syscon_node_to_regmap(of_get_parent(np));
324 of_property_read_string(np, "clock-output-names", &name);
326 hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
331 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
333 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
334 of_at91sam9x5_clk_main_setup);
336 static struct clk_master_characteristics * __init
337 of_at91_clk_master_get_characteristics(struct device_node *np)
339 struct clk_master_characteristics *characteristics;
341 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
342 if (!characteristics)
345 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
346 goto out_free_characteristics;
348 of_property_read_u32_array(np, "atmel,clk-divisors",
349 characteristics->divisors, 4);
351 characteristics->have_div3_pres =
352 of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
354 return characteristics;
356 out_free_characteristics:
357 kfree(characteristics);
362 of_at91_clk_master_setup(struct device_node *np,
363 const struct clk_master_layout *layout)
366 unsigned int num_parents;
367 const char *parent_names[MASTER_SOURCE_MAX];
368 const char *name = np->name;
369 struct clk_master_characteristics *characteristics;
370 struct regmap *regmap;
372 num_parents = of_clk_get_parent_count(np);
373 if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
376 of_clk_parent_fill(np, parent_names, num_parents);
378 of_property_read_string(np, "clock-output-names", &name);
380 characteristics = of_at91_clk_master_get_characteristics(np);
381 if (!characteristics)
384 regmap = syscon_node_to_regmap(of_get_parent(np));
388 hw = at91_clk_register_master(regmap, name, num_parents,
389 parent_names, layout,
392 goto out_free_characteristics;
394 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
397 out_free_characteristics:
398 kfree(characteristics);
401 static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
403 of_at91_clk_master_setup(np, &at91rm9200_master_layout);
405 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
406 of_at91rm9200_clk_master_setup);
408 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
410 of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
412 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
413 of_at91sam9x5_clk_master_setup);
416 of_at91_clk_periph_setup(struct device_node *np, u8 type)
421 const char *parent_name;
423 struct device_node *periphclknp;
424 struct regmap *regmap;
426 parent_name = of_clk_get_parent_name(np, 0);
430 num = of_get_child_count(np);
431 if (!num || num > PERIPHERAL_MAX)
434 regmap = syscon_node_to_regmap(of_get_parent(np));
438 for_each_child_of_node(np, periphclknp) {
439 if (of_property_read_u32(periphclknp, "reg", &id))
442 if (id >= PERIPHERAL_MAX)
445 if (of_property_read_string(np, "clock-output-names", &name))
446 name = periphclknp->name;
448 if (type == PERIPHERAL_AT91RM9200) {
449 hw = at91_clk_register_peripheral(regmap, name,
452 struct clk_range range = CLK_RANGE(0, 0);
454 of_at91_get_clk_range(periphclknp,
455 "atmel,clk-output-range",
458 hw = at91_clk_register_sam9x5_peripheral(regmap,
469 of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
473 static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
475 of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
477 CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
478 of_at91rm9200_clk_periph_setup);
480 static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
482 of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
484 CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
485 of_at91sam9x5_clk_periph_setup);
487 static struct clk_pll_characteristics * __init
488 of_at91_clk_pll_get_characteristics(struct device_node *np)
495 struct clk_range input;
496 struct clk_range *output;
499 struct clk_pll_characteristics *characteristics;
501 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
504 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
508 if (num_cells < 2 || num_cells > 4)
511 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
513 num_output = tmp / (sizeof(u32) * num_cells);
515 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
516 if (!characteristics)
519 output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
521 goto out_free_characteristics;
524 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
526 goto out_free_output;
530 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
532 goto out_free_output;
535 for (i = 0; i < num_output; i++) {
536 offset = i * num_cells;
537 if (of_property_read_u32_index(np,
538 "atmel,pll-clk-output-ranges",
540 goto out_free_output;
542 if (of_property_read_u32_index(np,
543 "atmel,pll-clk-output-ranges",
545 goto out_free_output;
551 if (of_property_read_u32_index(np,
552 "atmel,pll-clk-output-ranges",
554 goto out_free_output;
560 if (of_property_read_u32_index(np,
561 "atmel,pll-clk-output-ranges",
563 goto out_free_output;
567 characteristics->input = input;
568 characteristics->num_output = num_output;
569 characteristics->output = output;
570 characteristics->out = out;
571 characteristics->icpll = icpll;
572 return characteristics;
578 out_free_characteristics:
579 kfree(characteristics);
584 of_at91_clk_pll_setup(struct device_node *np,
585 const struct clk_pll_layout *layout)
589 struct regmap *regmap;
590 const char *parent_name;
591 const char *name = np->name;
592 struct clk_pll_characteristics *characteristics;
594 if (of_property_read_u32(np, "reg", &id))
597 parent_name = of_clk_get_parent_name(np, 0);
599 of_property_read_string(np, "clock-output-names", &name);
601 regmap = syscon_node_to_regmap(of_get_parent(np));
605 characteristics = of_at91_clk_pll_get_characteristics(np);
606 if (!characteristics)
609 hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
612 goto out_free_characteristics;
614 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
617 out_free_characteristics:
618 kfree(characteristics);
621 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
623 of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
625 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
626 of_at91rm9200_clk_pll_setup);
628 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
630 of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
632 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
633 of_at91sam9g45_clk_pll_setup);
635 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
637 of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
639 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
640 of_at91sam9g20_clk_pllb_setup);
642 static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
644 of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
646 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
647 of_sama5d3_clk_pll_setup);
650 of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
653 const char *parent_name;
654 const char *name = np->name;
655 struct regmap *regmap;
657 parent_name = of_clk_get_parent_name(np, 0);
659 of_property_read_string(np, "clock-output-names", &name);
661 regmap = syscon_node_to_regmap(of_get_parent(np));
665 hw = at91_clk_register_plldiv(regmap, name, parent_name);
669 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
671 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
672 of_at91sam9x5_clk_plldiv_setup);
675 of_at91_clk_prog_setup(struct device_node *np,
676 const struct clk_programmable_layout *layout)
681 unsigned int num_parents;
682 const char *parent_names[PROG_SOURCE_MAX];
684 struct device_node *progclknp;
685 struct regmap *regmap;
687 num_parents = of_clk_get_parent_count(np);
688 if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
691 of_clk_parent_fill(np, parent_names, num_parents);
693 num = of_get_child_count(np);
694 if (!num || num > (PROG_ID_MAX + 1))
697 regmap = syscon_node_to_regmap(of_get_parent(np));
701 for_each_child_of_node(np, progclknp) {
702 if (of_property_read_u32(progclknp, "reg", &id))
705 if (of_property_read_string(np, "clock-output-names", &name))
706 name = progclknp->name;
708 hw = at91_clk_register_programmable(regmap, name,
709 parent_names, num_parents,
714 of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
718 static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
720 of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
722 CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
723 of_at91rm9200_clk_prog_setup);
725 static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
727 of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
729 CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
730 of_at91sam9g45_clk_prog_setup);
732 static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
734 of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
736 CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
737 of_at91sam9x5_clk_prog_setup);
739 static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
742 const char *parent_names[2];
743 unsigned int num_parents;
744 const char *name = np->name;
745 struct regmap *regmap;
747 num_parents = of_clk_get_parent_count(np);
748 if (num_parents != 2)
751 of_clk_parent_fill(np, parent_names, num_parents);
752 regmap = syscon_node_to_regmap(of_get_parent(np));
756 of_property_read_string(np, "clock-output-names", &name);
758 hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
763 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
765 CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
766 of_at91sam9260_clk_slow_setup);
768 #ifdef CONFIG_HAVE_AT91_SMD
769 #define SMD_SOURCE_MAX 2
771 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
774 unsigned int num_parents;
775 const char *parent_names[SMD_SOURCE_MAX];
776 const char *name = np->name;
777 struct regmap *regmap;
779 num_parents = of_clk_get_parent_count(np);
780 if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
783 of_clk_parent_fill(np, parent_names, num_parents);
785 of_property_read_string(np, "clock-output-names", &name);
787 regmap = syscon_node_to_regmap(of_get_parent(np));
791 hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
796 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
798 CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
799 of_at91sam9x5_clk_smd_setup);
800 #endif /* CONFIG_HAVE_AT91_SMD */
802 static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
808 struct device_node *sysclknp;
809 const char *parent_name;
810 struct regmap *regmap;
812 num = of_get_child_count(np);
813 if (num > (SYSTEM_MAX_ID + 1))
816 regmap = syscon_node_to_regmap(of_get_parent(np));
820 for_each_child_of_node(np, sysclknp) {
821 if (of_property_read_u32(sysclknp, "reg", &id))
824 if (of_property_read_string(np, "clock-output-names", &name))
825 name = sysclknp->name;
827 parent_name = of_clk_get_parent_name(sysclknp, 0);
829 hw = at91_clk_register_system(regmap, name, parent_name, id);
833 of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
836 CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
837 of_at91rm9200_clk_sys_setup);
839 #ifdef CONFIG_HAVE_AT91_USB_CLK
840 #define USB_SOURCE_MAX 2
842 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
845 unsigned int num_parents;
846 const char *parent_names[USB_SOURCE_MAX];
847 const char *name = np->name;
848 struct regmap *regmap;
850 num_parents = of_clk_get_parent_count(np);
851 if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
854 of_clk_parent_fill(np, parent_names, num_parents);
856 of_property_read_string(np, "clock-output-names", &name);
858 regmap = syscon_node_to_regmap(of_get_parent(np));
862 hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
867 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
869 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
870 of_at91sam9x5_clk_usb_setup);
872 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
875 const char *parent_name;
876 const char *name = np->name;
877 struct regmap *regmap;
879 parent_name = of_clk_get_parent_name(np, 0);
883 of_property_read_string(np, "clock-output-names", &name);
885 regmap = syscon_node_to_regmap(of_get_parent(np));
889 hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
893 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
895 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
896 of_at91sam9n12_clk_usb_setup);
898 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
901 const char *parent_name;
902 const char *name = np->name;
903 u32 divisors[4] = {0, 0, 0, 0};
904 struct regmap *regmap;
906 parent_name = of_clk_get_parent_name(np, 0);
910 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
914 of_property_read_string(np, "clock-output-names", &name);
916 regmap = syscon_node_to_regmap(of_get_parent(np));
919 hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
923 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
925 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
926 of_at91rm9200_clk_usb_setup);
927 #endif /* CONFIG_HAVE_AT91_USB_CLK */
929 #ifdef CONFIG_HAVE_AT91_UTMI
930 static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
933 const char *parent_name;
934 const char *name = np->name;
935 struct regmap *regmap_pmc, *regmap_sfr;
937 parent_name = of_clk_get_parent_name(np, 0);
939 of_property_read_string(np, "clock-output-names", &name);
941 regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
942 if (IS_ERR(regmap_pmc))
946 * If the device supports different mainck rates, this value has to be
947 * set in the UTMI Clock Trimming register.
948 * - 9x5: mainck supports several rates but it is indicated that a
949 * 12 MHz is needed in case of USB.
950 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
951 * the FREQ field of the UTMI Clock Trimming register is mandatory.
952 * - sama5d4: mainck is at 12 MHz.
954 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
956 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
957 if (IS_ERR(regmap_sfr)) {
958 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
959 if (IS_ERR(regmap_sfr))
963 hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
967 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
969 CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
970 of_at91sam9x5_clk_utmi_setup);
971 #endif /* CONFIG_HAVE_AT91_UTMI */