2 * drivers/clk/at91/clk-slow.c
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/clk-provider.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk/at91_pmc.h>
16 #include <linux/delay.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/sched.h>
24 #include <linux/wait.h>
29 #define SLOW_CLOCK_FREQ 32768
30 #define SLOWCK_SW_CYCLES 5
31 #define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
34 #define AT91_SCKC_CR 0x00
35 #define AT91_SCKC_RCEN (1 << 0)
36 #define AT91_SCKC_OSC32EN (1 << 1)
37 #define AT91_SCKC_OSC32BYP (1 << 2)
38 #define AT91_SCKC_OSCSEL (1 << 3)
43 unsigned long startup_usec;
46 #define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
48 struct clk_slow_rc_osc {
51 unsigned long frequency;
52 unsigned long accuracy;
53 unsigned long startup_usec;
56 #define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw)
58 struct clk_sam9260_slow {
63 #define to_clk_sam9260_slow(hw) container_of(hw, struct clk_sam9260_slow, hw)
65 struct clk_sam9x5_slow {
71 #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
74 static int clk_slow_osc_prepare(struct clk_hw *hw)
76 struct clk_slow_osc *osc = to_clk_slow_osc(hw);
77 void __iomem *sckcr = osc->sckcr;
78 u32 tmp = readl(sckcr);
80 if (tmp & AT91_SCKC_OSC32BYP)
83 writel(tmp | AT91_SCKC_OSC32EN, sckcr);
85 usleep_range(osc->startup_usec, osc->startup_usec + 1);
90 static void clk_slow_osc_unprepare(struct clk_hw *hw)
92 struct clk_slow_osc *osc = to_clk_slow_osc(hw);
93 void __iomem *sckcr = osc->sckcr;
94 u32 tmp = readl(sckcr);
96 if (tmp & AT91_SCKC_OSC32BYP)
99 writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);
102 static int clk_slow_osc_is_prepared(struct clk_hw *hw)
104 struct clk_slow_osc *osc = to_clk_slow_osc(hw);
105 void __iomem *sckcr = osc->sckcr;
106 u32 tmp = readl(sckcr);
108 if (tmp & AT91_SCKC_OSC32BYP)
111 return !!(tmp & AT91_SCKC_OSC32EN);
114 static const struct clk_ops slow_osc_ops = {
115 .prepare = clk_slow_osc_prepare,
116 .unprepare = clk_slow_osc_unprepare,
117 .is_prepared = clk_slow_osc_is_prepared,
120 static struct clk * __init
121 at91_clk_register_slow_osc(void __iomem *sckcr,
123 const char *parent_name,
124 unsigned long startup,
127 struct clk_slow_osc *osc;
128 struct clk *clk = NULL;
129 struct clk_init_data init;
131 if (!sckcr || !name || !parent_name)
132 return ERR_PTR(-EINVAL);
134 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
136 return ERR_PTR(-ENOMEM);
139 init.ops = &slow_osc_ops;
140 init.parent_names = &parent_name;
141 init.num_parents = 1;
142 init.flags = CLK_IGNORE_UNUSED;
144 osc->hw.init = &init;
146 osc->startup_usec = startup;
149 writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,
152 clk = clk_register(NULL, &osc->hw);
159 void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np,
163 const char *parent_name;
164 const char *name = np->name;
168 parent_name = of_clk_get_parent_name(np, 0);
169 of_property_read_string(np, "clock-output-names", &name);
170 of_property_read_u32(np, "atmel,startup-time-usec", &startup);
171 bypass = of_property_read_bool(np, "atmel,osc-bypass");
173 clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup,
178 of_clk_add_provider(np, of_clk_src_simple_get, clk);
181 static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
182 unsigned long parent_rate)
184 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
186 return osc->frequency;
189 static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw,
190 unsigned long parent_acc)
192 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
194 return osc->accuracy;
197 static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
199 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
200 void __iomem *sckcr = osc->sckcr;
202 writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);
204 usleep_range(osc->startup_usec, osc->startup_usec + 1);
209 static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
211 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
212 void __iomem *sckcr = osc->sckcr;
214 writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);
217 static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
219 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
221 return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);
224 static const struct clk_ops slow_rc_osc_ops = {
225 .prepare = clk_slow_rc_osc_prepare,
226 .unprepare = clk_slow_rc_osc_unprepare,
227 .is_prepared = clk_slow_rc_osc_is_prepared,
228 .recalc_rate = clk_slow_rc_osc_recalc_rate,
229 .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy,
232 static struct clk * __init
233 at91_clk_register_slow_rc_osc(void __iomem *sckcr,
235 unsigned long frequency,
236 unsigned long accuracy,
237 unsigned long startup)
239 struct clk_slow_rc_osc *osc;
240 struct clk *clk = NULL;
241 struct clk_init_data init;
244 return ERR_PTR(-EINVAL);
246 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
248 return ERR_PTR(-ENOMEM);
251 init.ops = &slow_rc_osc_ops;
252 init.parent_names = NULL;
253 init.num_parents = 0;
254 init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
256 osc->hw.init = &init;
258 osc->frequency = frequency;
259 osc->accuracy = accuracy;
260 osc->startup_usec = startup;
262 clk = clk_register(NULL, &osc->hw);
269 void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np,
276 const char *name = np->name;
278 of_property_read_string(np, "clock-output-names", &name);
279 of_property_read_u32(np, "clock-frequency", &frequency);
280 of_property_read_u32(np, "clock-accuracy", &accuracy);
281 of_property_read_u32(np, "atmel,startup-time-usec", &startup);
283 clk = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy,
288 of_clk_add_provider(np, of_clk_src_simple_get, clk);
291 static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
293 struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
294 void __iomem *sckcr = slowck->sckcr;
302 if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||
303 (index && (tmp & AT91_SCKC_OSCSEL)))
307 tmp |= AT91_SCKC_OSCSEL;
309 tmp &= ~AT91_SCKC_OSCSEL;
313 usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
318 static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
320 struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
322 return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);
325 static const struct clk_ops sam9x5_slow_ops = {
326 .set_parent = clk_sam9x5_slow_set_parent,
327 .get_parent = clk_sam9x5_slow_get_parent,
330 static struct clk * __init
331 at91_clk_register_sam9x5_slow(void __iomem *sckcr,
333 const char **parent_names,
336 struct clk_sam9x5_slow *slowck;
337 struct clk *clk = NULL;
338 struct clk_init_data init;
340 if (!sckcr || !name || !parent_names || !num_parents)
341 return ERR_PTR(-EINVAL);
343 slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
345 return ERR_PTR(-ENOMEM);
348 init.ops = &sam9x5_slow_ops;
349 init.parent_names = parent_names;
350 init.num_parents = num_parents;
353 slowck->hw.init = &init;
354 slowck->sckcr = sckcr;
355 slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);
357 clk = clk_register(NULL, &slowck->hw);
364 void __init of_at91sam9x5_clk_slow_setup(struct device_node *np,
368 const char *parent_names[2];
370 const char *name = np->name;
373 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
374 if (num_parents <= 0 || num_parents > 2)
377 for (i = 0; i < num_parents; ++i) {
378 parent_names[i] = of_clk_get_parent_name(np, i);
379 if (!parent_names[i])
383 of_property_read_string(np, "clock-output-names", &name);
385 clk = at91_clk_register_sam9x5_slow(sckcr, name, parent_names,
390 of_clk_add_provider(np, of_clk_src_simple_get, clk);
393 static u8 clk_sam9260_slow_get_parent(struct clk_hw *hw)
395 struct clk_sam9260_slow *slowck = to_clk_sam9260_slow(hw);
397 return !!(pmc_read(slowck->pmc, AT91_PMC_SR) & AT91_PMC_OSCSEL);
400 static const struct clk_ops sam9260_slow_ops = {
401 .get_parent = clk_sam9260_slow_get_parent,
404 static struct clk * __init
405 at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
407 const char **parent_names,
410 struct clk_sam9260_slow *slowck;
411 struct clk *clk = NULL;
412 struct clk_init_data init;
415 return ERR_PTR(-EINVAL);
417 if (!parent_names || !num_parents)
418 return ERR_PTR(-EINVAL);
420 slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
422 return ERR_PTR(-ENOMEM);
425 init.ops = &sam9260_slow_ops;
426 init.parent_names = parent_names;
427 init.num_parents = num_parents;
430 slowck->hw.init = &init;
433 clk = clk_register(NULL, &slowck->hw);
440 void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
441 struct at91_pmc *pmc)
444 const char *parent_names[2];
446 const char *name = np->name;
449 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
450 if (num_parents != 2)
453 for (i = 0; i < num_parents; ++i) {
454 parent_names[i] = of_clk_get_parent_name(np, i);
455 if (!parent_names[i])
459 of_property_read_string(np, "clock-output-names", &name);
461 clk = at91_clk_register_sam9260_slow(pmc, name, parent_names,
466 of_clk_add_provider(np, of_clk_src_simple_get, clk);