1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Microchip Technology Inc.
7 #include <linux/bitfield.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
10 #include <linux/clk/at91_pmc.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/regmap.h>
17 #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
18 #define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
20 #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
22 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
28 struct regmap *regmap;
30 const struct clk_pll_characteristics *characteristics;
37 #define to_sam9x60_pll(hw) container_of(hw, struct sam9x60_pll, hw)
39 static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
43 regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
45 return !!(status & BIT(id));
48 static int sam9x60_pll_prepare(struct clk_hw *hw)
50 struct sam9x60_pll *pll = to_sam9x60_pll(hw);
51 struct regmap *regmap = pll->regmap;
57 spin_lock_irqsave(pll->lock, flags);
58 regmap_write(regmap, AT91_PMC_PLL_UPDT, pll->id);
60 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
61 div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
63 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
64 mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
66 if (sam9x60_pll_ready(regmap, pll->id) &&
67 (div == pll->div && mul == pll->mul)) {
68 spin_unlock_irqrestore(pll->lock, flags);
72 /* Recommended value for AT91_PMC_PLL_ACR */
73 if (pll->characteristics->upll)
74 val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
76 val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
77 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
79 regmap_write(regmap, AT91_PMC_PLL_CTRL1,
80 FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
82 if (pll->characteristics->upll) {
83 /* Enable the UTMI internal bandgap */
84 val |= AT91_PMC_PLL_ACR_UTMIBG;
85 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
89 /* Enable the UTMI internal regulator */
90 val |= AT91_PMC_PLL_ACR_UTMIVR;
91 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
96 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
97 AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
99 regmap_write(regmap, AT91_PMC_PLL_CTRL0,
100 AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL |
101 AT91_PMC_PLL_CTRL0_ENPLLCK | pll->div);
103 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
104 AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
106 while (!sam9x60_pll_ready(regmap, pll->id))
109 spin_unlock_irqrestore(pll->lock, flags);
114 static int sam9x60_pll_is_prepared(struct clk_hw *hw)
116 struct sam9x60_pll *pll = to_sam9x60_pll(hw);
118 return sam9x60_pll_ready(pll->regmap, pll->id);
121 static void sam9x60_pll_unprepare(struct clk_hw *hw)
123 struct sam9x60_pll *pll = to_sam9x60_pll(hw);
126 spin_lock_irqsave(pll->lock, flags);
128 regmap_write(pll->regmap, AT91_PMC_PLL_UPDT, pll->id);
130 regmap_update_bits(pll->regmap, AT91_PMC_PLL_CTRL0,
131 AT91_PMC_PLL_CTRL0_ENPLLCK, 0);
133 regmap_update_bits(pll->regmap, AT91_PMC_PLL_UPDT,
134 AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
136 regmap_update_bits(pll->regmap, AT91_PMC_PLL_CTRL0,
137 AT91_PMC_PLL_CTRL0_ENPLL, 0);
139 if (pll->characteristics->upll)
140 regmap_update_bits(pll->regmap, AT91_PMC_PLL_ACR,
141 AT91_PMC_PLL_ACR_UTMIBG |
142 AT91_PMC_PLL_ACR_UTMIVR, 0);
144 regmap_update_bits(pll->regmap, AT91_PMC_PLL_UPDT,
145 AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
147 spin_unlock_irqrestore(pll->lock, flags);
150 static unsigned long sam9x60_pll_recalc_rate(struct clk_hw *hw,
151 unsigned long parent_rate)
153 struct sam9x60_pll *pll = to_sam9x60_pll(hw);
155 return (parent_rate * (pll->mul + 1)) / (pll->div + 1);
158 static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
160 unsigned long parent_rate,
163 const struct clk_pll_characteristics *characteristics =
164 pll->characteristics;
165 unsigned long bestremainder = ULONG_MAX;
166 unsigned long maxdiv, mindiv, tmpdiv;
167 long bestrate = -ERANGE;
168 unsigned long bestdiv = 0;
169 unsigned long bestmul = 0;
170 unsigned long bestfrac = 0;
172 if (rate < characteristics->output[0].min ||
173 rate > characteristics->output[0].max)
176 if (!pll->characteristics->upll) {
177 mindiv = parent_rate / rate;
181 maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX, rate);
182 if (maxdiv > PLL_DIV_MAX)
183 maxdiv = PLL_DIV_MAX;
185 mindiv = maxdiv = UPLL_DIV;
188 for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
189 unsigned long remainder;
190 unsigned long tmprate;
191 unsigned long tmpmul;
192 unsigned long tmpfrac = 0;
195 * Calculate the multiplier associated with the current
196 * divider that provide the closest rate to the requested one.
198 tmpmul = mult_frac(rate, tmpdiv, parent_rate);
199 tmprate = mult_frac(parent_rate, tmpmul, tmpdiv);
200 remainder = rate - tmprate;
203 tmpfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * tmpdiv * (1 << 22),
206 tmprate += DIV_ROUND_CLOSEST_ULL((u64)tmpfrac * parent_rate,
210 remainder = tmprate - rate;
212 remainder = rate - tmprate;
216 * Compare the remainder with the best remainder found until
217 * now and elect a new best multiplier/divider pair if the
218 * current remainder is smaller than the best one.
220 if (remainder < bestremainder) {
221 bestremainder = remainder;
228 /* We've found a perfect match! */
233 /* Check if bestrate is a valid output rate */
234 if (bestrate < characteristics->output[0].min &&
235 bestrate > characteristics->output[0].max)
239 pll->div = bestdiv - 1;
240 pll->mul = bestmul - 1;
241 pll->frac = bestfrac;
247 static long sam9x60_pll_round_rate(struct clk_hw *hw, unsigned long rate,
248 unsigned long *parent_rate)
250 struct sam9x60_pll *pll = to_sam9x60_pll(hw);
252 return sam9x60_pll_get_best_div_mul(pll, rate, *parent_rate, false);
255 static int sam9x60_pll_set_rate(struct clk_hw *hw, unsigned long rate,
256 unsigned long parent_rate)
258 struct sam9x60_pll *pll = to_sam9x60_pll(hw);
260 return sam9x60_pll_get_best_div_mul(pll, rate, parent_rate, true);
263 static const struct clk_ops pll_ops = {
264 .prepare = sam9x60_pll_prepare,
265 .unprepare = sam9x60_pll_unprepare,
266 .is_prepared = sam9x60_pll_is_prepared,
267 .recalc_rate = sam9x60_pll_recalc_rate,
268 .round_rate = sam9x60_pll_round_rate,
269 .set_rate = sam9x60_pll_set_rate,
272 struct clk_hw * __init
273 sam9x60_clk_register_pll(struct regmap *regmap, spinlock_t *lock,
274 const char *name, const char *parent_name, u8 id,
275 const struct clk_pll_characteristics *characteristics)
277 struct sam9x60_pll *pll;
279 struct clk_init_data init;
284 return ERR_PTR(-EINVAL);
286 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
288 return ERR_PTR(-ENOMEM);
292 init.parent_names = &parent_name;
293 init.num_parents = 1;
294 init.flags = CLK_SET_RATE_GATE;
297 pll->hw.init = &init;
298 pll->characteristics = characteristics;
299 pll->regmap = regmap;
302 regmap_write(regmap, AT91_PMC_PLL_UPDT, id);
303 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &pllr);
304 pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr);
305 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &pllr);
306 pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr);
309 ret = clk_hw_register(NULL, hw);