1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Microchip Technology Inc.
7 #include <linux/bitfield.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
10 #include <linux/clk/at91_pmc.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/regmap.h>
17 #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
18 #define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
19 #define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
21 #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
23 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
25 #define FCORE_MIN (600000000)
26 #define FCORE_MAX (1200000000)
30 struct sam9x60_pll_core {
31 struct regmap *regmap;
33 const struct clk_pll_characteristics *characteristics;
34 const struct clk_pll_layout *layout;
40 struct sam9x60_pll_core core;
46 struct sam9x60_pll_core core;
50 #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
51 #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
52 #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
54 static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
58 regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
60 return !!(status & BIT(id));
63 static bool sam9x60_frac_pll_ready(struct regmap *regmap, u8 id)
65 return sam9x60_pll_ready(regmap, id);
68 static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
69 unsigned long parent_rate)
71 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
72 struct sam9x60_frac *frac = to_sam9x60_frac(core);
74 return (parent_rate * (frac->mul + 1) +
75 ((u64)parent_rate * frac->frac >> 22));
78 static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
80 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
81 struct sam9x60_frac *frac = to_sam9x60_frac(core);
82 struct regmap *regmap = core->regmap;
83 unsigned int val, cfrac, cmul;
86 spin_lock_irqsave(core->lock, flags);
88 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
89 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
90 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
91 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
92 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
94 if (sam9x60_frac_pll_ready(regmap, core->id) &&
95 (cmul == frac->mul && cfrac == frac->frac))
98 /* Recommended value for PMC_PLL_ACR */
99 if (core->characteristics->upll)
100 val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
102 val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
103 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
105 regmap_write(regmap, AT91_PMC_PLL_CTRL1,
106 (frac->mul << core->layout->mul_shift) |
107 (frac->frac << core->layout->frac_shift));
109 if (core->characteristics->upll) {
110 /* Enable the UTMI internal bandgap */
111 val |= AT91_PMC_PLL_ACR_UTMIBG;
112 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
116 /* Enable the UTMI internal regulator */
117 val |= AT91_PMC_PLL_ACR_UTMIVR;
118 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
123 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
124 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
125 AT91_PMC_PLL_UPDT_UPDATE | core->id);
127 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
128 AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
129 AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
131 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
132 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
133 AT91_PMC_PLL_UPDT_UPDATE | core->id);
135 while (!sam9x60_pll_ready(regmap, core->id))
139 spin_unlock_irqrestore(core->lock, flags);
144 static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
146 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
147 struct regmap *regmap = core->regmap;
150 spin_lock_irqsave(core->lock, flags);
152 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
153 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
155 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
157 if (core->characteristics->upll)
158 regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
159 AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
161 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
162 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
163 AT91_PMC_PLL_UPDT_UPDATE | core->id);
165 spin_unlock_irqrestore(core->lock, flags);
168 static int sam9x60_frac_pll_is_prepared(struct clk_hw *hw)
170 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
172 return sam9x60_pll_ready(core->regmap, core->id);
175 static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
177 unsigned long parent_rate,
180 struct sam9x60_frac *frac = to_sam9x60_frac(core);
181 unsigned long tmprate, remainder;
182 unsigned long nmul = 0;
183 unsigned long nfrac = 0;
185 if (rate < FCORE_MIN || rate > FCORE_MAX)
189 * Calculate the multiplier associated with the current
190 * divider that provide the closest rate to the requested one.
192 nmul = mult_frac(rate, 1, parent_rate);
193 tmprate = mult_frac(parent_rate, nmul, 1);
194 remainder = rate - tmprate;
197 nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22),
200 tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate,
204 /* Check if resulted rate is a valid. */
205 if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
209 frac->mul = nmul - 1;
216 static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate,
217 unsigned long *parent_rate)
219 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
221 return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);
224 static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long parent_rate)
227 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
229 return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
232 static const struct clk_ops sam9x60_frac_pll_ops = {
233 .prepare = sam9x60_frac_pll_prepare,
234 .unprepare = sam9x60_frac_pll_unprepare,
235 .is_prepared = sam9x60_frac_pll_is_prepared,
236 .recalc_rate = sam9x60_frac_pll_recalc_rate,
237 .round_rate = sam9x60_frac_pll_round_rate,
238 .set_rate = sam9x60_frac_pll_set_rate,
241 static int sam9x60_div_pll_prepare(struct clk_hw *hw)
243 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
244 struct sam9x60_div *div = to_sam9x60_div(core);
245 struct regmap *regmap = core->regmap;
247 unsigned int val, cdiv;
249 spin_lock_irqsave(core->lock, flags);
250 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
251 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
252 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
253 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
255 /* Stop if enabled an nothing changed. */
256 if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
259 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
260 core->layout->div_mask | core->layout->endiv_mask,
261 (div->div << core->layout->div_shift) |
262 (1 << core->layout->endiv_shift));
264 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
265 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
266 AT91_PMC_PLL_UPDT_UPDATE | core->id);
268 while (!sam9x60_pll_ready(regmap, core->id))
272 spin_unlock_irqrestore(core->lock, flags);
277 static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
279 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
280 struct regmap *regmap = core->regmap;
283 spin_lock_irqsave(core->lock, flags);
285 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
286 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
288 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
289 core->layout->endiv_mask, 0);
291 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
292 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
293 AT91_PMC_PLL_UPDT_UPDATE | core->id);
295 spin_unlock_irqrestore(core->lock, flags);
298 static int sam9x60_div_pll_is_prepared(struct clk_hw *hw)
300 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
301 struct regmap *regmap = core->regmap;
305 spin_lock_irqsave(core->lock, flags);
307 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
308 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
309 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
311 spin_unlock_irqrestore(core->lock, flags);
313 return !!(val & core->layout->endiv_mask);
316 static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
317 unsigned long parent_rate)
319 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
320 struct sam9x60_div *div = to_sam9x60_div(core);
322 return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
325 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
326 unsigned long *parent_rate,
329 const struct clk_pll_characteristics *characteristics =
330 core->characteristics;
331 struct clk_hw *parent = clk_hw_get_parent(&core->hw);
332 unsigned long tmp_rate, tmp_parent_rate, tmp_diff;
333 long best_diff = -1, best_rate = -EINVAL;
339 if (rate < characteristics->output[0].min ||
340 rate > characteristics->output[0].max)
343 for (divid = 1; divid < core->layout->div_mask; divid++) {
344 tmp_parent_rate = clk_hw_round_rate(parent, rate * divid);
345 if (!tmp_parent_rate)
348 tmp_rate = DIV_ROUND_CLOSEST_ULL(tmp_parent_rate, divid);
349 tmp_diff = abs(rate - tmp_rate);
351 if (best_diff < 0 || best_diff > tmp_diff) {
352 *parent_rate = tmp_parent_rate;
353 best_rate = tmp_rate;
354 best_diff = tmp_diff;
362 if (best_rate < characteristics->output[0].min ||
363 best_rate > characteristics->output[0].max)
369 static long sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate,
370 unsigned long *parent_rate)
372 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
374 return sam9x60_div_pll_compute_div(core, parent_rate, rate);
377 static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate,
378 unsigned long parent_rate)
380 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
381 struct sam9x60_div *div = to_sam9x60_div(core);
383 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
388 static const struct clk_ops sam9x60_div_pll_ops = {
389 .prepare = sam9x60_div_pll_prepare,
390 .unprepare = sam9x60_div_pll_unprepare,
391 .is_prepared = sam9x60_div_pll_is_prepared,
392 .recalc_rate = sam9x60_div_pll_recalc_rate,
393 .round_rate = sam9x60_div_pll_round_rate,
394 .set_rate = sam9x60_div_pll_set_rate,
397 struct clk_hw * __init
398 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
399 const char *name, const char *parent_name,
400 struct clk_hw *parent_hw, u8 id,
401 const struct clk_pll_characteristics *characteristics,
402 const struct clk_pll_layout *layout, bool critical)
404 struct sam9x60_frac *frac;
406 struct clk_init_data init;
407 unsigned long parent_rate, flags;
411 if (id > PLL_MAX_ID || !lock || !parent_hw)
412 return ERR_PTR(-EINVAL);
414 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
416 return ERR_PTR(-ENOMEM);
419 init.parent_names = &parent_name;
420 init.num_parents = 1;
421 init.ops = &sam9x60_frac_pll_ops;
422 init.flags = CLK_SET_RATE_GATE;
424 init.flags |= CLK_IS_CRITICAL;
427 frac->core.hw.init = &init;
428 frac->core.characteristics = characteristics;
429 frac->core.layout = layout;
430 frac->core.regmap = regmap;
431 frac->core.lock = lock;
433 spin_lock_irqsave(frac->core.lock, flags);
434 if (sam9x60_pll_ready(regmap, id)) {
435 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
436 AT91_PMC_PLL_UPDT_ID_MSK, id);
437 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
438 frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
439 frac->frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
442 * This means the PLL is not setup by bootloaders. In this
443 * case we need to set the minimum rate for it. Otherwise
444 * a clock child of this PLL may be enabled before setting
445 * its rate leading to enabling this PLL with unsupported
446 * rate. This will lead to PLL not being locked at all.
448 parent_rate = clk_hw_get_rate(parent_hw);
450 hw = ERR_PTR(-EINVAL);
454 ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
461 spin_unlock_irqrestore(frac->core.lock, flags);
464 ret = clk_hw_register(NULL, hw);
473 spin_unlock_irqrestore(frac->core.lock, flags);
478 struct clk_hw * __init
479 sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
480 const char *name, const char *parent_name, u8 id,
481 const struct clk_pll_characteristics *characteristics,
482 const struct clk_pll_layout *layout, bool critical)
484 struct sam9x60_div *div;
486 struct clk_init_data init;
491 if (id > PLL_MAX_ID || !lock)
492 return ERR_PTR(-EINVAL);
494 div = kzalloc(sizeof(*div), GFP_KERNEL);
496 return ERR_PTR(-ENOMEM);
499 init.parent_names = &parent_name;
500 init.num_parents = 1;
501 init.ops = &sam9x60_div_pll_ops;
502 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
505 init.flags |= CLK_IS_CRITICAL;
508 div->core.hw.init = &init;
509 div->core.characteristics = characteristics;
510 div->core.layout = layout;
511 div->core.regmap = regmap;
512 div->core.lock = lock;
514 spin_lock_irqsave(div->core.lock, flags);
516 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
517 AT91_PMC_PLL_UPDT_ID_MSK, id);
518 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
519 div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
521 spin_unlock_irqrestore(div->core.lock, flags);
524 ret = clk_hw_register(NULL, hw);