drivers/clk/at91/clk-sam9x60-pll.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2019 Microchip Technology Inc.
   4  *
   5  */
   6
   7 #include <linux/bitfield.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/clkdev.h>
  10 #include <linux/clk/at91_pmc.h>
  11 #include <linux/of.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/regmap.h>
  14
  15 #include "pmc.h"
  16
  17 #define PMC_PLL_CTRL0_DIV_MSK   GENMASK(7, 0)
  18 #define PMC_PLL_CTRL1_MUL_MSK   GENMASK(31, 24)
  19 #define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
  20
  21 #define PLL_DIV_MAX             (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
  22 #define UPLL_DIV                2
  23 #define PLL_MUL_MAX             (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
  24
  25 #define FCORE_MIN               (600000000)
  26 #define FCORE_MAX               (1200000000)
  27
  28 #define PLL_MAX_ID              7
  29
  30 struct sam9x60_pll_core {
  31         struct regmap *regmap;
  32         spinlock_t *lock;
  33         const struct clk_pll_characteristics *characteristics;
  34         const struct clk_pll_layout *layout;
  35         struct clk_hw hw;
  36         u8 id;
  37 };
  38
  39 struct sam9x60_frac {
  40         struct sam9x60_pll_core core;
  41         u32 frac;
  42         u16 mul;
  43 };
  44
  45 struct sam9x60_div {
  46         struct sam9x60_pll_core core;
  47         u8 div;
  48 };
  49
  50 #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
  51 #define to_sam9x60_frac(core)   container_of(core, struct sam9x60_frac, core)
  52 #define to_sam9x60_div(core)    container_of(core, struct sam9x60_div, core)
  53
  54 static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
  55 {
  56         unsigned int status;
  57
  58         regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
  59
  60         return !!(status & BIT(id));
  61 }
  62
  63 static bool sam9x60_frac_pll_ready(struct regmap *regmap, u8 id)
  64 {
  65         return sam9x60_pll_ready(regmap, id);
  66 }
  67
  68 static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
  69                                                   unsigned long parent_rate)
  70 {
  71         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
  72         struct sam9x60_frac *frac = to_sam9x60_frac(core);
  73
  74         return (parent_rate * (frac->mul + 1) +
  75                 ((u64)parent_rate * frac->frac >> 22));
  76 }
  77
  78 static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
  79 {
  80         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
  81         struct sam9x60_frac *frac = to_sam9x60_frac(core);
  82         struct regmap *regmap = core->regmap;
  83         unsigned int val, cfrac, cmul;
  84         unsigned long flags;
  85
  86         spin_lock_irqsave(core->lock, flags);
  87
  88         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
  89                            AT91_PMC_PLL_UPDT_ID_MSK, core->id);
  90         regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
  91         cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
  92         cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
  93
  94         if (sam9x60_frac_pll_ready(regmap, core->id) &&
  95             (cmul == frac->mul && cfrac == frac->frac))
  96                 goto unlock;
  97
  98         /* Recommended value for PMC_PLL_ACR */
  99         if (core->characteristics->upll)
 100                 val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
 101         else
 102                 val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
 103         regmap_write(regmap, AT91_PMC_PLL_ACR, val);
 104
 105         regmap_write(regmap, AT91_PMC_PLL_CTRL1,
 106                      (frac->mul << core->layout->mul_shift) |
 107                      (frac->frac << core->layout->frac_shift));
 108
 109         if (core->characteristics->upll) {
 110                 /* Enable the UTMI internal bandgap */
 111                 val |= AT91_PMC_PLL_ACR_UTMIBG;
 112                 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
 113
 114                 udelay(10);
 115
 116                 /* Enable the UTMI internal regulator */
 117                 val |= AT91_PMC_PLL_ACR_UTMIVR;
 118                 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
 119
 120                 udelay(10);
 121         }
 122
 123         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 124                            AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 125                            AT91_PMC_PLL_UPDT_UPDATE | core->id);
 126
 127         regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 128                            AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
 129                            AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
 130
 131         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 132                            AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 133                            AT91_PMC_PLL_UPDT_UPDATE | core->id);
 134
 135         while (!sam9x60_pll_ready(regmap, core->id))
 136                 cpu_relax();
 137
 138 unlock:
 139         spin_unlock_irqrestore(core->lock, flags);
 140
 141         return 0;
 142 }
 143
 144 static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
 145 {
 146         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 147         struct regmap *regmap = core->regmap;
 148         unsigned long flags;
 149
 150         spin_lock_irqsave(core->lock, flags);
 151
 152         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 153                            AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 154
 155         regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
 156
 157         if (core->characteristics->upll)
 158                 regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
 159                                    AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
 160
 161         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 162                            AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 163                            AT91_PMC_PLL_UPDT_UPDATE | core->id);
 164
 165         spin_unlock_irqrestore(core->lock, flags);
 166 }
 167
 168 static int sam9x60_frac_pll_is_prepared(struct clk_hw *hw)
 169 {
 170         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 171
 172         return sam9x60_pll_ready(core->regmap, core->id);
 173 }
 174
 175 static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 176                                               unsigned long rate,
 177                                               unsigned long parent_rate,
 178                                               bool update)
 179 {
 180         struct sam9x60_frac *frac = to_sam9x60_frac(core);
 181         unsigned long tmprate, remainder;
 182         unsigned long nmul = 0;
 183         unsigned long nfrac = 0;
 184
 185         if (rate < FCORE_MIN || rate > FCORE_MAX)
 186                 return -ERANGE;
 187
 188         /*
 189          * Calculate the multiplier associated with the current
 190          * divider that provide the closest rate to the requested one.
 191          */
 192         nmul = mult_frac(rate, 1, parent_rate);
 193         tmprate = mult_frac(parent_rate, nmul, 1);
 194         remainder = rate - tmprate;
 195
 196         if (remainder) {
 197                 nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22),
 198                                               parent_rate);
 199
 200                 tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate,
 201                                                  (1 << 22));
 202         }
 203
 204         /* Check if resulted rate is a valid.  */
 205         if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
 206                 return -ERANGE;
 207
 208         if (update) {
 209                 frac->mul = nmul - 1;
 210                 frac->frac = nfrac;
 211         }
 212
 213         return tmprate;
 214 }
 215
 216 static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 217                                         unsigned long *parent_rate)
 218 {
 219         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 220
 221         return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);
 222 }
 223
 224 static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 225                                      unsigned long parent_rate)
 226 {
 227         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 228
 229         return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
 230 }
 231
 232 static const struct clk_ops sam9x60_frac_pll_ops = {
 233         .prepare = sam9x60_frac_pll_prepare,
 234         .unprepare = sam9x60_frac_pll_unprepare,
 235         .is_prepared = sam9x60_frac_pll_is_prepared,
 236         .recalc_rate = sam9x60_frac_pll_recalc_rate,
 237         .round_rate = sam9x60_frac_pll_round_rate,
 238         .set_rate = sam9x60_frac_pll_set_rate,
 239 };
 240
 241 static int sam9x60_div_pll_prepare(struct clk_hw *hw)
 242 {
 243         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 244         struct sam9x60_div *div = to_sam9x60_div(core);
 245         struct regmap *regmap = core->regmap;
 246         unsigned long flags;
 247         unsigned int val, cdiv;
 248
 249         spin_lock_irqsave(core->lock, flags);
 250         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 251                            AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 252         regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 253         cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
 254
 255         /* Stop if enabled an nothing changed. */
 256         if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
 257                 goto unlock;
 258
 259         regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 260                            core->layout->div_mask | core->layout->endiv_mask,
 261                            (div->div << core->layout->div_shift) |
 262                            (1 << core->layout->endiv_shift));
 263
 264         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 265                            AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 266                            AT91_PMC_PLL_UPDT_UPDATE | core->id);
 267
 268         while (!sam9x60_pll_ready(regmap, core->id))
 269                 cpu_relax();
 270
 271 unlock:
 272         spin_unlock_irqrestore(core->lock, flags);
 273
 274         return 0;
 275 }
 276
 277 static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
 278 {
 279         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 280         struct regmap *regmap = core->regmap;
 281         unsigned long flags;
 282
 283         spin_lock_irqsave(core->lock, flags);
 284
 285         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 286                            AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 287
 288         regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 289                            core->layout->endiv_mask, 0);
 290
 291         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 292                            AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 293                            AT91_PMC_PLL_UPDT_UPDATE | core->id);
 294
 295         spin_unlock_irqrestore(core->lock, flags);
 296 }
 297
 298 static int sam9x60_div_pll_is_prepared(struct clk_hw *hw)
 299 {
 300         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 301         struct regmap *regmap = core->regmap;
 302         unsigned long flags;
 303         unsigned int val;
 304
 305         spin_lock_irqsave(core->lock, flags);
 306
 307         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 308                            AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 309         regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 310
 311         spin_unlock_irqrestore(core->lock, flags);
 312
 313         return !!(val & core->layout->endiv_mask);
 314 }
 315
 316 static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
 317                                                  unsigned long parent_rate)
 318 {
 319         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 320         struct sam9x60_div *div = to_sam9x60_div(core);
 321
 322         return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
 323 }
 324
 325 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
 326                                         unsigned long *parent_rate,
 327                                         unsigned long rate)
 328 {
 329         const struct clk_pll_characteristics *characteristics =
 330                                                         core->characteristics;
 331         struct clk_hw *parent = clk_hw_get_parent(&core->hw);
 332         unsigned long tmp_rate, tmp_parent_rate, tmp_diff;
 333         long best_diff = -1, best_rate = -EINVAL;
 334         u32 divid;
 335
 336         if (!rate)
 337                 return 0;
 338
 339         if (rate < characteristics->output[0].min ||
 340             rate > characteristics->output[0].max)
 341                 return -ERANGE;
 342
 343         for (divid = 1; divid < core->layout->div_mask; divid++) {
 344                 tmp_parent_rate = clk_hw_round_rate(parent, rate * divid);
 345                 if (!tmp_parent_rate)
 346                         continue;
 347
 348                 tmp_rate = DIV_ROUND_CLOSEST_ULL(tmp_parent_rate, divid);
 349                 tmp_diff = abs(rate - tmp_rate);
 350
 351                 if (best_diff < 0 || best_diff > tmp_diff) {
 352                         *parent_rate = tmp_parent_rate;
 353                         best_rate = tmp_rate;
 354                         best_diff = tmp_diff;
 355                 }
 356
 357                 if (!best_diff)
 358                         break;
 359         }
 360
 361         if (best_rate < characteristics->output[0].min ||
 362             best_rate > characteristics->output[0].max)
 363                 return -ERANGE;
 364
 365         return best_rate;
 366 }
 367
 368 static long sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 369                                        unsigned long *parent_rate)
 370 {
 371         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 372
 373         return sam9x60_div_pll_compute_div(core, parent_rate, rate);
 374 }
 375
 376 static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 377                                     unsigned long parent_rate)
 378 {
 379         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 380         struct sam9x60_div *div = to_sam9x60_div(core);
 381
 382         div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
 383
 384         return 0;
 385 }
 386
 387 static const struct clk_ops sam9x60_div_pll_ops = {
 388         .prepare = sam9x60_div_pll_prepare,
 389         .unprepare = sam9x60_div_pll_unprepare,
 390         .is_prepared = sam9x60_div_pll_is_prepared,
 391         .recalc_rate = sam9x60_div_pll_recalc_rate,
 392         .round_rate = sam9x60_div_pll_round_rate,
 393         .set_rate = sam9x60_div_pll_set_rate,
 394 };
 395
 396 struct clk_hw * __init
 397 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 398                               const char *name, const char *parent_name,
 399                               struct clk_hw *parent_hw, u8 id,
 400                               const struct clk_pll_characteristics *characteristics,
 401                               const struct clk_pll_layout *layout, bool critical)
 402 {
 403         struct sam9x60_frac *frac;
 404         struct clk_hw *hw;
 405         struct clk_init_data init;
 406         unsigned long parent_rate, flags;
 407         unsigned int val;
 408         int ret;
 409
 410         if (id > PLL_MAX_ID || !lock || !parent_hw)
 411                 return ERR_PTR(-EINVAL);
 412
 413         frac = kzalloc(sizeof(*frac), GFP_KERNEL);
 414         if (!frac)
 415                 return ERR_PTR(-ENOMEM);
 416
 417         init.name = name;
 418         init.parent_names = &parent_name;
 419         init.num_parents = 1;
 420         init.ops = &sam9x60_frac_pll_ops;
 421         init.flags = CLK_SET_RATE_GATE;
 422         if (critical)
 423                 init.flags |= CLK_IS_CRITICAL;
 424
 425         frac->core.id = id;
 426         frac->core.hw.init = &init;
 427         frac->core.characteristics = characteristics;
 428         frac->core.layout = layout;
 429         frac->core.regmap = regmap;
 430         frac->core.lock = lock;
 431
 432         spin_lock_irqsave(frac->core.lock, flags);
 433         if (sam9x60_pll_ready(regmap, id)) {
 434                 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 435                                    AT91_PMC_PLL_UPDT_ID_MSK, id);
 436                 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
 437                 frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
 438                 frac->frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
 439         } else {
 440                 /*
 441                  * This means the PLL is not setup by bootloaders. In this
 442                  * case we need to set the minimum rate for it. Otherwise
 443                  * a clock child of this PLL may be enabled before setting
 444                  * its rate leading to enabling this PLL with unsupported
 445                  * rate. This will lead to PLL not being locked at all.
 446                  */
 447                 parent_rate = clk_hw_get_rate(parent_hw);
 448                 if (!parent_rate) {
 449                         hw = ERR_PTR(-EINVAL);
 450                         goto free;
 451                 }
 452
 453                 ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
 454                                                         parent_rate, true);
 455                 if (ret <= 0) {
 456                         hw = ERR_PTR(ret);
 457                         goto free;
 458                 }
 459         }
 460         spin_unlock_irqrestore(frac->core.lock, flags);
 461
 462         hw = &frac->core.hw;
 463         ret = clk_hw_register(NULL, hw);
 464         if (ret) {
 465                 kfree(frac);
 466                 hw = ERR_PTR(ret);
 467         }
 468
 469         return hw;
 470
 471 free:
 472         spin_unlock_irqrestore(frac->core.lock, flags);
 473         kfree(frac);
 474         return hw;
 475 }
 476
 477 struct clk_hw * __init
 478 sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 479                              const char *name, const char *parent_name, u8 id,
 480                              const struct clk_pll_characteristics *characteristics,
 481                              const struct clk_pll_layout *layout, bool critical)
 482 {
 483         struct sam9x60_div *div;
 484         struct clk_hw *hw;
 485         struct clk_init_data init;
 486         unsigned long flags;
 487         unsigned int val;
 488         int ret;
 489
 490         if (id > PLL_MAX_ID || !lock)
 491                 return ERR_PTR(-EINVAL);
 492
 493         div = kzalloc(sizeof(*div), GFP_KERNEL);
 494         if (!div)
 495                 return ERR_PTR(-ENOMEM);
 496
 497         init.name = name;
 498         init.parent_names = &parent_name;
 499         init.num_parents = 1;
 500         init.ops = &sam9x60_div_pll_ops;
 501         init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 502                      CLK_SET_RATE_PARENT;
 503         if (critical)
 504                 init.flags |= CLK_IS_CRITICAL;
 505
 506         div->core.id = id;
 507         div->core.hw.init = &init;
 508         div->core.characteristics = characteristics;
 509         div->core.layout = layout;
 510         div->core.regmap = regmap;
 511         div->core.lock = lock;
 512
 513         spin_lock_irqsave(div->core.lock, flags);
 514
 515         regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 516                            AT91_PMC_PLL_UPDT_ID_MSK, id);
 517         regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 518         div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
 519
 520         spin_unlock_irqrestore(div->core.lock, flags);
 521
 522         hw = &div->core.hw;
 523         ret = clk_hw_register(NULL, hw);
 524         if (ret) {
 525                 kfree(div);
 526                 hw = ERR_PTR(ret);
 527         }
 528
 529         return hw;
 530 }
 531