1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 #include <linux/bitops.h>
7 #include <linux/clk-provider.h>
8 #include <linux/clkdev.h>
9 #include <linux/clk/at91_pmc.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/regmap.h>
16 DEFINE_SPINLOCK(pmc_pcr_lock);
18 #define PERIPHERAL_ID_MIN 2
19 #define PERIPHERAL_ID_MAX 31
20 #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
22 #define PERIPHERAL_MAX_SHIFT 3
24 struct clk_peripheral {
26 struct regmap *regmap;
30 #define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
32 struct clk_sam9x5_peripheral {
34 struct regmap *regmap;
35 struct clk_range range;
39 const struct clk_pcr_layout *layout;
40 struct at91_clk_pms pms;
45 #define to_clk_sam9x5_peripheral(hw) \
46 container_of(hw, struct clk_sam9x5_peripheral, hw)
48 static int clk_peripheral_enable(struct clk_hw *hw)
50 struct clk_peripheral *periph = to_clk_peripheral(hw);
51 int offset = AT91_PMC_PCER;
54 if (id < PERIPHERAL_ID_MIN)
56 if (id > PERIPHERAL_ID_MAX)
57 offset = AT91_PMC_PCER1;
58 regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id));
63 static void clk_peripheral_disable(struct clk_hw *hw)
65 struct clk_peripheral *periph = to_clk_peripheral(hw);
66 int offset = AT91_PMC_PCDR;
69 if (id < PERIPHERAL_ID_MIN)
71 if (id > PERIPHERAL_ID_MAX)
72 offset = AT91_PMC_PCDR1;
73 regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id));
76 static int clk_peripheral_is_enabled(struct clk_hw *hw)
78 struct clk_peripheral *periph = to_clk_peripheral(hw);
79 int offset = AT91_PMC_PCSR;
83 if (id < PERIPHERAL_ID_MIN)
85 if (id > PERIPHERAL_ID_MAX)
86 offset = AT91_PMC_PCSR1;
87 regmap_read(periph->regmap, offset, &status);
89 return status & PERIPHERAL_MASK(id) ? 1 : 0;
92 static const struct clk_ops peripheral_ops = {
93 .enable = clk_peripheral_enable,
94 .disable = clk_peripheral_disable,
95 .is_enabled = clk_peripheral_is_enabled,
98 struct clk_hw * __init
99 at91_clk_register_peripheral(struct regmap *regmap, const char *name,
100 const char *parent_name, struct clk_hw *parent_hw,
103 struct clk_peripheral *periph;
104 struct clk_init_data init = {};
108 if (!name || !(parent_name || parent_hw) || id > PERIPHERAL_ID_MAX)
109 return ERR_PTR(-EINVAL);
111 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
113 return ERR_PTR(-ENOMEM);
116 init.ops = &peripheral_ops;
118 init.parent_hws = (const struct clk_hw **)&parent_hw;
120 init.parent_names = &parent_name;
121 init.num_parents = 1;
125 periph->hw.init = &init;
126 periph->regmap = regmap;
129 ret = clk_hw_register(NULL, &periph->hw);
138 static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)
140 struct clk_hw *parent;
141 unsigned long parent_rate;
144 if (!periph->auto_div)
147 if (periph->range.max) {
148 parent = clk_hw_get_parent_by_index(&periph->hw, 0);
149 parent_rate = clk_hw_get_rate(parent);
153 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
154 if (parent_rate >> shift <= periph->range.max)
159 periph->auto_div = false;
163 static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph,
167 unsigned int enable = status ? AT91_PMC_PCR_EN : 0;
169 if (periph->id < PERIPHERAL_ID_MIN)
172 spin_lock_irqsave(periph->lock, flags);
173 regmap_write(periph->regmap, periph->layout->offset,
174 (periph->id & periph->layout->pid_mask));
175 regmap_update_bits(periph->regmap, periph->layout->offset,
176 periph->layout->div_mask | periph->layout->cmd |
178 field_prep(periph->layout->div_mask, periph->div) |
179 periph->layout->cmd | enable);
180 spin_unlock_irqrestore(periph->lock, flags);
185 static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
187 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
189 return clk_sam9x5_peripheral_set(periph, 1);
192 static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
194 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
197 if (periph->id < PERIPHERAL_ID_MIN)
200 spin_lock_irqsave(periph->lock, flags);
201 regmap_write(periph->regmap, periph->layout->offset,
202 (periph->id & periph->layout->pid_mask));
203 regmap_update_bits(periph->regmap, periph->layout->offset,
204 AT91_PMC_PCR_EN | periph->layout->cmd,
205 periph->layout->cmd);
206 spin_unlock_irqrestore(periph->lock, flags);
209 static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
211 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
215 if (periph->id < PERIPHERAL_ID_MIN)
218 spin_lock_irqsave(periph->lock, flags);
219 regmap_write(periph->regmap, periph->layout->offset,
220 (periph->id & periph->layout->pid_mask));
221 regmap_read(periph->regmap, periph->layout->offset, &status);
222 spin_unlock_irqrestore(periph->lock, flags);
224 return !!(status & AT91_PMC_PCR_EN);
228 clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
229 unsigned long parent_rate)
231 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
235 if (periph->id < PERIPHERAL_ID_MIN)
238 spin_lock_irqsave(periph->lock, flags);
239 regmap_write(periph->regmap, periph->layout->offset,
240 (periph->id & periph->layout->pid_mask));
241 regmap_read(periph->regmap, periph->layout->offset, &status);
242 spin_unlock_irqrestore(periph->lock, flags);
244 if (status & AT91_PMC_PCR_EN) {
245 periph->div = field_get(periph->layout->div_mask, status);
246 periph->auto_div = false;
248 clk_sam9x5_peripheral_autodiv(periph);
251 return parent_rate >> periph->div;
254 static void clk_sam9x5_peripheral_best_diff(struct clk_rate_request *req,
255 struct clk_hw *parent,
256 unsigned long parent_rate,
257 u32 shift, long *best_diff,
260 unsigned long tmp_rate = parent_rate >> shift;
261 unsigned long tmp_diff = abs(req->rate - tmp_rate);
263 if (*best_diff < 0 || *best_diff >= tmp_diff) {
264 *best_rate = tmp_rate;
265 *best_diff = tmp_diff;
266 req->best_parent_rate = parent_rate;
267 req->best_parent_hw = parent;
271 static int clk_sam9x5_peripheral_determine_rate(struct clk_hw *hw,
272 struct clk_rate_request *req)
274 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
275 struct clk_hw *parent = clk_hw_get_parent(hw);
276 unsigned long parent_rate = clk_hw_get_rate(parent);
277 unsigned long tmp_rate;
278 long best_rate = LONG_MIN;
279 long best_diff = LONG_MIN;
282 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
285 /* Fist step: check the available dividers. */
286 for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
287 tmp_rate = parent_rate >> shift;
289 if (periph->range.max && tmp_rate > periph->range.max)
292 clk_sam9x5_peripheral_best_diff(req, parent, parent_rate,
293 shift, &best_diff, &best_rate);
295 if (!best_diff || best_rate <= req->rate)
299 if (periph->chg_pid < 0)
302 /* Step two: try to request rate from parent. */
303 parent = clk_hw_get_parent_by_index(hw, periph->chg_pid);
307 for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
308 struct clk_rate_request req_parent;
310 clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate << shift);
311 if (__clk_determine_rate(parent, &req_parent))
314 clk_sam9x5_peripheral_best_diff(req, parent, req_parent.rate,
315 shift, &best_diff, &best_rate);
322 (periph->range.max && best_rate > periph->range.max))
325 pr_debug("PCK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
327 __clk_get_name((req->best_parent_hw)->clk),
328 req->best_parent_rate);
330 req->rate = best_rate;
335 static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
337 unsigned long *parent_rate)
340 unsigned long best_rate;
341 unsigned long best_diff;
342 unsigned long cur_rate = *parent_rate;
343 unsigned long cur_diff;
344 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
346 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
349 if (periph->range.max) {
350 for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
351 cur_rate = *parent_rate >> shift;
352 if (cur_rate <= periph->range.max)
357 if (rate >= cur_rate)
360 best_diff = cur_rate - rate;
361 best_rate = cur_rate;
362 for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
363 cur_rate = *parent_rate >> shift;
365 cur_diff = rate - cur_rate;
367 cur_diff = cur_rate - rate;
369 if (cur_diff < best_diff) {
370 best_diff = cur_diff;
371 best_rate = cur_rate;
374 if (!best_diff || cur_rate < rate)
381 static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
383 unsigned long parent_rate)
386 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
387 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
388 if (parent_rate == rate)
394 if (periph->range.max && rate > periph->range.max)
397 for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
398 if (parent_rate >> shift == rate) {
399 periph->auto_div = false;
408 static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw)
410 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
412 periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw);
417 static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw)
419 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
421 if (periph->pms.status)
422 clk_sam9x5_peripheral_set(periph, periph->pms.status);
425 static const struct clk_ops sam9x5_peripheral_ops = {
426 .enable = clk_sam9x5_peripheral_enable,
427 .disable = clk_sam9x5_peripheral_disable,
428 .is_enabled = clk_sam9x5_peripheral_is_enabled,
429 .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
430 .round_rate = clk_sam9x5_peripheral_round_rate,
431 .set_rate = clk_sam9x5_peripheral_set_rate,
432 .save_context = clk_sam9x5_peripheral_save_context,
433 .restore_context = clk_sam9x5_peripheral_restore_context,
436 static const struct clk_ops sam9x5_peripheral_chg_ops = {
437 .enable = clk_sam9x5_peripheral_enable,
438 .disable = clk_sam9x5_peripheral_disable,
439 .is_enabled = clk_sam9x5_peripheral_is_enabled,
440 .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
441 .determine_rate = clk_sam9x5_peripheral_determine_rate,
442 .set_rate = clk_sam9x5_peripheral_set_rate,
443 .save_context = clk_sam9x5_peripheral_save_context,
444 .restore_context = clk_sam9x5_peripheral_restore_context,
447 struct clk_hw * __init
448 at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
449 const struct clk_pcr_layout *layout,
450 const char *name, const char *parent_name,
451 struct clk_hw *parent_hw,
452 u32 id, const struct clk_range *range,
453 int chg_pid, unsigned long flags)
455 struct clk_sam9x5_peripheral *periph;
456 struct clk_init_data init = {};
460 if (!name || !(parent_name || parent_hw))
461 return ERR_PTR(-EINVAL);
463 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
465 return ERR_PTR(-ENOMEM);
469 init.parent_hws = (const struct clk_hw **)&parent_hw;
471 init.parent_names = &parent_name;
472 init.num_parents = 1;
475 init.ops = &sam9x5_peripheral_ops;
477 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
479 init.ops = &sam9x5_peripheral_chg_ops;
483 periph->hw.init = &init;
485 periph->regmap = regmap;
487 if (layout->div_mask)
488 periph->auto_div = true;
489 periph->layout = layout;
490 periph->range = *range;
491 periph->chg_pid = chg_pid;
494 ret = clk_hw_register(NULL, &periph->hw);
499 clk_sam9x5_peripheral_autodiv(periph);