1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
9 #include <linux/clk/at91_pmc.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/regmap.h>
16 #define MASTER_PRES_MASK 0x7
17 #define MASTER_PRES_MAX MASTER_PRES_MASK
18 #define MASTER_DIV_SHIFT 8
19 #define MASTER_DIV_MASK 0x7
21 #define PMC_MCR_CSS_SHIFT (16)
23 #define MASTER_MAX_ID 4
25 #define to_clk_master(hw) container_of(hw, struct clk_master, hw)
29 struct regmap *regmap;
31 const struct clk_master_layout *layout;
32 const struct clk_master_characteristics *characteristics;
33 struct at91_clk_pms pms;
43 /* MCK div reference to be used by notifier. */
44 static struct clk_master *master_div;
46 static inline bool clk_master_ready(struct clk_master *master)
48 unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
51 regmap_read(master->regmap, AT91_PMC_SR, &status);
53 return !!(status & bit);
56 static int clk_master_prepare(struct clk_hw *hw)
58 struct clk_master *master = to_clk_master(hw);
61 spin_lock_irqsave(master->lock, flags);
63 while (!clk_master_ready(master))
66 spin_unlock_irqrestore(master->lock, flags);
71 static int clk_master_is_prepared(struct clk_hw *hw)
73 struct clk_master *master = to_clk_master(hw);
77 spin_lock_irqsave(master->lock, flags);
78 status = clk_master_ready(master);
79 spin_unlock_irqrestore(master->lock, flags);
84 static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw,
85 unsigned long parent_rate)
88 unsigned long flags, rate = parent_rate;
89 struct clk_master *master = to_clk_master(hw);
90 const struct clk_master_layout *layout = master->layout;
91 const struct clk_master_characteristics *characteristics =
92 master->characteristics;
95 spin_lock_irqsave(master->lock, flags);
96 regmap_read(master->regmap, master->layout->offset, &mckr);
97 spin_unlock_irqrestore(master->lock, flags);
101 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
103 rate /= characteristics->divisors[div];
105 if (rate < characteristics->output.min)
106 pr_warn("master clk div is underclocked");
107 else if (rate > characteristics->output.max)
108 pr_warn("master clk div is overclocked");
113 static int clk_master_div_save_context(struct clk_hw *hw)
115 struct clk_master *master = to_clk_master(hw);
116 struct clk_hw *parent_hw = clk_hw_get_parent(hw);
118 unsigned int mckr, div;
120 spin_lock_irqsave(master->lock, flags);
121 regmap_read(master->regmap, master->layout->offset, &mckr);
122 spin_unlock_irqrestore(master->lock, flags);
124 mckr &= master->layout->mask;
125 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
126 div = master->characteristics->divisors[div];
128 master->pms.parent_rate = clk_hw_get_rate(parent_hw);
129 master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div);
134 static void clk_master_div_restore_context(struct clk_hw *hw)
136 struct clk_master *master = to_clk_master(hw);
141 spin_lock_irqsave(master->lock, flags);
142 regmap_read(master->regmap, master->layout->offset, &mckr);
143 spin_unlock_irqrestore(master->lock, flags);
145 mckr &= master->layout->mask;
146 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
147 div = master->characteristics->divisors[div];
149 if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate))
150 pr_warn("MCKR DIV not configured properly by firmware!\n");
153 static const struct clk_ops master_div_ops = {
154 .prepare = clk_master_prepare,
155 .is_prepared = clk_master_is_prepared,
156 .recalc_rate = clk_master_div_recalc_rate,
157 .save_context = clk_master_div_save_context,
158 .restore_context = clk_master_div_restore_context,
161 /* This function must be called with lock acquired. */
162 static int clk_master_div_set(struct clk_master *master,
163 unsigned long parent_rate, int div)
165 const struct clk_master_characteristics *characteristics =
166 master->characteristics;
167 unsigned long rate = parent_rate;
168 unsigned int max_div = 0, div_index = 0, max_div_index = 0;
169 unsigned int i, mckr, tmp;
172 for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
173 if (!characteristics->divisors[i])
176 if (div == characteristics->divisors[i])
179 if (max_div < characteristics->divisors[i]) {
180 max_div = characteristics->divisors[i];
186 div_index = max_div_index;
188 ret = regmap_read(master->regmap, master->layout->offset, &mckr);
192 mckr &= master->layout->mask;
193 tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
194 if (tmp == div_index)
197 rate /= characteristics->divisors[div_index];
198 if (rate < characteristics->output.min)
199 pr_warn("master clk div is underclocked");
200 else if (rate > characteristics->output.max)
201 pr_warn("master clk div is overclocked");
203 mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
204 mckr |= (div_index << MASTER_DIV_SHIFT);
205 ret = regmap_write(master->regmap, master->layout->offset, mckr);
209 while (!clk_master_ready(master))
212 master->div = characteristics->divisors[div_index];
217 static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw,
218 unsigned long parent_rate)
220 struct clk_master *master = to_clk_master(hw);
222 return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);
225 static void clk_master_div_restore_context_chg(struct clk_hw *hw)
227 struct clk_master *master = to_clk_master(hw);
231 spin_lock_irqsave(master->lock, flags);
232 ret = clk_master_div_set(master, master->pms.parent_rate,
233 DIV_ROUND_CLOSEST(master->pms.parent_rate,
235 spin_unlock_irqrestore(master->lock, flags);
237 pr_warn("Failed to restore MCK DIV clock\n");
240 static const struct clk_ops master_div_ops_chg = {
241 .prepare = clk_master_prepare,
242 .is_prepared = clk_master_is_prepared,
243 .recalc_rate = clk_master_div_recalc_rate_chg,
244 .save_context = clk_master_div_save_context,
245 .restore_context = clk_master_div_restore_context_chg,
248 static int clk_master_div_notifier_fn(struct notifier_block *notifier,
249 unsigned long code, void *data)
251 const struct clk_master_characteristics *characteristics =
252 master_div->characteristics;
253 struct clk_notifier_data *cnd = data;
254 unsigned long flags, new_parent_rate, new_rate;
255 unsigned int mckr, div, new_div = 0;
260 spin_lock_irqsave(master_div->lock, flags);
262 case PRE_RATE_CHANGE:
264 * We want to avoid any overclocking of MCK DIV domain. To do
265 * this we set a safe divider (the underclocking is not of
266 * interest as we can go as low as 32KHz). The relation
267 * b/w this clock and its parents are as follows:
269 * FRAC PLL -> DIV PLL -> MCK DIV
271 * With the proper safe divider we should be good even with FRAC
272 * PLL at its maximum value.
274 ret = regmap_read(master_div->regmap, master_div->layout->offset,
277 ret = NOTIFY_STOP_MASK;
281 mckr &= master_div->layout->mask;
282 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
284 /* Switch to safe divider. */
285 clk_master_div_set(master_div,
286 cnd->old_rate * characteristics->divisors[div],
287 master_div->safe_div);
290 case POST_RATE_CHANGE:
292 * At this point we want to restore MCK DIV domain to its maximum
295 ret = regmap_read(master_div->regmap, master_div->layout->offset,
298 ret = NOTIFY_STOP_MASK;
302 mckr &= master_div->layout->mask;
303 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
304 new_parent_rate = cnd->new_rate * characteristics->divisors[div];
306 for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
307 if (!characteristics->divisors[i])
310 new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate,
311 characteristics->divisors[i]);
313 tmp_diff = characteristics->output.max - new_rate;
317 if (best_diff < 0 || best_diff > tmp_diff) {
318 new_div = characteristics->divisors[i];
319 best_diff = tmp_diff;
327 ret = NOTIFY_STOP_MASK;
331 /* Update the div to preserve MCK DIV clock rate. */
332 clk_master_div_set(master_div, new_parent_rate,
344 spin_unlock_irqrestore(master_div->lock, flags);
349 static struct notifier_block clk_master_div_notifier = {
350 .notifier_call = clk_master_div_notifier_fn,
353 static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
354 struct clk_hw *parent,
355 unsigned long parent_rate,
360 unsigned long tmp_rate, tmp_diff;
362 if (div == MASTER_PRES_MAX)
363 tmp_rate = parent_rate / 3;
365 tmp_rate = parent_rate >> div;
367 tmp_diff = abs(req->rate - tmp_rate);
369 if (*best_diff < 0 || *best_diff >= tmp_diff) {
370 *best_rate = tmp_rate;
371 *best_diff = tmp_diff;
372 req->best_parent_rate = parent_rate;
373 req->best_parent_hw = parent;
377 static int clk_master_pres_determine_rate(struct clk_hw *hw,
378 struct clk_rate_request *req)
380 struct clk_master *master = to_clk_master(hw);
381 struct clk_rate_request req_parent = *req;
382 const struct clk_master_characteristics *characteristics =
383 master->characteristics;
384 struct clk_hw *parent;
385 long best_rate = LONG_MIN, best_diff = LONG_MIN;
389 if (master->chg_pid < 0)
392 parent = clk_hw_get_parent_by_index(hw, master->chg_pid);
396 for (i = 0; i <= MASTER_PRES_MAX; i++) {
397 if (characteristics->have_div3_pres && i == MASTER_PRES_MAX)
402 req_parent.rate = req->rate * pres;
403 if (__clk_determine_rate(parent, &req_parent))
406 clk_sama7g5_master_best_diff(req, parent, req_parent.rate,
407 &best_diff, &best_rate, pres);
415 static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,
416 unsigned long parent_rate)
418 struct clk_master *master = to_clk_master(hw);
420 unsigned int pres, mckr, tmp;
423 pres = DIV_ROUND_CLOSEST(parent_rate, rate);
424 if (pres > MASTER_PRES_MAX)
428 pres = MASTER_PRES_MAX;
430 pres = ffs(pres) - 1;
432 spin_lock_irqsave(master->lock, flags);
433 ret = regmap_read(master->regmap, master->layout->offset, &mckr);
437 mckr &= master->layout->mask;
438 tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK;
442 mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift);
443 mckr |= (pres << master->layout->pres_shift);
444 ret = regmap_write(master->regmap, master->layout->offset, mckr);
448 while (!clk_master_ready(master))
451 spin_unlock_irqrestore(master->lock, flags);
456 static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
457 unsigned long parent_rate)
459 struct clk_master *master = to_clk_master(hw);
460 const struct clk_master_characteristics *characteristics =
461 master->characteristics;
463 unsigned int val, pres;
465 spin_lock_irqsave(master->lock, flags);
466 regmap_read(master->regmap, master->layout->offset, &val);
467 spin_unlock_irqrestore(master->lock, flags);
469 val &= master->layout->mask;
470 pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
471 if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
476 return DIV_ROUND_CLOSEST_ULL(parent_rate, pres);
479 static u8 clk_master_pres_get_parent(struct clk_hw *hw)
481 struct clk_master *master = to_clk_master(hw);
485 spin_lock_irqsave(master->lock, flags);
486 regmap_read(master->regmap, master->layout->offset, &mckr);
487 spin_unlock_irqrestore(master->lock, flags);
489 mckr &= master->layout->mask;
491 return mckr & AT91_PMC_CSS;
494 static int clk_master_pres_save_context(struct clk_hw *hw)
496 struct clk_master *master = to_clk_master(hw);
497 struct clk_hw *parent_hw = clk_hw_get_parent(hw);
499 unsigned int val, pres;
501 spin_lock_irqsave(master->lock, flags);
502 regmap_read(master->regmap, master->layout->offset, &val);
503 spin_unlock_irqrestore(master->lock, flags);
505 val &= master->layout->mask;
506 pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
507 if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
512 master->pms.parent = val & AT91_PMC_CSS;
513 master->pms.parent_rate = clk_hw_get_rate(parent_hw);
514 master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres);
519 static void clk_master_pres_restore_context(struct clk_hw *hw)
521 struct clk_master *master = to_clk_master(hw);
523 unsigned int val, pres;
525 spin_lock_irqsave(master->lock, flags);
526 regmap_read(master->regmap, master->layout->offset, &val);
527 spin_unlock_irqrestore(master->lock, flags);
529 val &= master->layout->mask;
530 pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
531 if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
536 if (master->pms.rate !=
537 DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) ||
538 (master->pms.parent != (val & AT91_PMC_CSS)))
539 pr_warn("MCKR PRES was not configured properly by firmware!\n");
542 static void clk_master_pres_restore_context_chg(struct clk_hw *hw)
544 struct clk_master *master = to_clk_master(hw);
546 clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate);
549 static const struct clk_ops master_pres_ops = {
550 .prepare = clk_master_prepare,
551 .is_prepared = clk_master_is_prepared,
552 .recalc_rate = clk_master_pres_recalc_rate,
553 .get_parent = clk_master_pres_get_parent,
554 .save_context = clk_master_pres_save_context,
555 .restore_context = clk_master_pres_restore_context,
558 static const struct clk_ops master_pres_ops_chg = {
559 .prepare = clk_master_prepare,
560 .is_prepared = clk_master_is_prepared,
561 .determine_rate = clk_master_pres_determine_rate,
562 .recalc_rate = clk_master_pres_recalc_rate,
563 .get_parent = clk_master_pres_get_parent,
564 .set_rate = clk_master_pres_set_rate,
565 .save_context = clk_master_pres_save_context,
566 .restore_context = clk_master_pres_restore_context_chg,
569 static struct clk_hw * __init
570 at91_clk_register_master_internal(struct regmap *regmap,
571 const char *name, int num_parents,
572 const char **parent_names,
573 const struct clk_master_layout *layout,
574 const struct clk_master_characteristics *characteristics,
575 const struct clk_ops *ops, spinlock_t *lock, u32 flags,
578 struct clk_master *master;
579 struct clk_init_data init;
582 unsigned long irqflags;
585 if (!name || !num_parents || !parent_names || !lock)
586 return ERR_PTR(-EINVAL);
588 master = kzalloc(sizeof(*master), GFP_KERNEL);
590 return ERR_PTR(-ENOMEM);
594 init.parent_names = parent_names;
595 init.num_parents = num_parents;
598 master->hw.init = &init;
599 master->layout = layout;
600 master->characteristics = characteristics;
601 master->regmap = regmap;
602 master->chg_pid = chg_pid;
605 if (ops == &master_div_ops_chg) {
606 spin_lock_irqsave(master->lock, irqflags);
607 regmap_read(master->regmap, master->layout->offset, &mckr);
608 spin_unlock_irqrestore(master->lock, irqflags);
610 mckr &= layout->mask;
611 mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
612 master->div = characteristics->divisors[mckr];
616 ret = clk_hw_register(NULL, &master->hw);
625 struct clk_hw * __init
626 at91_clk_register_master_pres(struct regmap *regmap,
627 const char *name, int num_parents,
628 const char **parent_names,
629 const struct clk_master_layout *layout,
630 const struct clk_master_characteristics *characteristics,
631 spinlock_t *lock, u32 flags, int chg_pid)
633 const struct clk_ops *ops;
635 if (flags & CLK_SET_RATE_GATE)
636 ops = &master_pres_ops;
638 ops = &master_pres_ops_chg;
640 return at91_clk_register_master_internal(regmap, name, num_parents,
641 parent_names, layout,
642 characteristics, ops,
643 lock, flags, chg_pid);
646 struct clk_hw * __init
647 at91_clk_register_master_div(struct regmap *regmap,
648 const char *name, const char *parent_name,
649 const struct clk_master_layout *layout,
650 const struct clk_master_characteristics *characteristics,
651 spinlock_t *lock, u32 flags, u32 safe_div)
653 const struct clk_ops *ops;
656 if (flags & CLK_SET_RATE_GATE)
657 ops = &master_div_ops;
659 ops = &master_div_ops_chg;
661 hw = at91_clk_register_master_internal(regmap, name, 1,
662 &parent_name, layout,
663 characteristics, ops,
664 lock, flags, -EINVAL);
666 if (!IS_ERR(hw) && safe_div) {
667 master_div = to_clk_master(hw);
668 master_div->safe_div = safe_div;
669 clk_notifier_register(hw->clk,
670 &clk_master_div_notifier);
677 clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
678 unsigned long parent_rate)
680 struct clk_master *master = to_clk_master(hw);
682 return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
685 static int clk_sama7g5_master_determine_rate(struct clk_hw *hw,
686 struct clk_rate_request *req)
688 struct clk_master *master = to_clk_master(hw);
689 struct clk_rate_request req_parent = *req;
690 struct clk_hw *parent;
691 long best_rate = LONG_MIN, best_diff = LONG_MIN;
692 unsigned long parent_rate;
695 /* First: check the dividers of MCR. */
696 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
697 parent = clk_hw_get_parent_by_index(hw, i);
701 parent_rate = clk_hw_get_rate(parent);
705 for (div = 0; div < MASTER_PRES_MAX + 1; div++) {
706 clk_sama7g5_master_best_diff(req, parent, parent_rate,
707 &best_rate, &best_diff,
717 /* Second: try to request rate form changeable parent. */
718 if (master->chg_pid < 0)
721 parent = clk_hw_get_parent_by_index(hw, master->chg_pid);
725 for (div = 0; div < MASTER_PRES_MAX + 1; div++) {
726 if (div == MASTER_PRES_MAX)
727 req_parent.rate = req->rate * 3;
729 req_parent.rate = req->rate << div;
731 if (__clk_determine_rate(parent, &req_parent))
734 clk_sama7g5_master_best_diff(req, parent, req_parent.rate,
735 &best_rate, &best_diff, div);
742 pr_debug("MCK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
744 __clk_get_name((req->best_parent_hw)->clk),
745 req->best_parent_rate);
750 req->rate = best_rate;
755 static u8 clk_sama7g5_master_get_parent(struct clk_hw *hw)
757 struct clk_master *master = to_clk_master(hw);
761 spin_lock_irqsave(master->lock, flags);
762 index = clk_mux_val_to_index(&master->hw, master->mux_table, 0,
764 spin_unlock_irqrestore(master->lock, flags);
769 static int clk_sama7g5_master_set_parent(struct clk_hw *hw, u8 index)
771 struct clk_master *master = to_clk_master(hw);
774 if (index >= clk_hw_get_num_parents(hw))
777 spin_lock_irqsave(master->lock, flags);
778 master->parent = clk_mux_index_to_val(master->mux_table, 0, index);
779 spin_unlock_irqrestore(master->lock, flags);
784 static void clk_sama7g5_master_set(struct clk_master *master,
788 unsigned int val, cparent;
789 unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
790 unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT;
791 unsigned int div = master->div << MASTER_DIV_SHIFT;
793 spin_lock_irqsave(master->lock, flags);
795 regmap_write(master->regmap, AT91_PMC_MCR_V2,
796 AT91_PMC_MCR_V2_ID(master->id));
797 regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
798 regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
799 enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
800 AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
801 enable | parent | div | AT91_PMC_MCR_V2_CMD |
802 AT91_PMC_MCR_V2_ID(master->id));
804 cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
806 /* Wait here only if parent is being changed. */
807 while ((cparent != master->parent) && !clk_master_ready(master))
810 spin_unlock_irqrestore(master->lock, flags);
813 static int clk_sama7g5_master_enable(struct clk_hw *hw)
815 struct clk_master *master = to_clk_master(hw);
817 clk_sama7g5_master_set(master, 1);
822 static void clk_sama7g5_master_disable(struct clk_hw *hw)
824 struct clk_master *master = to_clk_master(hw);
827 spin_lock_irqsave(master->lock, flags);
829 regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
830 regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
831 AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |
832 AT91_PMC_MCR_V2_ID_MSK,
833 AT91_PMC_MCR_V2_CMD |
834 AT91_PMC_MCR_V2_ID(master->id));
836 spin_unlock_irqrestore(master->lock, flags);
839 static int clk_sama7g5_master_is_enabled(struct clk_hw *hw)
841 struct clk_master *master = to_clk_master(hw);
845 spin_lock_irqsave(master->lock, flags);
847 regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
848 regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
850 spin_unlock_irqrestore(master->lock, flags);
852 return !!(val & AT91_PMC_MCR_V2_EN);
855 static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
856 unsigned long parent_rate)
858 struct clk_master *master = to_clk_master(hw);
859 unsigned long div, flags;
861 div = DIV_ROUND_CLOSEST(parent_rate, rate);
862 if ((div > (1 << (MASTER_PRES_MAX - 1))) || (div & (div - 1)))
866 div = MASTER_PRES_MAX;
870 spin_lock_irqsave(master->lock, flags);
872 spin_unlock_irqrestore(master->lock, flags);
877 static int clk_sama7g5_master_save_context(struct clk_hw *hw)
879 struct clk_master *master = to_clk_master(hw);
881 master->pms.status = clk_sama7g5_master_is_enabled(hw);
886 static void clk_sama7g5_master_restore_context(struct clk_hw *hw)
888 struct clk_master *master = to_clk_master(hw);
890 if (master->pms.status)
891 clk_sama7g5_master_set(master, master->pms.status);
894 static const struct clk_ops sama7g5_master_ops = {
895 .enable = clk_sama7g5_master_enable,
896 .disable = clk_sama7g5_master_disable,
897 .is_enabled = clk_sama7g5_master_is_enabled,
898 .recalc_rate = clk_sama7g5_master_recalc_rate,
899 .determine_rate = clk_sama7g5_master_determine_rate,
900 .set_rate = clk_sama7g5_master_set_rate,
901 .get_parent = clk_sama7g5_master_get_parent,
902 .set_parent = clk_sama7g5_master_set_parent,
903 .save_context = clk_sama7g5_master_save_context,
904 .restore_context = clk_sama7g5_master_restore_context,
907 struct clk_hw * __init
908 at91_clk_sama7g5_register_master(struct regmap *regmap,
909 const char *name, int num_parents,
910 const char **parent_names,
912 spinlock_t *lock, u8 id,
913 bool critical, int chg_pid)
915 struct clk_master *master;
917 struct clk_init_data init;
922 if (!name || !num_parents || !parent_names || !mux_table ||
923 !lock || id > MASTER_MAX_ID)
924 return ERR_PTR(-EINVAL);
926 master = kzalloc(sizeof(*master), GFP_KERNEL);
928 return ERR_PTR(-ENOMEM);
931 init.ops = &sama7g5_master_ops;
932 init.parent_names = parent_names;
933 init.num_parents = num_parents;
934 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
936 init.flags |= CLK_SET_RATE_PARENT;
938 init.flags |= CLK_IS_CRITICAL;
940 master->hw.init = &init;
941 master->regmap = regmap;
943 master->chg_pid = chg_pid;
945 master->mux_table = mux_table;
947 spin_lock_irqsave(master->lock, flags);
948 regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
949 regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
950 master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
951 master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
952 spin_unlock_irqrestore(master->lock, flags);
955 ret = clk_hw_register(NULL, &master->hw);
964 const struct clk_master_layout at91rm9200_master_layout = {
967 .offset = AT91_PMC_MCKR,
970 const struct clk_master_layout at91sam9x5_master_layout = {
973 .offset = AT91_PMC_MCKR,