1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
6 #include <dt-bindings/clock/at91.h>
10 static DEFINE_SPINLOCK(mck_lock);
12 static const struct clk_master_characteristics mck_characteristics = {
13 .output = { .min = 0, .max = 133333333 },
14 .divisors = { 1, 2, 4, 3 },
18 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
20 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
22 static const struct clk_range plla_outputs[] = {
23 { .min = 745000000, .max = 800000000 },
24 { .min = 695000000, .max = 750000000 },
25 { .min = 645000000, .max = 700000000 },
26 { .min = 595000000, .max = 650000000 },
27 { .min = 545000000, .max = 600000000 },
28 { .min = 495000000, .max = 555000000 },
29 { .min = 445000000, .max = 500000000 },
30 { .min = 400000000, .max = 450000000 },
33 static const struct clk_pll_characteristics plla_characteristics = {
34 .input = { .min = 2000000, .max = 32000000 },
35 .num_output = ARRAY_SIZE(plla_outputs),
36 .output = plla_outputs,
45 } at91sam9x5_systemck[] = {
46 { .n = "ddrck", .p = "masterck_div", .id = 2 },
47 { .n = "smdck", .p = "smdclk", .id = 4 },
48 { .n = "uhpck", .p = "usbck", .id = 6 },
49 { .n = "udpck", .p = "usbck", .id = 7 },
50 { .n = "pck0", .p = "prog0", .id = 8 },
51 { .n = "pck1", .p = "prog1", .id = 9 },
54 static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
57 .pid_mask = GENMASK(5, 0),
58 .div_mask = GENMASK(17, 16),
66 static const struct pck at91sam9x5_periphck[] = {
67 { .n = "pioAB_clk", .id = 2, },
68 { .n = "pioCD_clk", .id = 3, },
69 { .n = "smd_clk", .id = 4, },
70 { .n = "usart0_clk", .id = 5, },
71 { .n = "usart1_clk", .id = 6, },
72 { .n = "usart2_clk", .id = 7, },
73 { .n = "twi0_clk", .id = 9, },
74 { .n = "twi1_clk", .id = 10, },
75 { .n = "twi2_clk", .id = 11, },
76 { .n = "mci0_clk", .id = 12, },
77 { .n = "spi0_clk", .id = 13, },
78 { .n = "spi1_clk", .id = 14, },
79 { .n = "uart0_clk", .id = 15, },
80 { .n = "uart1_clk", .id = 16, },
81 { .n = "tcb0_clk", .id = 17, },
82 { .n = "pwm_clk", .id = 18, },
83 { .n = "adc_clk", .id = 19, },
84 { .n = "dma0_clk", .id = 20, },
85 { .n = "dma1_clk", .id = 21, },
86 { .n = "uhphs_clk", .id = 22, },
87 { .n = "udphs_clk", .id = 23, },
88 { .n = "mci1_clk", .id = 26, },
89 { .n = "ssc0_clk", .id = 28, },
92 static const struct pck at91sam9g15_periphck[] = {
93 { .n = "lcdc_clk", .id = 25, },
97 static const struct pck at91sam9g25_periphck[] = {
98 { .n = "usart3_clk", .id = 8, },
99 { .n = "macb0_clk", .id = 24, },
100 { .n = "isi_clk", .id = 25, },
104 static const struct pck at91sam9g35_periphck[] = {
105 { .n = "macb0_clk", .id = 24, },
106 { .n = "lcdc_clk", .id = 25, },
110 static const struct pck at91sam9x25_periphck[] = {
111 { .n = "usart3_clk", .id = 8, },
112 { .n = "macb0_clk", .id = 24, },
113 { .n = "macb1_clk", .id = 27, },
114 { .n = "can0_clk", .id = 29, },
115 { .n = "can1_clk", .id = 30, },
119 static const struct pck at91sam9x35_periphck[] = {
120 { .n = "macb0_clk", .id = 24, },
121 { .n = "lcdc_clk", .id = 25, },
122 { .n = "can0_clk", .id = 29, },
123 { .n = "can1_clk", .id = 30, },
127 static void __init at91sam9x5_pmc_setup(struct device_node *np,
128 const struct pck *extra_pcks,
131 struct clk_range range = CLK_RANGE(0, 0);
132 const char *slck_name, *mainxtal_name;
133 struct pmc_data *at91sam9x5_pmc;
134 const char *parent_names[6];
135 struct regmap *regmap;
140 i = of_property_match_string(np, "clock-names", "slow_clk");
144 slck_name = of_clk_get_parent_name(np, i);
146 i = of_property_match_string(np, "clock-names", "main_xtal");
149 mainxtal_name = of_clk_get_parent_name(np, i);
151 regmap = device_node_to_regmap(np);
155 at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1,
156 nck(at91sam9x5_systemck), 31, 0, 2);
160 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
165 bypass = of_property_read_bool(np, "atmel,osc-bypass");
167 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
172 parent_names[0] = "main_rc_osc";
173 parent_names[1] = "main_osc";
174 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
178 at91sam9x5_pmc->chws[PMC_MAIN] = hw;
180 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
181 &at91rm9200_pll_layout, &plla_characteristics);
185 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
189 at91sam9x5_pmc->chws[PMC_PLLACK] = hw;
191 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
195 at91sam9x5_pmc->chws[PMC_UTMI] = hw;
197 parent_names[0] = slck_name;
198 parent_names[1] = "mainck";
199 parent_names[2] = "plladivck";
200 parent_names[3] = "utmick";
201 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
203 &at91sam9x5_master_layout,
204 &mck_characteristics, &mck_lock,
205 CLK_SET_RATE_GATE, INT_MIN);
209 hw = at91_clk_register_master_div(regmap, "masterck_div",
211 &at91sam9x5_master_layout,
212 &mck_characteristics, &mck_lock,
217 at91sam9x5_pmc->chws[PMC_MCK] = hw;
219 parent_names[0] = "plladivck";
220 parent_names[1] = "utmick";
221 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
225 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
229 parent_names[0] = slck_name;
230 parent_names[1] = "mainck";
231 parent_names[2] = "plladivck";
232 parent_names[3] = "utmick";
233 parent_names[4] = "masterck_div";
234 for (i = 0; i < 2; i++) {
237 snprintf(name, sizeof(name), "prog%d", i);
239 hw = at91_clk_register_programmable(regmap, name,
241 &at91sam9x5_programmable_layout,
246 at91sam9x5_pmc->pchws[i] = hw;
249 for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
250 hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
251 at91sam9x5_systemck[i].p,
252 at91sam9x5_systemck[i].id);
256 at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
260 hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3);
264 at91sam9x5_pmc->shws[3] = hw;
267 for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
268 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
269 &at91sam9x5_pcr_layout,
270 at91sam9x5_periphck[i].n,
272 at91sam9x5_periphck[i].id,
277 at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
280 for (i = 0; extra_pcks[i].id; i++) {
281 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
282 &at91sam9x5_pcr_layout,
290 at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
293 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
298 kfree(at91sam9x5_pmc);
301 static void __init at91sam9g15_pmc_setup(struct device_node *np)
303 at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
306 CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup);
308 static void __init at91sam9g25_pmc_setup(struct device_node *np)
310 at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
313 CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup);
315 static void __init at91sam9g35_pmc_setup(struct device_node *np)
317 at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
320 CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup);
322 static void __init at91sam9x25_pmc_setup(struct device_node *np)
324 at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
327 CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup);
329 static void __init at91sam9x35_pmc_setup(struct device_node *np)
331 at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
334 CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);