1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
6 #include <dt-bindings/clock/at91.h>
10 static const struct clk_master_characteristics mck_characteristics = {
11 .output = { .min = 0, .max = 133333333 },
12 .divisors = { 1, 2, 4, 3 },
16 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
18 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
20 static const struct clk_range plla_outputs[] = {
21 { .min = 745000000, .max = 800000000 },
22 { .min = 695000000, .max = 750000000 },
23 { .min = 645000000, .max = 700000000 },
24 { .min = 595000000, .max = 650000000 },
25 { .min = 545000000, .max = 600000000 },
26 { .min = 495000000, .max = 555000000 },
27 { .min = 445000000, .max = 500000000 },
28 { .min = 400000000, .max = 450000000 },
31 static const struct clk_pll_characteristics plla_characteristics = {
32 .input = { .min = 2000000, .max = 32000000 },
33 .num_output = ARRAY_SIZE(plla_outputs),
34 .output = plla_outputs,
43 } at91sam9x5_systemck[] = {
44 { .n = "ddrck", .p = "masterck", .id = 2 },
45 { .n = "smdck", .p = "smdclk", .id = 4 },
46 { .n = "uhpck", .p = "usbck", .id = 6 },
47 { .n = "udpck", .p = "usbck", .id = 7 },
48 { .n = "pck0", .p = "prog0", .id = 8 },
49 { .n = "pck1", .p = "prog1", .id = 9 },
52 static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
55 .pid_mask = GENMASK(5, 0),
56 .div_mask = GENMASK(17, 16),
64 static const struct pck at91sam9x5_periphck[] = {
65 { .n = "pioAB_clk", .id = 2, },
66 { .n = "pioCD_clk", .id = 3, },
67 { .n = "smd_clk", .id = 4, },
68 { .n = "usart0_clk", .id = 5, },
69 { .n = "usart1_clk", .id = 6, },
70 { .n = "usart2_clk", .id = 7, },
71 { .n = "twi0_clk", .id = 9, },
72 { .n = "twi1_clk", .id = 10, },
73 { .n = "twi2_clk", .id = 11, },
74 { .n = "mci0_clk", .id = 12, },
75 { .n = "spi0_clk", .id = 13, },
76 { .n = "spi1_clk", .id = 14, },
77 { .n = "uart0_clk", .id = 15, },
78 { .n = "uart1_clk", .id = 16, },
79 { .n = "tcb0_clk", .id = 17, },
80 { .n = "pwm_clk", .id = 18, },
81 { .n = "adc_clk", .id = 19, },
82 { .n = "dma0_clk", .id = 20, },
83 { .n = "dma1_clk", .id = 21, },
84 { .n = "uhphs_clk", .id = 22, },
85 { .n = "udphs_clk", .id = 23, },
86 { .n = "mci1_clk", .id = 26, },
87 { .n = "ssc0_clk", .id = 28, },
90 static const struct pck at91sam9g15_periphck[] = {
91 { .n = "lcdc_clk", .id = 25, },
95 static const struct pck at91sam9g25_periphck[] = {
96 { .n = "usart3_clk", .id = 8, },
97 { .n = "macb0_clk", .id = 24, },
98 { .n = "isi_clk", .id = 25, },
102 static const struct pck at91sam9g35_periphck[] = {
103 { .n = "macb0_clk", .id = 24, },
104 { .n = "lcdc_clk", .id = 25, },
108 static const struct pck at91sam9x25_periphck[] = {
109 { .n = "usart3_clk", .id = 8, },
110 { .n = "macb0_clk", .id = 24, },
111 { .n = "macb1_clk", .id = 27, },
112 { .n = "can0_clk", .id = 29, },
113 { .n = "can1_clk", .id = 30, },
117 static const struct pck at91sam9x35_periphck[] = {
118 { .n = "macb0_clk", .id = 24, },
119 { .n = "lcdc_clk", .id = 25, },
120 { .n = "can0_clk", .id = 29, },
121 { .n = "can1_clk", .id = 30, },
125 static void __init at91sam9x5_pmc_setup(struct device_node *np,
126 const struct pck *extra_pcks,
129 struct clk_range range = CLK_RANGE(0, 0);
130 const char *slck_name, *mainxtal_name;
131 struct pmc_data *at91sam9x5_pmc;
132 const char *parent_names[6];
133 struct regmap *regmap;
138 i = of_property_match_string(np, "clock-names", "slow_clk");
142 slck_name = of_clk_get_parent_name(np, i);
144 i = of_property_match_string(np, "clock-names", "main_xtal");
147 mainxtal_name = of_clk_get_parent_name(np, i);
149 regmap = device_node_to_regmap(np);
153 at91sam9x5_pmc = pmc_data_allocate(PMC_MAIN + 1,
154 nck(at91sam9x5_systemck), 31, 0);
158 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
163 bypass = of_property_read_bool(np, "atmel,osc-bypass");
165 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
170 parent_names[0] = "main_rc_osc";
171 parent_names[1] = "main_osc";
172 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
176 at91sam9x5_pmc->chws[PMC_MAIN] = hw;
178 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
179 &at91rm9200_pll_layout, &plla_characteristics);
183 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
187 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
191 at91sam9x5_pmc->chws[PMC_UTMI] = hw;
193 parent_names[0] = slck_name;
194 parent_names[1] = "mainck";
195 parent_names[2] = "plladivck";
196 parent_names[3] = "utmick";
197 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
198 &at91sam9x5_master_layout,
199 &mck_characteristics);
203 at91sam9x5_pmc->chws[PMC_MCK] = hw;
205 parent_names[0] = "plladivck";
206 parent_names[1] = "utmick";
207 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
211 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
215 parent_names[0] = slck_name;
216 parent_names[1] = "mainck";
217 parent_names[2] = "plladivck";
218 parent_names[3] = "utmick";
219 parent_names[4] = "masterck";
220 for (i = 0; i < 2; i++) {
223 snprintf(name, sizeof(name), "prog%d", i);
225 hw = at91_clk_register_programmable(regmap, name,
227 &at91sam9x5_programmable_layout);
232 for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
233 hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
234 at91sam9x5_systemck[i].p,
235 at91sam9x5_systemck[i].id);
239 at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
243 hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3);
247 at91sam9x5_pmc->shws[3] = hw;
250 for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
251 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
252 &at91sam9x5_pcr_layout,
253 at91sam9x5_periphck[i].n,
255 at91sam9x5_periphck[i].id,
260 at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
263 for (i = 0; extra_pcks[i].id; i++) {
264 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
265 &at91sam9x5_pcr_layout,
273 at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
276 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
281 pmc_data_free(at91sam9x5_pmc);
284 static void __init at91sam9g15_pmc_setup(struct device_node *np)
286 at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
288 CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
289 at91sam9g15_pmc_setup);
291 static void __init at91sam9g25_pmc_setup(struct device_node *np)
293 at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
295 CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
296 at91sam9g25_pmc_setup);
298 static void __init at91sam9g35_pmc_setup(struct device_node *np)
300 at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
302 CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
303 at91sam9g35_pmc_setup);
305 static void __init at91sam9x25_pmc_setup(struct device_node *np)
307 at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
309 CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
310 at91sam9x25_pmc_setup);
312 static void __init at91sam9x35_pmc_setup(struct device_node *np)
314 at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
316 CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
317 at91sam9x35_pmc_setup);