1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
6 #include <dt-bindings/clock/at91.h>
10 static const struct clk_master_characteristics mck_characteristics = {
11 .output = { .min = 0, .max = 133333333 },
12 .divisors = { 1, 2, 4, 3 },
16 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
18 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
20 static const struct clk_range plla_outputs[] = {
21 { .min = 745000000, .max = 800000000 },
22 { .min = 695000000, .max = 750000000 },
23 { .min = 645000000, .max = 700000000 },
24 { .min = 595000000, .max = 650000000 },
25 { .min = 545000000, .max = 600000000 },
26 { .min = 495000000, .max = 555000000 },
27 { .min = 445000000, .max = 500000000 },
28 { .min = 400000000, .max = 450000000 },
31 static const struct clk_pll_characteristics plla_characteristics = {
32 .input = { .min = 2000000, .max = 32000000 },
33 .num_output = ARRAY_SIZE(plla_outputs),
34 .output = plla_outputs,
39 static u8 pllb_out[] = { 0 };
41 static const struct clk_range pllb_outputs[] = {
42 { .min = 30000000, .max = 100000000 },
45 static const struct clk_pll_characteristics pllb_characteristics = {
46 .input = { .min = 2000000, .max = 32000000 },
47 .num_output = ARRAY_SIZE(pllb_outputs),
48 .output = pllb_outputs,
56 } at91sam9n12_systemck[] = {
57 { .n = "ddrck", .p = "masterck", .id = 2 },
58 { .n = "lcdck", .p = "masterck", .id = 3 },
59 { .n = "uhpck", .p = "usbck", .id = 6 },
60 { .n = "udpck", .p = "usbck", .id = 7 },
61 { .n = "pck0", .p = "prog0", .id = 8 },
62 { .n = "pck1", .p = "prog1", .id = 9 },
65 static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
68 .pid_mask = GENMASK(5, 0),
69 .div_mask = GENMASK(17, 16),
77 static const struct pck at91sam9n12_periphck[] = {
78 { .n = "pioAB_clk", .id = 2, },
79 { .n = "pioCD_clk", .id = 3, },
80 { .n = "fuse_clk", .id = 4, },
81 { .n = "usart0_clk", .id = 5, },
82 { .n = "usart1_clk", .id = 6, },
83 { .n = "usart2_clk", .id = 7, },
84 { .n = "usart3_clk", .id = 8, },
85 { .n = "twi0_clk", .id = 9, },
86 { .n = "twi1_clk", .id = 10, },
87 { .n = "mci0_clk", .id = 12, },
88 { .n = "spi0_clk", .id = 13, },
89 { .n = "spi1_clk", .id = 14, },
90 { .n = "uart0_clk", .id = 15, },
91 { .n = "uart1_clk", .id = 16, },
92 { .n = "tcb_clk", .id = 17, },
93 { .n = "pwm_clk", .id = 18, },
94 { .n = "adc_clk", .id = 19, },
95 { .n = "dma0_clk", .id = 20, },
96 { .n = "uhphs_clk", .id = 22, },
97 { .n = "udphs_clk", .id = 23, },
98 { .n = "lcdc_clk", .id = 25, },
99 { .n = "sha_clk", .id = 27, },
100 { .n = "ssc0_clk", .id = 28, },
101 { .n = "aes_clk", .id = 29, },
102 { .n = "trng_clk", .id = 30, },
105 static void __init at91sam9n12_pmc_setup(struct device_node *np)
107 struct clk_range range = CLK_RANGE(0, 0);
108 const char *slck_name, *mainxtal_name;
109 struct pmc_data *at91sam9n12_pmc;
110 const char *parent_names[6];
111 struct regmap *regmap;
116 i = of_property_match_string(np, "clock-names", "slow_clk");
120 slck_name = of_clk_get_parent_name(np, i);
122 i = of_property_match_string(np, "clock-names", "main_xtal");
125 mainxtal_name = of_clk_get_parent_name(np, i);
127 regmap = syscon_node_to_regmap(np);
131 at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
132 nck(at91sam9n12_systemck), 31, 0, 2);
133 if (!at91sam9n12_pmc)
136 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
141 bypass = of_property_read_bool(np, "atmel,osc-bypass");
143 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
148 parent_names[0] = "main_rc_osc";
149 parent_names[1] = "main_osc";
150 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
154 at91sam9n12_pmc->chws[PMC_MAIN] = hw;
156 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
157 &at91rm9200_pll_layout, &plla_characteristics);
161 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
165 at91sam9n12_pmc->chws[PMC_PLLACK] = hw;
167 hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
168 &at91rm9200_pll_layout, &pllb_characteristics);
172 at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;
174 parent_names[0] = slck_name;
175 parent_names[1] = "mainck";
176 parent_names[2] = "plladivck";
177 parent_names[3] = "pllbck";
178 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
179 &at91sam9x5_master_layout,
180 &mck_characteristics);
184 at91sam9n12_pmc->chws[PMC_MCK] = hw;
186 hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
190 parent_names[0] = slck_name;
191 parent_names[1] = "mainck";
192 parent_names[2] = "plladivck";
193 parent_names[3] = "pllbck";
194 parent_names[4] = "masterck";
195 for (i = 0; i < 2; i++) {
198 snprintf(name, sizeof(name), "prog%d", i);
200 hw = at91_clk_register_programmable(regmap, name,
202 &at91sam9x5_programmable_layout);
206 at91sam9n12_pmc->pchws[i] = hw;
209 for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
210 hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
211 at91sam9n12_systemck[i].p,
212 at91sam9n12_systemck[i].id);
216 at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
219 for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
220 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
221 &at91sam9n12_pcr_layout,
222 at91sam9n12_periphck[i].n,
224 at91sam9n12_periphck[i].id,
229 at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
232 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);
237 kfree(at91sam9n12_pmc);
240 * The TCB is used as the clocksource so its clock is needed early. This means
241 * this can't be a platform driver.
243 CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc",
244 at91sam9n12_pmc_setup);