drivers/char/agp/sworks-agp.c

   1 /*
   2  * Serverworks AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include "agp.h"
  10
  11 #define SVWRKS_COMMAND          0x04
  12 #define SVWRKS_APSIZE           0x10
  13 #define SVWRKS_MMBASE           0x14
  14 #define SVWRKS_CACHING          0x4b
  15 #define SVWRKS_AGP_ENABLE       0x60
  16 #define SVWRKS_FEATURE          0x68
  17
  18 #define SVWRKS_SIZE_MASK        0xfe000000
  19
  20 /* Memory mapped registers */
  21 #define SVWRKS_GART_CACHE       0x02
  22 #define SVWRKS_GATTBASE         0x04
  23 #define SVWRKS_TLBFLUSH         0x10
  24 #define SVWRKS_POSTFLUSH        0x14
  25 #define SVWRKS_DIRFLUSH         0x0c
  26
  27
  28 struct serverworks_page_map {
  29         unsigned long *real;
  30         unsigned long __iomem *remapped;
  31 };
  32
  33 static struct _serverworks_private {
  34         struct pci_dev *svrwrks_dev;    /* device one */
  35         volatile u8 __iomem *registers;
  36         struct serverworks_page_map **gatt_pages;
  37         int num_tables;
  38         struct serverworks_page_map scratch_dir;
  39
  40         int gart_addr_ofs;
  41         int mm_addr_ofs;
  42 } serverworks_private;
  43
  44 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
  45 {
  46         int i;
  47
  48         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  49         if (page_map->real == NULL) {
  50                 return -ENOMEM;
  51         }
  52         SetPageReserved(virt_to_page(page_map->real));
  53         global_cache_flush();
  54         page_map->remapped = ioremap_nocache(virt_to_gart(page_map->real),
  55                                             PAGE_SIZE);
  56         if (page_map->remapped == NULL) {
  57                 ClearPageReserved(virt_to_page(page_map->real));
  58                 free_page((unsigned long) page_map->real);
  59                 page_map->real = NULL;
  60                 return -ENOMEM;
  61         }
  62         global_cache_flush();
  63
  64         for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
  65                 writel(agp_bridge->scratch_page, page_map->remapped+i);
  66
  67         return 0;
  68 }
  69
  70 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
  71 {
  72         iounmap(page_map->remapped);
  73         ClearPageReserved(virt_to_page(page_map->real));
  74         free_page((unsigned long) page_map->real);
  75 }
  76
  77 static void serverworks_free_gatt_pages(void)
  78 {
  79         int i;
  80         struct serverworks_page_map **tables;
  81         struct serverworks_page_map *entry;
  82
  83         tables = serverworks_private.gatt_pages;
  84         for(i = 0; i < serverworks_private.num_tables; i++) {
  85                 entry = tables[i];
  86                 if (entry != NULL) {
  87                         if (entry->real != NULL) {
  88                                 serverworks_free_page_map(entry);
  89                         }
  90                         kfree(entry);
  91                 }
  92         }
  93         kfree(tables);
  94 }
  95
  96 static int serverworks_create_gatt_pages(int nr_tables)
  97 {
  98         struct serverworks_page_map **tables;
  99         struct serverworks_page_map *entry;
 100         int retval = 0;
 101         int i;
 102
 103         tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
 104                          GFP_KERNEL);
 105         if (tables == NULL)
 106                 return -ENOMEM;
 107
 108         for (i = 0; i < nr_tables; i++) {
 109                 entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
 110                 if (entry == NULL) {
 111                         retval = -ENOMEM;
 112                         break;
 113                 }
 114                 tables[i] = entry;
 115                 retval = serverworks_create_page_map(entry);
 116                 if (retval != 0) break;
 117         }
 118         serverworks_private.num_tables = nr_tables;
 119         serverworks_private.gatt_pages = tables;
 120
 121         if (retval != 0) serverworks_free_gatt_pages();
 122
 123         return retval;
 124 }
 125
 126 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
 127         GET_PAGE_DIR_IDX(addr)]->remapped)
 128
 129 #ifndef GET_PAGE_DIR_OFF
 130 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 131 #endif
 132
 133 #ifndef GET_PAGE_DIR_IDX
 134 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 135         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 136 #endif
 137
 138 #ifndef GET_GATT_OFF
 139 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 140 #endif
 141
 142 static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
 143 {
 144         struct aper_size_info_lvl2 *value;
 145         struct serverworks_page_map page_dir;
 146         int retval;
 147         u32 temp;
 148         int i;
 149
 150         value = A_SIZE_LVL2(agp_bridge->current_size);
 151         retval = serverworks_create_page_map(&page_dir);
 152         if (retval != 0) {
 153                 return retval;
 154         }
 155         retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
 156         if (retval != 0) {
 157                 serverworks_free_page_map(&page_dir);
 158                 return retval;
 159         }
 160         /* Create a fake scratch directory */
 161         for(i = 0; i < 1024; i++) {
 162                 writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
 163                 writel(virt_to_gart(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
 164         }
 165
 166         retval = serverworks_create_gatt_pages(value->num_entries / 1024);
 167         if (retval != 0) {
 168                 serverworks_free_page_map(&page_dir);
 169                 serverworks_free_page_map(&serverworks_private.scratch_dir);
 170                 return retval;
 171         }
 172
 173         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 174         agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
 175         agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);
 176
 177         /* Get the address for the gart region.
 178          * This is a bus address even on the alpha, b/c its
 179          * used to program the agp master not the cpu
 180          */
 181
 182         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 183         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 184
 185         /* Calculate the agp offset */
 186
 187         for(i = 0; i < value->num_entries / 1024; i++)
 188                 writel(virt_to_gart(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
 189
 190         return 0;
 191 }
 192
 193 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
 194 {
 195         struct serverworks_page_map page_dir;
 196
 197         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 198         page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
 199
 200         serverworks_free_gatt_pages();
 201         serverworks_free_page_map(&page_dir);
 202         serverworks_free_page_map(&serverworks_private.scratch_dir);
 203         return 0;
 204 }
 205
 206 static int serverworks_fetch_size(void)
 207 {
 208         int i;
 209         u32 temp;
 210         u32 temp2;
 211         struct aper_size_info_lvl2 *values;
 212
 213         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 214         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 215         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
 216                                         SVWRKS_SIZE_MASK);
 217         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
 218         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
 219         temp2 &= SVWRKS_SIZE_MASK;
 220
 221         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 222                 if (temp2 == values[i].size_value) {
 223                         agp_bridge->previous_size =
 224                             agp_bridge->current_size = (void *) (values + i);
 225
 226                         agp_bridge->aperture_size_idx = i;
 227                         return values[i].size;
 228                 }
 229         }
 230
 231         return 0;
 232 }
 233
 234 /*
 235  * This routine could be implemented by taking the addresses
 236  * written to the GATT, and flushing them individually.  However
 237  * currently it just flushes the whole table.  Which is probably
 238  * more efficent, since agp_memory blocks can be a large number of
 239  * entries.
 240  */
 241 static void serverworks_tlbflush(struct agp_memory *temp)
 242 {
 243         unsigned long timeout;
 244
 245         writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
 246         timeout = jiffies + 3*HZ;
 247         while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
 248                 cpu_relax();
 249                 if (time_after(jiffies, timeout)) {
 250                         printk(KERN_ERR PFX "TLB post flush took more than 3 seconds\n");
 251                         break;
 252                 }
 253         }
 254
 255         writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
 256         timeout = jiffies + 3*HZ;
 257         while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
 258                 cpu_relax();
 259                 if (time_after(jiffies, timeout)) {
 260                         printk(KERN_ERR PFX "TLB Dir flush took more than 3 seconds\n");
 261                         break;
 262                 }
 263         }
 264 }
 265
 266 static int serverworks_configure(void)
 267 {
 268         struct aper_size_info_lvl2 *current_size;
 269         u32 temp;
 270         u8 enable_reg;
 271         u16 cap_reg;
 272
 273         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 274
 275         /* Get the memory mapped registers */
 276         pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
 277         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 278         serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
 279         if (!serverworks_private.registers) {
 280                 printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
 281                 return -ENOMEM;
 282         }
 283
 284         writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
 285         readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
 286
 287         writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
 288         readl(serverworks_private.registers+SVWRKS_GATTBASE);   /* PCI Posting. */
 289
 290         cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
 291         cap_reg &= ~0x0007;
 292         cap_reg |= 0x4;
 293         writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
 294         readw(serverworks_private.registers+SVWRKS_COMMAND);
 295
 296         pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
 297         enable_reg |= 0x1; /* Agp Enable bit */
 298         pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
 299         serverworks_tlbflush(NULL);
 300
 301         agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
 302
 303         /* Fill in the mode register */
 304         pci_read_config_dword(serverworks_private.svrwrks_dev,
 305                               agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 306
 307         pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
 308         enable_reg &= ~0x3;
 309         pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
 310
 311         pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
 312         enable_reg |= (1<<6);
 313         pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
 314
 315         return 0;
 316 }
 317
 318 static void serverworks_cleanup(void)
 319 {
 320         iounmap((void __iomem *) serverworks_private.registers);
 321 }
 322
 323 static int serverworks_insert_memory(struct agp_memory *mem,
 324                              off_t pg_start, int type)
 325 {
 326         int i, j, num_entries;
 327         unsigned long __iomem *cur_gatt;
 328         unsigned long addr;
 329
 330         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 331
 332         if (type != 0 || mem->type != 0) {
 333                 return -EINVAL;
 334         }
 335         if ((pg_start + mem->page_count) > num_entries) {
 336                 return -EINVAL;
 337         }
 338
 339         j = pg_start;
 340         while (j < (pg_start + mem->page_count)) {
 341                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 342                 cur_gatt = SVRWRKS_GET_GATT(addr);
 343                 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
 344                         return -EBUSY;
 345                 j++;
 346         }
 347
 348         if (mem->is_flushed == FALSE) {
 349                 global_cache_flush();
 350                 mem->is_flushed = TRUE;
 351         }
 352
 353         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 354                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 355                 cur_gatt = SVRWRKS_GET_GATT(addr);
 356                 writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
 357         }
 358         serverworks_tlbflush(mem);
 359         return 0;
 360 }
 361
 362 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
 363                              int type)
 364 {
 365         int i;
 366         unsigned long __iomem *cur_gatt;
 367         unsigned long addr;
 368
 369         if (type != 0 || mem->type != 0) {
 370                 return -EINVAL;
 371         }
 372
 373         global_cache_flush();
 374         serverworks_tlbflush(mem);
 375
 376         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 377                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 378                 cur_gatt = SVRWRKS_GET_GATT(addr);
 379                 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
 380         }
 381
 382         serverworks_tlbflush(mem);
 383         return 0;
 384 }
 385
 386 static struct gatt_mask serverworks_masks[] =
 387 {
 388         {.mask = 1, .type = 0}
 389 };
 390
 391 static struct aper_size_info_lvl2 serverworks_sizes[7] =
 392 {
 393         {2048, 524288, 0x80000000},
 394         {1024, 262144, 0xc0000000},
 395         {512, 131072, 0xe0000000},
 396         {256, 65536, 0xf0000000},
 397         {128, 32768, 0xf8000000},
 398         {64, 16384, 0xfc000000},
 399         {32, 8192, 0xfe000000}
 400 };
 401
 402 static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 403 {
 404         u32 command;
 405
 406         pci_read_config_dword(serverworks_private.svrwrks_dev,
 407                               bridge->capndx + PCI_AGP_STATUS,
 408                               &command);
 409
 410         command = agp_collect_device_status(bridge, mode, command);
 411
 412         command &= ~0x10;       /* disable FW */
 413         command &= ~0x08;
 414
 415         command |= 0x100;
 416
 417         pci_write_config_dword(serverworks_private.svrwrks_dev,
 418                                bridge->capndx + PCI_AGP_COMMAND,
 419                                command);
 420
 421         agp_device_command(command, 0);
 422 }
 423
 424 static struct agp_bridge_driver sworks_driver = {
 425         .owner                  = THIS_MODULE,
 426         .aperture_sizes         = serverworks_sizes,
 427         .size_type              = LVL2_APER_SIZE,
 428         .num_aperture_sizes     = 7,
 429         .configure              = serverworks_configure,
 430         .fetch_size             = serverworks_fetch_size,
 431         .cleanup                = serverworks_cleanup,
 432         .tlb_flush              = serverworks_tlbflush,
 433         .mask_memory            = agp_generic_mask_memory,
 434         .masks                  = serverworks_masks,
 435         .agp_enable             = serverworks_agp_enable,
 436         .cache_flush            = global_cache_flush,
 437         .create_gatt_table      = serverworks_create_gatt_table,
 438         .free_gatt_table        = serverworks_free_gatt_table,
 439         .insert_memory          = serverworks_insert_memory,
 440         .remove_memory          = serverworks_remove_memory,
 441         .alloc_by_type          = agp_generic_alloc_by_type,
 442         .free_by_type           = agp_generic_free_by_type,
 443         .agp_alloc_page         = agp_generic_alloc_page,
 444         .agp_destroy_page       = agp_generic_destroy_page,
 445 };
 446
 447 static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
 448                                            const struct pci_device_id *ent)
 449 {
 450         struct agp_bridge_data *bridge;
 451         struct pci_dev *bridge_dev;
 452         u32 temp, temp2;
 453         u8 cap_ptr = 0;
 454
 455         /* Everything is on func 1 here so we are hardcoding function one */
 456         bridge_dev = pci_find_slot((unsigned int)pdev->bus->number,
 457                         PCI_DEVFN(0, 1));
 458         if (!bridge_dev) {
 459                 printk(KERN_INFO PFX "Detected a Serverworks chipset "
 460                        "but could not find the secondary device.\n");
 461                 return -ENODEV;
 462         }
 463
 464         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 465
 466         switch (pdev->device) {
 467         case 0x0006:
 468                 /* ServerWorks CNB20HE
 469                 Fail silently.*/
 470                 printk (KERN_ERR PFX "Detected ServerWorks CNB20HE chipset: No AGP present.\n");
 471                 return -ENODEV;
 472
 473         case PCI_DEVICE_ID_SERVERWORKS_HE:
 474         case PCI_DEVICE_ID_SERVERWORKS_LE:
 475         case 0x0007:
 476                 break;
 477
 478         default:
 479                 if (cap_ptr)
 480                         printk(KERN_ERR PFX "Unsupported Serverworks chipset "
 481                                         "(device id: %04x)\n", pdev->device);
 482                 return -ENODEV;
 483         }
 484
 485         serverworks_private.svrwrks_dev = bridge_dev;
 486         serverworks_private.gart_addr_ofs = 0x10;
 487
 488         pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
 489         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 490                 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
 491                 if (temp2 != 0) {
 492                         printk(KERN_INFO PFX "Detected 64 bit aperture address, "
 493                                "but top bits are not zero.  Disabling agp\n");
 494                         return -ENODEV;
 495                 }
 496                 serverworks_private.mm_addr_ofs = 0x18;
 497         } else
 498                 serverworks_private.mm_addr_ofs = 0x14;
 499
 500         pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
 501         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 502                 pci_read_config_dword(pdev,
 503                                 serverworks_private.mm_addr_ofs + 4, &temp2);
 504                 if (temp2 != 0) {
 505                         printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
 506                                "but top bits are not zero.  Disabling agp\n");
 507                         return -ENODEV;
 508                 }
 509         }
 510
 511         bridge = agp_alloc_bridge();
 512         if (!bridge)
 513                 return -ENOMEM;
 514
 515         bridge->driver = &sworks_driver;
 516         bridge->dev_private_data = &serverworks_private,
 517         bridge->dev = pdev;
 518
 519         pci_set_drvdata(pdev, bridge);
 520         return agp_add_bridge(bridge);
 521 }
 522
 523 static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
 524 {
 525         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 526
 527         agp_remove_bridge(bridge);
 528         agp_put_bridge(bridge);
 529 }
 530
 531 static struct pci_device_id agp_serverworks_pci_table[] = {
 532         {
 533         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 534         .class_mask     = ~0,
 535         .vendor         = PCI_VENDOR_ID_SERVERWORKS,
 536         .device         = PCI_ANY_ID,
 537         .subvendor      = PCI_ANY_ID,
 538         .subdevice      = PCI_ANY_ID,
 539         },
 540         { }
 541 };
 542
 543 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
 544
 545 static struct pci_driver agp_serverworks_pci_driver = {
 546         .owner          = THIS_MODULE,
 547         .name           = "agpgart-serverworks",
 548         .id_table       = agp_serverworks_pci_table,
 549         .probe          = agp_serverworks_probe,
 550         .remove         = agp_serverworks_remove,
 551 };
 552
 553 static int __init agp_serverworks_init(void)
 554 {
 555         if (agp_off)
 556                 return -EINVAL;
 557         return pci_register_driver(&agp_serverworks_pci_driver);
 558 }
 559
 560 static void __exit agp_serverworks_cleanup(void)
 561 {
 562         pci_unregister_driver(&agp_serverworks_pci_driver);
 563 }
 564
 565 module_init(agp_serverworks_init);
 566 module_exit(agp_serverworks_cleanup);
 567
 568 MODULE_LICENSE("GPL and additional rights");
 569