Merge tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso...
[linux-2.6-microblaze.git] / drivers / char / agp / intel-gtt.c
1 /*
2  * Intel GTT (Graphics Translation Table) routines
3  *
4  * Caveat: This driver implements the linux agp interface, but this is far from
5  * a agp driver! GTT support ended up here for purely historical reasons: The
6  * old userspace intel graphics drivers needed an interface to map memory into
7  * the GTT. And the drm provides a default interface for graphic devices sitting
8  * on an agp port. So it made sense to fake the GTT support as an agp port to
9  * avoid having to create a new api.
10  *
11  * With gem this does not make much sense anymore, just needlessly complicates
12  * the code. But as long as the old graphics stack is still support, it's stuck
13  * here.
14  *
15  * /fairy-tale-mode off
16  */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/kernel.h>
21 #include <linux/pagemap.h>
22 #include <linux/agp_backend.h>
23 #include <linux/delay.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <drm/intel-gtt.h>
28 #include <asm/set_memory.h>
29
30 /*
31  * If we have Intel graphics, we're not going to have anything other than
32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34  * Only newer chipsets need to bother with this, of course.
35  */
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 struct intel_gtt_driver {
43         unsigned int gen : 8;
44         unsigned int is_g33 : 1;
45         unsigned int is_pineview : 1;
46         unsigned int is_ironlake : 1;
47         unsigned int has_pgtbl_enable : 1;
48         unsigned int dma_mask_size : 8;
49         /* Chipset specific GTT setup */
50         int (*setup)(void);
51         /* This should undo anything done in ->setup() save the unmapping
52          * of the mmio register file, that's done in the generic code. */
53         void (*cleanup)(void);
54         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
55         /* Flags is a more or less chipset specific opaque value.
56          * For chipsets that need to support old ums (non-gem) code, this
57          * needs to be identical to the various supported agp memory types! */
58         bool (*check_flags)(unsigned int flags);
59         void (*chipset_flush)(void);
60 };
61
62 static struct _intel_private {
63         const struct intel_gtt_driver *driver;
64         struct pci_dev *pcidev; /* device one */
65         struct pci_dev *bridge_dev;
66         u8 __iomem *registers;
67         phys_addr_t gtt_phys_addr;
68         u32 PGETBL_save;
69         u32 __iomem *gtt;               /* I915G */
70         bool clear_fake_agp; /* on first access via agp, fill with scratch */
71         int num_dcache_entries;
72         void __iomem *i9xx_flush_page;
73         char *i81x_gtt_table;
74         struct resource ifp_resource;
75         int resource_valid;
76         struct page *scratch_page;
77         phys_addr_t scratch_page_dma;
78         int refcount;
79         /* Whether i915 needs to use the dmar apis or not. */
80         unsigned int needs_dmar : 1;
81         phys_addr_t gma_bus_addr;
82         /*  Size of memory reserved for graphics by the BIOS */
83         unsigned int stolen_size;
84         /* Total number of gtt entries. */
85         unsigned int gtt_total_entries;
86         /* Part of the gtt that is mappable by the cpu, for those chips where
87          * this is not the full gtt. */
88         unsigned int gtt_mappable_entries;
89 } intel_private;
90
91 #define INTEL_GTT_GEN   intel_private.driver->gen
92 #define IS_G33          intel_private.driver->is_g33
93 #define IS_PINEVIEW     intel_private.driver->is_pineview
94 #define IS_IRONLAKE     intel_private.driver->is_ironlake
95 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
96
97 #if IS_ENABLED(CONFIG_AGP_INTEL)
98 static int intel_gtt_map_memory(struct page **pages,
99                                 unsigned int num_entries,
100                                 struct sg_table *st)
101 {
102         struct scatterlist *sg;
103         int i;
104
105         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
106
107         if (sg_alloc_table(st, num_entries, GFP_KERNEL))
108                 goto err;
109
110         for_each_sg(st->sgl, sg, num_entries, i)
111                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
112
113         if (!pci_map_sg(intel_private.pcidev,
114                         st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
115                 goto err;
116
117         return 0;
118
119 err:
120         sg_free_table(st);
121         return -ENOMEM;
122 }
123
124 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
125 {
126         struct sg_table st;
127         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
128
129         pci_unmap_sg(intel_private.pcidev, sg_list,
130                      num_sg, PCI_DMA_BIDIRECTIONAL);
131
132         st.sgl = sg_list;
133         st.orig_nents = st.nents = num_sg;
134
135         sg_free_table(&st);
136 }
137
138 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
139 {
140         return;
141 }
142
143 /* Exists to support ARGB cursors */
144 static struct page *i8xx_alloc_pages(void)
145 {
146         struct page *page;
147
148         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
149         if (page == NULL)
150                 return NULL;
151
152         if (set_pages_uc(page, 4) < 0) {
153                 set_pages_wb(page, 4);
154                 __free_pages(page, 2);
155                 return NULL;
156         }
157         atomic_inc(&agp_bridge->current_memory_agp);
158         return page;
159 }
160
161 static void i8xx_destroy_pages(struct page *page)
162 {
163         if (page == NULL)
164                 return;
165
166         set_pages_wb(page, 4);
167         __free_pages(page, 2);
168         atomic_dec(&agp_bridge->current_memory_agp);
169 }
170 #endif
171
172 #define I810_GTT_ORDER 4
173 static int i810_setup(void)
174 {
175         phys_addr_t reg_addr;
176         char *gtt_table;
177
178         /* i81x does not preallocate the gtt. It's always 64kb in size. */
179         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
180         if (gtt_table == NULL)
181                 return -ENOMEM;
182         intel_private.i81x_gtt_table = gtt_table;
183
184         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
185
186         intel_private.registers = ioremap(reg_addr, KB(64));
187         if (!intel_private.registers)
188                 return -ENOMEM;
189
190         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
191                intel_private.registers+I810_PGETBL_CTL);
192
193         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
194
195         if ((readl(intel_private.registers+I810_DRAM_CTL)
196                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
197                 dev_info(&intel_private.pcidev->dev,
198                          "detected 4MB dedicated video ram\n");
199                 intel_private.num_dcache_entries = 1024;
200         }
201
202         return 0;
203 }
204
205 static void i810_cleanup(void)
206 {
207         writel(0, intel_private.registers+I810_PGETBL_CTL);
208         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
209 }
210
211 #if IS_ENABLED(CONFIG_AGP_INTEL)
212 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
213                                       int type)
214 {
215         int i;
216
217         if ((pg_start + mem->page_count)
218                         > intel_private.num_dcache_entries)
219                 return -EINVAL;
220
221         if (!mem->is_flushed)
222                 global_cache_flush();
223
224         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
225                 dma_addr_t addr = i << PAGE_SHIFT;
226                 intel_private.driver->write_entry(addr,
227                                                   i, type);
228         }
229         wmb();
230
231         return 0;
232 }
233
234 /*
235  * The i810/i830 requires a physical address to program its mouse
236  * pointer into hardware.
237  * However the Xserver still writes to it through the agp aperture.
238  */
239 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
240 {
241         struct agp_memory *new;
242         struct page *page;
243
244         switch (pg_count) {
245         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
246                 break;
247         case 4:
248                 /* kludge to get 4 physical pages for ARGB cursor */
249                 page = i8xx_alloc_pages();
250                 break;
251         default:
252                 return NULL;
253         }
254
255         if (page == NULL)
256                 return NULL;
257
258         new = agp_create_memory(pg_count);
259         if (new == NULL)
260                 return NULL;
261
262         new->pages[0] = page;
263         if (pg_count == 4) {
264                 /* kludge to get 4 physical pages for ARGB cursor */
265                 new->pages[1] = new->pages[0] + 1;
266                 new->pages[2] = new->pages[1] + 1;
267                 new->pages[3] = new->pages[2] + 1;
268         }
269         new->page_count = pg_count;
270         new->num_scratch_pages = pg_count;
271         new->type = AGP_PHYS_MEMORY;
272         new->physical = page_to_phys(new->pages[0]);
273         return new;
274 }
275
276 static void intel_i810_free_by_type(struct agp_memory *curr)
277 {
278         agp_free_key(curr->key);
279         if (curr->type == AGP_PHYS_MEMORY) {
280                 if (curr->page_count == 4)
281                         i8xx_destroy_pages(curr->pages[0]);
282                 else {
283                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
284                                                              AGP_PAGE_DESTROY_UNMAP);
285                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
286                                                              AGP_PAGE_DESTROY_FREE);
287                 }
288                 agp_free_page_array(curr);
289         }
290         kfree(curr);
291 }
292 #endif
293
294 static int intel_gtt_setup_scratch_page(void)
295 {
296         struct page *page;
297         dma_addr_t dma_addr;
298
299         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
300         if (page == NULL)
301                 return -ENOMEM;
302         set_pages_uc(page, 1);
303
304         if (intel_private.needs_dmar) {
305                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
306                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
307                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
308                         return -EINVAL;
309
310                 intel_private.scratch_page_dma = dma_addr;
311         } else
312                 intel_private.scratch_page_dma = page_to_phys(page);
313
314         intel_private.scratch_page = page;
315
316         return 0;
317 }
318
319 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
320                              unsigned int flags)
321 {
322         u32 pte_flags = I810_PTE_VALID;
323
324         switch (flags) {
325         case AGP_DCACHE_MEMORY:
326                 pte_flags |= I810_PTE_LOCAL;
327                 break;
328         case AGP_USER_CACHED_MEMORY:
329                 pte_flags |= I830_PTE_SYSTEM_CACHED;
330                 break;
331         }
332
333         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
334 }
335
336 static unsigned int intel_gtt_stolen_size(void)
337 {
338         u16 gmch_ctrl;
339         u8 rdct;
340         int local = 0;
341         static const int ddt[4] = { 0, 16, 32, 64 };
342         unsigned int stolen_size = 0;
343
344         if (INTEL_GTT_GEN == 1)
345                 return 0; /* no stolen mem on i81x */
346
347         pci_read_config_word(intel_private.bridge_dev,
348                              I830_GMCH_CTRL, &gmch_ctrl);
349
350         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
351             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
352                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
353                 case I830_GMCH_GMS_STOLEN_512:
354                         stolen_size = KB(512);
355                         break;
356                 case I830_GMCH_GMS_STOLEN_1024:
357                         stolen_size = MB(1);
358                         break;
359                 case I830_GMCH_GMS_STOLEN_8192:
360                         stolen_size = MB(8);
361                         break;
362                 case I830_GMCH_GMS_LOCAL:
363                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
364                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
365                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
366                         local = 1;
367                         break;
368                 default:
369                         stolen_size = 0;
370                         break;
371                 }
372         } else {
373                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
374                 case I855_GMCH_GMS_STOLEN_1M:
375                         stolen_size = MB(1);
376                         break;
377                 case I855_GMCH_GMS_STOLEN_4M:
378                         stolen_size = MB(4);
379                         break;
380                 case I855_GMCH_GMS_STOLEN_8M:
381                         stolen_size = MB(8);
382                         break;
383                 case I855_GMCH_GMS_STOLEN_16M:
384                         stolen_size = MB(16);
385                         break;
386                 case I855_GMCH_GMS_STOLEN_32M:
387                         stolen_size = MB(32);
388                         break;
389                 case I915_GMCH_GMS_STOLEN_48M:
390                         stolen_size = MB(48);
391                         break;
392                 case I915_GMCH_GMS_STOLEN_64M:
393                         stolen_size = MB(64);
394                         break;
395                 case G33_GMCH_GMS_STOLEN_128M:
396                         stolen_size = MB(128);
397                         break;
398                 case G33_GMCH_GMS_STOLEN_256M:
399                         stolen_size = MB(256);
400                         break;
401                 case INTEL_GMCH_GMS_STOLEN_96M:
402                         stolen_size = MB(96);
403                         break;
404                 case INTEL_GMCH_GMS_STOLEN_160M:
405                         stolen_size = MB(160);
406                         break;
407                 case INTEL_GMCH_GMS_STOLEN_224M:
408                         stolen_size = MB(224);
409                         break;
410                 case INTEL_GMCH_GMS_STOLEN_352M:
411                         stolen_size = MB(352);
412                         break;
413                 default:
414                         stolen_size = 0;
415                         break;
416                 }
417         }
418
419         if (stolen_size > 0) {
420                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
421                        stolen_size / KB(1), local ? "local" : "stolen");
422         } else {
423                 dev_info(&intel_private.bridge_dev->dev,
424                        "no pre-allocated video memory detected\n");
425                 stolen_size = 0;
426         }
427
428         return stolen_size;
429 }
430
431 static void i965_adjust_pgetbl_size(unsigned int size_flag)
432 {
433         u32 pgetbl_ctl, pgetbl_ctl2;
434
435         /* ensure that ppgtt is disabled */
436         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
437         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
438         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
439
440         /* write the new ggtt size */
441         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
442         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
443         pgetbl_ctl |= size_flag;
444         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
445 }
446
447 static unsigned int i965_gtt_total_entries(void)
448 {
449         int size;
450         u32 pgetbl_ctl;
451         u16 gmch_ctl;
452
453         pci_read_config_word(intel_private.bridge_dev,
454                              I830_GMCH_CTRL, &gmch_ctl);
455
456         if (INTEL_GTT_GEN == 5) {
457                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
458                 case G4x_GMCH_SIZE_1M:
459                 case G4x_GMCH_SIZE_VT_1M:
460                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
461                         break;
462                 case G4x_GMCH_SIZE_VT_1_5M:
463                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
464                         break;
465                 case G4x_GMCH_SIZE_2M:
466                 case G4x_GMCH_SIZE_VT_2M:
467                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
468                         break;
469                 }
470         }
471
472         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
473
474         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
475         case I965_PGETBL_SIZE_128KB:
476                 size = KB(128);
477                 break;
478         case I965_PGETBL_SIZE_256KB:
479                 size = KB(256);
480                 break;
481         case I965_PGETBL_SIZE_512KB:
482                 size = KB(512);
483                 break;
484         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
485         case I965_PGETBL_SIZE_1MB:
486                 size = KB(1024);
487                 break;
488         case I965_PGETBL_SIZE_2MB:
489                 size = KB(2048);
490                 break;
491         case I965_PGETBL_SIZE_1_5MB:
492                 size = KB(1024 + 512);
493                 break;
494         default:
495                 dev_info(&intel_private.pcidev->dev,
496                          "unknown page table size, assuming 512KB\n");
497                 size = KB(512);
498         }
499
500         return size/4;
501 }
502
503 static unsigned int intel_gtt_total_entries(void)
504 {
505         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
506                 return i965_gtt_total_entries();
507         else {
508                 /* On previous hardware, the GTT size was just what was
509                  * required to map the aperture.
510                  */
511                 return intel_private.gtt_mappable_entries;
512         }
513 }
514
515 static unsigned int intel_gtt_mappable_entries(void)
516 {
517         unsigned int aperture_size;
518
519         if (INTEL_GTT_GEN == 1) {
520                 u32 smram_miscc;
521
522                 pci_read_config_dword(intel_private.bridge_dev,
523                                       I810_SMRAM_MISCC, &smram_miscc);
524
525                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
526                                 == I810_GFX_MEM_WIN_32M)
527                         aperture_size = MB(32);
528                 else
529                         aperture_size = MB(64);
530         } else if (INTEL_GTT_GEN == 2) {
531                 u16 gmch_ctrl;
532
533                 pci_read_config_word(intel_private.bridge_dev,
534                                      I830_GMCH_CTRL, &gmch_ctrl);
535
536                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
537                         aperture_size = MB(64);
538                 else
539                         aperture_size = MB(128);
540         } else {
541                 /* 9xx supports large sizes, just look at the length */
542                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
543         }
544
545         return aperture_size >> PAGE_SHIFT;
546 }
547
548 static void intel_gtt_teardown_scratch_page(void)
549 {
550         set_pages_wb(intel_private.scratch_page, 1);
551         if (intel_private.needs_dmar)
552                 pci_unmap_page(intel_private.pcidev,
553                                intel_private.scratch_page_dma,
554                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
555         __free_page(intel_private.scratch_page);
556 }
557
558 static void intel_gtt_cleanup(void)
559 {
560         intel_private.driver->cleanup();
561
562         iounmap(intel_private.gtt);
563         iounmap(intel_private.registers);
564
565         intel_gtt_teardown_scratch_page();
566 }
567
568 /* Certain Gen5 chipsets require require idling the GPU before
569  * unmapping anything from the GTT when VT-d is enabled.
570  */
571 static inline int needs_ilk_vtd_wa(void)
572 {
573 #ifdef CONFIG_INTEL_IOMMU
574         const unsigned short gpu_devid = intel_private.pcidev->device;
575
576         /* Query intel_iommu to see if we need the workaround. Presumably that
577          * was loaded first.
578          */
579         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||
580              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
581              intel_iommu_gfx_mapped)
582                 return 1;
583 #endif
584         return 0;
585 }
586
587 static bool intel_gtt_can_wc(void)
588 {
589         if (INTEL_GTT_GEN <= 2)
590                 return false;
591
592         if (INTEL_GTT_GEN >= 6)
593                 return false;
594
595         /* Reports of major corruption with ILK vt'd enabled */
596         if (needs_ilk_vtd_wa())
597                 return false;
598
599         return true;
600 }
601
602 static int intel_gtt_init(void)
603 {
604         u32 gtt_map_size;
605         int ret, bar;
606
607         ret = intel_private.driver->setup();
608         if (ret != 0)
609                 return ret;
610
611         intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
612         intel_private.gtt_total_entries = intel_gtt_total_entries();
613
614         /* save the PGETBL reg for resume */
615         intel_private.PGETBL_save =
616                 readl(intel_private.registers+I810_PGETBL_CTL)
617                         & ~I810_PGETBL_ENABLED;
618         /* we only ever restore the register when enabling the PGTBL... */
619         if (HAS_PGTBL_EN)
620                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
621
622         dev_info(&intel_private.bridge_dev->dev,
623                         "detected gtt size: %dK total, %dK mappable\n",
624                         intel_private.gtt_total_entries * 4,
625                         intel_private.gtt_mappable_entries * 4);
626
627         gtt_map_size = intel_private.gtt_total_entries * 4;
628
629         intel_private.gtt = NULL;
630         if (intel_gtt_can_wc())
631                 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
632                                                gtt_map_size);
633         if (intel_private.gtt == NULL)
634                 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
635                                             gtt_map_size);
636         if (intel_private.gtt == NULL) {
637                 intel_private.driver->cleanup();
638                 iounmap(intel_private.registers);
639                 return -ENOMEM;
640         }
641
642 #if IS_ENABLED(CONFIG_AGP_INTEL)
643         global_cache_flush();   /* FIXME: ? */
644 #endif
645
646         intel_private.stolen_size = intel_gtt_stolen_size();
647
648         intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
649
650         ret = intel_gtt_setup_scratch_page();
651         if (ret != 0) {
652                 intel_gtt_cleanup();
653                 return ret;
654         }
655
656         if (INTEL_GTT_GEN <= 2)
657                 bar = I810_GMADR_BAR;
658         else
659                 bar = I915_GMADR_BAR;
660
661         intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
662         return 0;
663 }
664
665 #if IS_ENABLED(CONFIG_AGP_INTEL)
666 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
667         {32, 8192, 3},
668         {64, 16384, 4},
669         {128, 32768, 5},
670         {256, 65536, 6},
671         {512, 131072, 7},
672 };
673
674 static int intel_fake_agp_fetch_size(void)
675 {
676         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
677         unsigned int aper_size;
678         int i;
679
680         aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
681
682         for (i = 0; i < num_sizes; i++) {
683                 if (aper_size == intel_fake_agp_sizes[i].size) {
684                         agp_bridge->current_size =
685                                 (void *) (intel_fake_agp_sizes + i);
686                         return aper_size;
687                 }
688         }
689
690         return 0;
691 }
692 #endif
693
694 static void i830_cleanup(void)
695 {
696 }
697
698 /* The chipset_flush interface needs to get data that has already been
699  * flushed out of the CPU all the way out to main memory, because the GPU
700  * doesn't snoop those buffers.
701  *
702  * The 8xx series doesn't have the same lovely interface for flushing the
703  * chipset write buffers that the later chips do. According to the 865
704  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
705  * that buffer out, we just fill 1KB and clflush it out, on the assumption
706  * that it'll push whatever was in there out.  It appears to work.
707  */
708 static void i830_chipset_flush(void)
709 {
710         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
711
712         /* Forcibly evict everything from the CPU write buffers.
713          * clflush appears to be insufficient.
714          */
715         wbinvd_on_all_cpus();
716
717         /* Now we've only seen documents for this magic bit on 855GM,
718          * we hope it exists for the other gen2 chipsets...
719          *
720          * Also works as advertised on my 845G.
721          */
722         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
723                intel_private.registers+I830_HIC);
724
725         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
726                 if (time_after(jiffies, timeout))
727                         break;
728
729                 udelay(50);
730         }
731 }
732
733 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
734                              unsigned int flags)
735 {
736         u32 pte_flags = I810_PTE_VALID;
737
738         if (flags ==  AGP_USER_CACHED_MEMORY)
739                 pte_flags |= I830_PTE_SYSTEM_CACHED;
740
741         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
742 }
743
744 bool intel_enable_gtt(void)
745 {
746         u8 __iomem *reg;
747
748         if (INTEL_GTT_GEN == 2) {
749                 u16 gmch_ctrl;
750
751                 pci_read_config_word(intel_private.bridge_dev,
752                                      I830_GMCH_CTRL, &gmch_ctrl);
753                 gmch_ctrl |= I830_GMCH_ENABLED;
754                 pci_write_config_word(intel_private.bridge_dev,
755                                       I830_GMCH_CTRL, gmch_ctrl);
756
757                 pci_read_config_word(intel_private.bridge_dev,
758                                      I830_GMCH_CTRL, &gmch_ctrl);
759                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
760                         dev_err(&intel_private.pcidev->dev,
761                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
762                                 gmch_ctrl);
763                         return false;
764                 }
765         }
766
767         /* On the resume path we may be adjusting the PGTBL value, so
768          * be paranoid and flush all chipset write buffers...
769          */
770         if (INTEL_GTT_GEN >= 3)
771                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
772
773         reg = intel_private.registers+I810_PGETBL_CTL;
774         writel(intel_private.PGETBL_save, reg);
775         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
776                 dev_err(&intel_private.pcidev->dev,
777                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
778                         readl(reg), intel_private.PGETBL_save);
779                 return false;
780         }
781
782         if (INTEL_GTT_GEN >= 3)
783                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
784
785         return true;
786 }
787 EXPORT_SYMBOL(intel_enable_gtt);
788
789 static int i830_setup(void)
790 {
791         phys_addr_t reg_addr;
792
793         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
794
795         intel_private.registers = ioremap(reg_addr, KB(64));
796         if (!intel_private.registers)
797                 return -ENOMEM;
798
799         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
800
801         return 0;
802 }
803
804 #if IS_ENABLED(CONFIG_AGP_INTEL)
805 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
806 {
807         agp_bridge->gatt_table_real = NULL;
808         agp_bridge->gatt_table = NULL;
809         agp_bridge->gatt_bus_addr = 0;
810
811         return 0;
812 }
813
814 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
815 {
816         return 0;
817 }
818
819 static int intel_fake_agp_configure(void)
820 {
821         if (!intel_enable_gtt())
822             return -EIO;
823
824         intel_private.clear_fake_agp = true;
825         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
826
827         return 0;
828 }
829 #endif
830
831 static bool i830_check_flags(unsigned int flags)
832 {
833         switch (flags) {
834         case 0:
835         case AGP_PHYS_MEMORY:
836         case AGP_USER_CACHED_MEMORY:
837         case AGP_USER_MEMORY:
838                 return true;
839         }
840
841         return false;
842 }
843
844 void intel_gtt_insert_page(dma_addr_t addr,
845                            unsigned int pg,
846                            unsigned int flags)
847 {
848         intel_private.driver->write_entry(addr, pg, flags);
849         if (intel_private.driver->chipset_flush)
850                 intel_private.driver->chipset_flush();
851 }
852 EXPORT_SYMBOL(intel_gtt_insert_page);
853
854 void intel_gtt_insert_sg_entries(struct sg_table *st,
855                                  unsigned int pg_start,
856                                  unsigned int flags)
857 {
858         struct scatterlist *sg;
859         unsigned int len, m;
860         int i, j;
861
862         j = pg_start;
863
864         /* sg may merge pages, but we have to separate
865          * per-page addr for GTT */
866         for_each_sg(st->sgl, sg, st->nents, i) {
867                 len = sg_dma_len(sg) >> PAGE_SHIFT;
868                 for (m = 0; m < len; m++) {
869                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
870                         intel_private.driver->write_entry(addr, j, flags);
871                         j++;
872                 }
873         }
874         wmb();
875 }
876 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
877
878 #if IS_ENABLED(CONFIG_AGP_INTEL)
879 static void intel_gtt_insert_pages(unsigned int first_entry,
880                                    unsigned int num_entries,
881                                    struct page **pages,
882                                    unsigned int flags)
883 {
884         int i, j;
885
886         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
887                 dma_addr_t addr = page_to_phys(pages[i]);
888                 intel_private.driver->write_entry(addr,
889                                                   j, flags);
890         }
891         wmb();
892 }
893
894 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
895                                          off_t pg_start, int type)
896 {
897         int ret = -EINVAL;
898
899         if (intel_private.clear_fake_agp) {
900                 int start = intel_private.stolen_size / PAGE_SIZE;
901                 int end = intel_private.gtt_mappable_entries;
902                 intel_gtt_clear_range(start, end - start);
903                 intel_private.clear_fake_agp = false;
904         }
905
906         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
907                 return i810_insert_dcache_entries(mem, pg_start, type);
908
909         if (mem->page_count == 0)
910                 goto out;
911
912         if (pg_start + mem->page_count > intel_private.gtt_total_entries)
913                 goto out_err;
914
915         if (type != mem->type)
916                 goto out_err;
917
918         if (!intel_private.driver->check_flags(type))
919                 goto out_err;
920
921         if (!mem->is_flushed)
922                 global_cache_flush();
923
924         if (intel_private.needs_dmar) {
925                 struct sg_table st;
926
927                 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
928                 if (ret != 0)
929                         return ret;
930
931                 intel_gtt_insert_sg_entries(&st, pg_start, type);
932                 mem->sg_list = st.sgl;
933                 mem->num_sg = st.nents;
934         } else
935                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
936                                        type);
937
938 out:
939         ret = 0;
940 out_err:
941         mem->is_flushed = true;
942         return ret;
943 }
944 #endif
945
946 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
947 {
948         unsigned int i;
949
950         for (i = first_entry; i < (first_entry + num_entries); i++) {
951                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
952                                                   i, 0);
953         }
954         wmb();
955 }
956 EXPORT_SYMBOL(intel_gtt_clear_range);
957
958 #if IS_ENABLED(CONFIG_AGP_INTEL)
959 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
960                                          off_t pg_start, int type)
961 {
962         if (mem->page_count == 0)
963                 return 0;
964
965         intel_gtt_clear_range(pg_start, mem->page_count);
966
967         if (intel_private.needs_dmar) {
968                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
969                 mem->sg_list = NULL;
970                 mem->num_sg = 0;
971         }
972
973         return 0;
974 }
975
976 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
977                                                        int type)
978 {
979         struct agp_memory *new;
980
981         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
982                 if (pg_count != intel_private.num_dcache_entries)
983                         return NULL;
984
985                 new = agp_create_memory(1);
986                 if (new == NULL)
987                         return NULL;
988
989                 new->type = AGP_DCACHE_MEMORY;
990                 new->page_count = pg_count;
991                 new->num_scratch_pages = 0;
992                 agp_free_page_array(new);
993                 return new;
994         }
995         if (type == AGP_PHYS_MEMORY)
996                 return alloc_agpphysmem_i8xx(pg_count, type);
997         /* always return NULL for other allocation types for now */
998         return NULL;
999 }
1000 #endif
1001
1002 static int intel_alloc_chipset_flush_resource(void)
1003 {
1004         int ret;
1005         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1006                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1007                                      pcibios_align_resource, intel_private.bridge_dev);
1008
1009         return ret;
1010 }
1011
1012 static void intel_i915_setup_chipset_flush(void)
1013 {
1014         int ret;
1015         u32 temp;
1016
1017         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1018         if (!(temp & 0x1)) {
1019                 intel_alloc_chipset_flush_resource();
1020                 intel_private.resource_valid = 1;
1021                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1022         } else {
1023                 temp &= ~1;
1024
1025                 intel_private.resource_valid = 1;
1026                 intel_private.ifp_resource.start = temp;
1027                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1028                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1029                 /* some BIOSes reserve this area in a pnp some don't */
1030                 if (ret)
1031                         intel_private.resource_valid = 0;
1032         }
1033 }
1034
1035 static void intel_i965_g33_setup_chipset_flush(void)
1036 {
1037         u32 temp_hi, temp_lo;
1038         int ret;
1039
1040         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1041         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1042
1043         if (!(temp_lo & 0x1)) {
1044
1045                 intel_alloc_chipset_flush_resource();
1046
1047                 intel_private.resource_valid = 1;
1048                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1049                         upper_32_bits(intel_private.ifp_resource.start));
1050                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1051         } else {
1052                 u64 l64;
1053
1054                 temp_lo &= ~0x1;
1055                 l64 = ((u64)temp_hi << 32) | temp_lo;
1056
1057                 intel_private.resource_valid = 1;
1058                 intel_private.ifp_resource.start = l64;
1059                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1060                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1061                 /* some BIOSes reserve this area in a pnp some don't */
1062                 if (ret)
1063                         intel_private.resource_valid = 0;
1064         }
1065 }
1066
1067 static void intel_i9xx_setup_flush(void)
1068 {
1069         /* return if already configured */
1070         if (intel_private.ifp_resource.start)
1071                 return;
1072
1073         if (INTEL_GTT_GEN == 6)
1074                 return;
1075
1076         /* setup a resource for this object */
1077         intel_private.ifp_resource.name = "Intel Flush Page";
1078         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1079
1080         /* Setup chipset flush for 915 */
1081         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1082                 intel_i965_g33_setup_chipset_flush();
1083         } else {
1084                 intel_i915_setup_chipset_flush();
1085         }
1086
1087         if (intel_private.ifp_resource.start)
1088                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1089         if (!intel_private.i9xx_flush_page)
1090                 dev_err(&intel_private.pcidev->dev,
1091                         "can't ioremap flush page - no chipset flushing\n");
1092 }
1093
1094 static void i9xx_cleanup(void)
1095 {
1096         if (intel_private.i9xx_flush_page)
1097                 iounmap(intel_private.i9xx_flush_page);
1098         if (intel_private.resource_valid)
1099                 release_resource(&intel_private.ifp_resource);
1100         intel_private.ifp_resource.start = 0;
1101         intel_private.resource_valid = 0;
1102 }
1103
1104 static void i9xx_chipset_flush(void)
1105 {
1106         if (intel_private.i9xx_flush_page)
1107                 writel(1, intel_private.i9xx_flush_page);
1108 }
1109
1110 static void i965_write_entry(dma_addr_t addr,
1111                              unsigned int entry,
1112                              unsigned int flags)
1113 {
1114         u32 pte_flags;
1115
1116         pte_flags = I810_PTE_VALID;
1117         if (flags == AGP_USER_CACHED_MEMORY)
1118                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1119
1120         /* Shift high bits down */
1121         addr |= (addr >> 28) & 0xf0;
1122         writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1123 }
1124
1125 static int i9xx_setup(void)
1126 {
1127         phys_addr_t reg_addr;
1128         int size = KB(512);
1129
1130         reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1131
1132         intel_private.registers = ioremap(reg_addr, size);
1133         if (!intel_private.registers)
1134                 return -ENOMEM;
1135
1136         switch (INTEL_GTT_GEN) {
1137         case 3:
1138                 intel_private.gtt_phys_addr =
1139                         pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1140                 break;
1141         case 5:
1142                 intel_private.gtt_phys_addr = reg_addr + MB(2);
1143                 break;
1144         default:
1145                 intel_private.gtt_phys_addr = reg_addr + KB(512);
1146                 break;
1147         }
1148
1149         intel_i9xx_setup_flush();
1150
1151         return 0;
1152 }
1153
1154 #if IS_ENABLED(CONFIG_AGP_INTEL)
1155 static const struct agp_bridge_driver intel_fake_agp_driver = {
1156         .owner                  = THIS_MODULE,
1157         .size_type              = FIXED_APER_SIZE,
1158         .aperture_sizes         = intel_fake_agp_sizes,
1159         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1160         .configure              = intel_fake_agp_configure,
1161         .fetch_size             = intel_fake_agp_fetch_size,
1162         .cleanup                = intel_gtt_cleanup,
1163         .agp_enable             = intel_fake_agp_enable,
1164         .cache_flush            = global_cache_flush,
1165         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1166         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1167         .insert_memory          = intel_fake_agp_insert_entries,
1168         .remove_memory          = intel_fake_agp_remove_entries,
1169         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1170         .free_by_type           = intel_i810_free_by_type,
1171         .agp_alloc_page         = agp_generic_alloc_page,
1172         .agp_alloc_pages        = agp_generic_alloc_pages,
1173         .agp_destroy_page       = agp_generic_destroy_page,
1174         .agp_destroy_pages      = agp_generic_destroy_pages,
1175 };
1176 #endif
1177
1178 static const struct intel_gtt_driver i81x_gtt_driver = {
1179         .gen = 1,
1180         .has_pgtbl_enable = 1,
1181         .dma_mask_size = 32,
1182         .setup = i810_setup,
1183         .cleanup = i810_cleanup,
1184         .check_flags = i830_check_flags,
1185         .write_entry = i810_write_entry,
1186 };
1187 static const struct intel_gtt_driver i8xx_gtt_driver = {
1188         .gen = 2,
1189         .has_pgtbl_enable = 1,
1190         .setup = i830_setup,
1191         .cleanup = i830_cleanup,
1192         .write_entry = i830_write_entry,
1193         .dma_mask_size = 32,
1194         .check_flags = i830_check_flags,
1195         .chipset_flush = i830_chipset_flush,
1196 };
1197 static const struct intel_gtt_driver i915_gtt_driver = {
1198         .gen = 3,
1199         .has_pgtbl_enable = 1,
1200         .setup = i9xx_setup,
1201         .cleanup = i9xx_cleanup,
1202         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1203         .write_entry = i830_write_entry,
1204         .dma_mask_size = 32,
1205         .check_flags = i830_check_flags,
1206         .chipset_flush = i9xx_chipset_flush,
1207 };
1208 static const struct intel_gtt_driver g33_gtt_driver = {
1209         .gen = 3,
1210         .is_g33 = 1,
1211         .setup = i9xx_setup,
1212         .cleanup = i9xx_cleanup,
1213         .write_entry = i965_write_entry,
1214         .dma_mask_size = 36,
1215         .check_flags = i830_check_flags,
1216         .chipset_flush = i9xx_chipset_flush,
1217 };
1218 static const struct intel_gtt_driver pineview_gtt_driver = {
1219         .gen = 3,
1220         .is_pineview = 1, .is_g33 = 1,
1221         .setup = i9xx_setup,
1222         .cleanup = i9xx_cleanup,
1223         .write_entry = i965_write_entry,
1224         .dma_mask_size = 36,
1225         .check_flags = i830_check_flags,
1226         .chipset_flush = i9xx_chipset_flush,
1227 };
1228 static const struct intel_gtt_driver i965_gtt_driver = {
1229         .gen = 4,
1230         .has_pgtbl_enable = 1,
1231         .setup = i9xx_setup,
1232         .cleanup = i9xx_cleanup,
1233         .write_entry = i965_write_entry,
1234         .dma_mask_size = 36,
1235         .check_flags = i830_check_flags,
1236         .chipset_flush = i9xx_chipset_flush,
1237 };
1238 static const struct intel_gtt_driver g4x_gtt_driver = {
1239         .gen = 5,
1240         .setup = i9xx_setup,
1241         .cleanup = i9xx_cleanup,
1242         .write_entry = i965_write_entry,
1243         .dma_mask_size = 36,
1244         .check_flags = i830_check_flags,
1245         .chipset_flush = i9xx_chipset_flush,
1246 };
1247 static const struct intel_gtt_driver ironlake_gtt_driver = {
1248         .gen = 5,
1249         .is_ironlake = 1,
1250         .setup = i9xx_setup,
1251         .cleanup = i9xx_cleanup,
1252         .write_entry = i965_write_entry,
1253         .dma_mask_size = 36,
1254         .check_flags = i830_check_flags,
1255         .chipset_flush = i9xx_chipset_flush,
1256 };
1257
1258 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1259  * driver and gmch_driver must be non-null, and find_gmch will determine
1260  * which one should be used if a gmch_chip_id is present.
1261  */
1262 static const struct intel_gtt_driver_description {
1263         unsigned int gmch_chip_id;
1264         char *name;
1265         const struct intel_gtt_driver *gtt_driver;
1266 } intel_gtt_chipsets[] = {
1267         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1268                 &i81x_gtt_driver},
1269         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1270                 &i81x_gtt_driver},
1271         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1272                 &i81x_gtt_driver},
1273         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1274                 &i81x_gtt_driver},
1275         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1276                 &i8xx_gtt_driver},
1277         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1278                 &i8xx_gtt_driver},
1279         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1280                 &i8xx_gtt_driver},
1281         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1282                 &i8xx_gtt_driver},
1283         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1284                 &i8xx_gtt_driver},
1285         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1286                 &i915_gtt_driver },
1287         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1288                 &i915_gtt_driver },
1289         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1290                 &i915_gtt_driver },
1291         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1292                 &i915_gtt_driver },
1293         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1294                 &i915_gtt_driver },
1295         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1296                 &i915_gtt_driver },
1297         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1298                 &i965_gtt_driver },
1299         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1300                 &i965_gtt_driver },
1301         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1302                 &i965_gtt_driver },
1303         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1304                 &i965_gtt_driver },
1305         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1306                 &i965_gtt_driver },
1307         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1308                 &i965_gtt_driver },
1309         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1310                 &g33_gtt_driver },
1311         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1312                 &g33_gtt_driver },
1313         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1314                 &g33_gtt_driver },
1315         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1316                 &pineview_gtt_driver },
1317         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1318                 &pineview_gtt_driver },
1319         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1320                 &g4x_gtt_driver },
1321         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1322                 &g4x_gtt_driver },
1323         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1324                 &g4x_gtt_driver },
1325         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1326                 &g4x_gtt_driver },
1327         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1328                 &g4x_gtt_driver },
1329         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1330                 &g4x_gtt_driver },
1331         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1332                 &g4x_gtt_driver },
1333         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1334             "HD Graphics", &ironlake_gtt_driver },
1335         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1336             "HD Graphics", &ironlake_gtt_driver },
1337         { 0, NULL, NULL }
1338 };
1339
1340 static int find_gmch(u16 device)
1341 {
1342         struct pci_dev *gmch_device;
1343
1344         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1345         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1346                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1347                                              device, gmch_device);
1348         }
1349
1350         if (!gmch_device)
1351                 return 0;
1352
1353         intel_private.pcidev = gmch_device;
1354         return 1;
1355 }
1356
1357 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1358                      struct agp_bridge_data *bridge)
1359 {
1360         int i, mask;
1361
1362         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1363                 if (gpu_pdev) {
1364                         if (gpu_pdev->device ==
1365                             intel_gtt_chipsets[i].gmch_chip_id) {
1366                                 intel_private.pcidev = pci_dev_get(gpu_pdev);
1367                                 intel_private.driver =
1368                                         intel_gtt_chipsets[i].gtt_driver;
1369
1370                                 break;
1371                         }
1372                 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1373                         intel_private.driver =
1374                                 intel_gtt_chipsets[i].gtt_driver;
1375                         break;
1376                 }
1377         }
1378
1379         if (!intel_private.driver)
1380                 return 0;
1381
1382 #if IS_ENABLED(CONFIG_AGP_INTEL)
1383         if (bridge) {
1384                 if (INTEL_GTT_GEN > 1)
1385                         return 0;
1386
1387                 bridge->driver = &intel_fake_agp_driver;
1388                 bridge->dev_private_data = &intel_private;
1389                 bridge->dev = bridge_pdev;
1390         }
1391 #endif
1392
1393
1394         /*
1395          * Can be called from the fake agp driver but also directly from
1396          * drm/i915.ko. Hence we need to check whether everything is set up
1397          * already.
1398          */
1399         if (intel_private.refcount++)
1400                 return 1;
1401
1402         intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1403
1404         dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1405
1406         mask = intel_private.driver->dma_mask_size;
1407         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1408                 dev_err(&intel_private.pcidev->dev,
1409                         "set gfx device dma mask %d-bit failed!\n", mask);
1410         else
1411                 pci_set_consistent_dma_mask(intel_private.pcidev,
1412                                             DMA_BIT_MASK(mask));
1413
1414         if (intel_gtt_init() != 0) {
1415                 intel_gmch_remove();
1416
1417                 return 0;
1418         }
1419
1420         return 1;
1421 }
1422 EXPORT_SYMBOL(intel_gmch_probe);
1423
1424 void intel_gtt_get(u64 *gtt_total,
1425                    u32 *stolen_size,
1426                    phys_addr_t *mappable_base,
1427                    u64 *mappable_end)
1428 {
1429         *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1430         *stolen_size = intel_private.stolen_size;
1431         *mappable_base = intel_private.gma_bus_addr;
1432         *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1433 }
1434 EXPORT_SYMBOL(intel_gtt_get);
1435
1436 void intel_gtt_chipset_flush(void)
1437 {
1438         if (intel_private.driver->chipset_flush)
1439                 intel_private.driver->chipset_flush();
1440 }
1441 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1442
1443 void intel_gmch_remove(void)
1444 {
1445         if (--intel_private.refcount)
1446                 return;
1447
1448         if (intel_private.scratch_page)
1449                 intel_gtt_teardown_scratch_page();
1450         if (intel_private.pcidev)
1451                 pci_dev_put(intel_private.pcidev);
1452         if (intel_private.bridge_dev)
1453                 pci_dev_put(intel_private.bridge_dev);
1454         intel_private.driver = NULL;
1455 }
1456 EXPORT_SYMBOL(intel_gmch_remove);
1457
1458 MODULE_AUTHOR("Dave Jones, Various @Intel");
1459 MODULE_LICENSE("GPL and additional rights");