drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <linux/delay.h>
  25 #include <asm/smp.h>
  26 #include "agp.h"
  27 #include "intel-agp.h"
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_INTEL_IOMMU
  37 #define USE_PCI_DMA_API 1
  38 #else
  39 #define USE_PCI_DMA_API 0
  40 #endif
  41
  42 struct intel_gtt_driver {
  43         unsigned int gen : 8;
  44         unsigned int is_g33 : 1;
  45         unsigned int is_pineview : 1;
  46         unsigned int is_ironlake : 1;
  47         unsigned int has_pgtbl_enable : 1;
  48         unsigned int dma_mask_size : 8;
  49         /* Chipset specific GTT setup */
  50         int (*setup)(void);
  51         /* This should undo anything done in ->setup() save the unmapping
  52          * of the mmio register file, that's done in the generic code. */
  53         void (*cleanup)(void);
  54         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  55         /* Flags is a more or less chipset specific opaque value.
  56          * For chipsets that need to support old ums (non-gem) code, this
  57          * needs to be identical to the various supported agp memory types! */
  58         bool (*check_flags)(unsigned int flags);
  59         void (*chipset_flush)(void);
  60 };
  61
  62 static struct _intel_private {
  63         struct intel_gtt base;
  64         const struct intel_gtt_driver *driver;
  65         struct pci_dev *pcidev; /* device one */
  66         struct pci_dev *bridge_dev;
  67         u8 __iomem *registers;
  68         phys_addr_t gtt_bus_addr;
  69         u32 PGETBL_save;
  70         u32 __iomem *gtt;               /* I915G */
  71         bool clear_fake_agp; /* on first access via agp, fill with scratch */
  72         int num_dcache_entries;
  73         void __iomem *i9xx_flush_page;
  74         char *i81x_gtt_table;
  75         struct resource ifp_resource;
  76         int resource_valid;
  77         struct page *scratch_page;
  78 } intel_private;
  79
  80 #define INTEL_GTT_GEN   intel_private.driver->gen
  81 #define IS_G33          intel_private.driver->is_g33
  82 #define IS_PINEVIEW     intel_private.driver->is_pineview
  83 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  84 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  85
  86 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
  87                          struct scatterlist **sg_list, int *num_sg)
  88 {
  89         struct sg_table st;
  90         struct scatterlist *sg;
  91         int i;
  92
  93         if (*sg_list)
  94                 return 0; /* already mapped (for e.g. resume */
  95
  96         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
  97
  98         if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
  99                 goto err;
 100
 101         *sg_list = sg = st.sgl;
 102
 103         for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
 104                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
 105
 106         *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
 107                                  num_entries, PCI_DMA_BIDIRECTIONAL);
 108         if (unlikely(!*num_sg))
 109                 goto err;
 110
 111         return 0;
 112
 113 err:
 114         sg_free_table(&st);
 115         return -ENOMEM;
 116 }
 117 EXPORT_SYMBOL(intel_gtt_map_memory);
 118
 119 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
 120 {
 121         struct sg_table st;
 122         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 123
 124         pci_unmap_sg(intel_private.pcidev, sg_list,
 125                      num_sg, PCI_DMA_BIDIRECTIONAL);
 126
 127         st.sgl = sg_list;
 128         st.orig_nents = st.nents = num_sg;
 129
 130         sg_free_table(&st);
 131 }
 132 EXPORT_SYMBOL(intel_gtt_unmap_memory);
 133
 134 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 135 {
 136         return;
 137 }
 138
 139 /* Exists to support ARGB cursors */
 140 static struct page *i8xx_alloc_pages(void)
 141 {
 142         struct page *page;
 143
 144         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 145         if (page == NULL)
 146                 return NULL;
 147
 148         if (set_pages_uc(page, 4) < 0) {
 149                 set_pages_wb(page, 4);
 150                 __free_pages(page, 2);
 151                 return NULL;
 152         }
 153         get_page(page);
 154         atomic_inc(&agp_bridge->current_memory_agp);
 155         return page;
 156 }
 157
 158 static void i8xx_destroy_pages(struct page *page)
 159 {
 160         if (page == NULL)
 161                 return;
 162
 163         set_pages_wb(page, 4);
 164         put_page(page);
 165         __free_pages(page, 2);
 166         atomic_dec(&agp_bridge->current_memory_agp);
 167 }
 168
 169 #define I810_GTT_ORDER 4
 170 static int i810_setup(void)
 171 {
 172         u32 reg_addr;
 173         char *gtt_table;
 174
 175         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 176         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 177         if (gtt_table == NULL)
 178                 return -ENOMEM;
 179         intel_private.i81x_gtt_table = gtt_table;
 180
 181         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 182         reg_addr &= 0xfff80000;
 183
 184         intel_private.registers = ioremap(reg_addr, KB(64));
 185         if (!intel_private.registers)
 186                 return -ENOMEM;
 187
 188         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 189                intel_private.registers+I810_PGETBL_CTL);
 190
 191         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 192
 193         if ((readl(intel_private.registers+I810_DRAM_CTL)
 194                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 195                 dev_info(&intel_private.pcidev->dev,
 196                          "detected 4MB dedicated video ram\n");
 197                 intel_private.num_dcache_entries = 1024;
 198         }
 199
 200         return 0;
 201 }
 202
 203 static void i810_cleanup(void)
 204 {
 205         writel(0, intel_private.registers+I810_PGETBL_CTL);
 206         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 207 }
 208
 209 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 210                                       int type)
 211 {
 212         int i;
 213
 214         if ((pg_start + mem->page_count)
 215                         > intel_private.num_dcache_entries)
 216                 return -EINVAL;
 217
 218         if (!mem->is_flushed)
 219                 global_cache_flush();
 220
 221         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 222                 dma_addr_t addr = i << PAGE_SHIFT;
 223                 intel_private.driver->write_entry(addr,
 224                                                   i, type);
 225         }
 226         readl(intel_private.gtt+i-1);
 227
 228         return 0;
 229 }
 230
 231 /*
 232  * The i810/i830 requires a physical address to program its mouse
 233  * pointer into hardware.
 234  * However the Xserver still writes to it through the agp aperture.
 235  */
 236 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 237 {
 238         struct agp_memory *new;
 239         struct page *page;
 240
 241         switch (pg_count) {
 242         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 243                 break;
 244         case 4:
 245                 /* kludge to get 4 physical pages for ARGB cursor */
 246                 page = i8xx_alloc_pages();
 247                 break;
 248         default:
 249                 return NULL;
 250         }
 251
 252         if (page == NULL)
 253                 return NULL;
 254
 255         new = agp_create_memory(pg_count);
 256         if (new == NULL)
 257                 return NULL;
 258
 259         new->pages[0] = page;
 260         if (pg_count == 4) {
 261                 /* kludge to get 4 physical pages for ARGB cursor */
 262                 new->pages[1] = new->pages[0] + 1;
 263                 new->pages[2] = new->pages[1] + 1;
 264                 new->pages[3] = new->pages[2] + 1;
 265         }
 266         new->page_count = pg_count;
 267         new->num_scratch_pages = pg_count;
 268         new->type = AGP_PHYS_MEMORY;
 269         new->physical = page_to_phys(new->pages[0]);
 270         return new;
 271 }
 272
 273 static void intel_i810_free_by_type(struct agp_memory *curr)
 274 {
 275         agp_free_key(curr->key);
 276         if (curr->type == AGP_PHYS_MEMORY) {
 277                 if (curr->page_count == 4)
 278                         i8xx_destroy_pages(curr->pages[0]);
 279                 else {
 280                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 281                                                              AGP_PAGE_DESTROY_UNMAP);
 282                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 283                                                              AGP_PAGE_DESTROY_FREE);
 284                 }
 285                 agp_free_page_array(curr);
 286         }
 287         kfree(curr);
 288 }
 289
 290 static int intel_gtt_setup_scratch_page(void)
 291 {
 292         struct page *page;
 293         dma_addr_t dma_addr;
 294
 295         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 296         if (page == NULL)
 297                 return -ENOMEM;
 298         get_page(page);
 299         set_pages_uc(page, 1);
 300
 301         if (intel_private.base.needs_dmar) {
 302                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 303                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 304                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 305                         return -EINVAL;
 306
 307                 intel_private.base.scratch_page_dma = dma_addr;
 308         } else
 309                 intel_private.base.scratch_page_dma = page_to_phys(page);
 310
 311         intel_private.scratch_page = page;
 312
 313         return 0;
 314 }
 315
 316 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 317                              unsigned int flags)
 318 {
 319         u32 pte_flags = I810_PTE_VALID;
 320
 321         switch (flags) {
 322         case AGP_DCACHE_MEMORY:
 323                 pte_flags |= I810_PTE_LOCAL;
 324                 break;
 325         case AGP_USER_CACHED_MEMORY:
 326                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 327                 break;
 328         }
 329
 330         writel(addr | pte_flags, intel_private.gtt + entry);
 331 }
 332
 333 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
 334         {32, 8192, 3},
 335         {64, 16384, 4},
 336         {128, 32768, 5},
 337         {256, 65536, 6},
 338         {512, 131072, 7},
 339 };
 340
 341 static unsigned int intel_gtt_stolen_size(void)
 342 {
 343         u16 gmch_ctrl;
 344         u8 rdct;
 345         int local = 0;
 346         static const int ddt[4] = { 0, 16, 32, 64 };
 347         unsigned int stolen_size = 0;
 348
 349         if (INTEL_GTT_GEN == 1)
 350                 return 0; /* no stolen mem on i81x */
 351
 352         pci_read_config_word(intel_private.bridge_dev,
 353                              I830_GMCH_CTRL, &gmch_ctrl);
 354
 355         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 356             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 357                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 358                 case I830_GMCH_GMS_STOLEN_512:
 359                         stolen_size = KB(512);
 360                         break;
 361                 case I830_GMCH_GMS_STOLEN_1024:
 362                         stolen_size = MB(1);
 363                         break;
 364                 case I830_GMCH_GMS_STOLEN_8192:
 365                         stolen_size = MB(8);
 366                         break;
 367                 case I830_GMCH_GMS_LOCAL:
 368                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 369                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 370                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 371                         local = 1;
 372                         break;
 373                 default:
 374                         stolen_size = 0;
 375                         break;
 376                 }
 377         } else if (INTEL_GTT_GEN == 6) {
 378                 /*
 379                  * SandyBridge has new memory control reg at 0x50.w
 380                  */
 381                 u16 snb_gmch_ctl;
 382                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 383                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 384                 case SNB_GMCH_GMS_STOLEN_32M:
 385                         stolen_size = MB(32);
 386                         break;
 387                 case SNB_GMCH_GMS_STOLEN_64M:
 388                         stolen_size = MB(64);
 389                         break;
 390                 case SNB_GMCH_GMS_STOLEN_96M:
 391                         stolen_size = MB(96);
 392                         break;
 393                 case SNB_GMCH_GMS_STOLEN_128M:
 394                         stolen_size = MB(128);
 395                         break;
 396                 case SNB_GMCH_GMS_STOLEN_160M:
 397                         stolen_size = MB(160);
 398                         break;
 399                 case SNB_GMCH_GMS_STOLEN_192M:
 400                         stolen_size = MB(192);
 401                         break;
 402                 case SNB_GMCH_GMS_STOLEN_224M:
 403                         stolen_size = MB(224);
 404                         break;
 405                 case SNB_GMCH_GMS_STOLEN_256M:
 406                         stolen_size = MB(256);
 407                         break;
 408                 case SNB_GMCH_GMS_STOLEN_288M:
 409                         stolen_size = MB(288);
 410                         break;
 411                 case SNB_GMCH_GMS_STOLEN_320M:
 412                         stolen_size = MB(320);
 413                         break;
 414                 case SNB_GMCH_GMS_STOLEN_352M:
 415                         stolen_size = MB(352);
 416                         break;
 417                 case SNB_GMCH_GMS_STOLEN_384M:
 418                         stolen_size = MB(384);
 419                         break;
 420                 case SNB_GMCH_GMS_STOLEN_416M:
 421                         stolen_size = MB(416);
 422                         break;
 423                 case SNB_GMCH_GMS_STOLEN_448M:
 424                         stolen_size = MB(448);
 425                         break;
 426                 case SNB_GMCH_GMS_STOLEN_480M:
 427                         stolen_size = MB(480);
 428                         break;
 429                 case SNB_GMCH_GMS_STOLEN_512M:
 430                         stolen_size = MB(512);
 431                         break;
 432                 }
 433         } else {
 434                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 435                 case I855_GMCH_GMS_STOLEN_1M:
 436                         stolen_size = MB(1);
 437                         break;
 438                 case I855_GMCH_GMS_STOLEN_4M:
 439                         stolen_size = MB(4);
 440                         break;
 441                 case I855_GMCH_GMS_STOLEN_8M:
 442                         stolen_size = MB(8);
 443                         break;
 444                 case I855_GMCH_GMS_STOLEN_16M:
 445                         stolen_size = MB(16);
 446                         break;
 447                 case I855_GMCH_GMS_STOLEN_32M:
 448                         stolen_size = MB(32);
 449                         break;
 450                 case I915_GMCH_GMS_STOLEN_48M:
 451                         stolen_size = MB(48);
 452                         break;
 453                 case I915_GMCH_GMS_STOLEN_64M:
 454                         stolen_size = MB(64);
 455                         break;
 456                 case G33_GMCH_GMS_STOLEN_128M:
 457                         stolen_size = MB(128);
 458                         break;
 459                 case G33_GMCH_GMS_STOLEN_256M:
 460                         stolen_size = MB(256);
 461                         break;
 462                 case INTEL_GMCH_GMS_STOLEN_96M:
 463                         stolen_size = MB(96);
 464                         break;
 465                 case INTEL_GMCH_GMS_STOLEN_160M:
 466                         stolen_size = MB(160);
 467                         break;
 468                 case INTEL_GMCH_GMS_STOLEN_224M:
 469                         stolen_size = MB(224);
 470                         break;
 471                 case INTEL_GMCH_GMS_STOLEN_352M:
 472                         stolen_size = MB(352);
 473                         break;
 474                 default:
 475                         stolen_size = 0;
 476                         break;
 477                 }
 478         }
 479
 480         if (stolen_size > 0) {
 481                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 482                        stolen_size / KB(1), local ? "local" : "stolen");
 483         } else {
 484                 dev_info(&intel_private.bridge_dev->dev,
 485                        "no pre-allocated video memory detected\n");
 486                 stolen_size = 0;
 487         }
 488
 489         return stolen_size;
 490 }
 491
 492 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 493 {
 494         u32 pgetbl_ctl, pgetbl_ctl2;
 495
 496         /* ensure that ppgtt is disabled */
 497         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 498         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 499         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 500
 501         /* write the new ggtt size */
 502         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 503         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 504         pgetbl_ctl |= size_flag;
 505         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 506 }
 507
 508 static unsigned int i965_gtt_total_entries(void)
 509 {
 510         int size;
 511         u32 pgetbl_ctl;
 512         u16 gmch_ctl;
 513
 514         pci_read_config_word(intel_private.bridge_dev,
 515                              I830_GMCH_CTRL, &gmch_ctl);
 516
 517         if (INTEL_GTT_GEN == 5) {
 518                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 519                 case G4x_GMCH_SIZE_1M:
 520                 case G4x_GMCH_SIZE_VT_1M:
 521                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 522                         break;
 523                 case G4x_GMCH_SIZE_VT_1_5M:
 524                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 525                         break;
 526                 case G4x_GMCH_SIZE_2M:
 527                 case G4x_GMCH_SIZE_VT_2M:
 528                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 529                         break;
 530                 }
 531         }
 532
 533         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 534
 535         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 536         case I965_PGETBL_SIZE_128KB:
 537                 size = KB(128);
 538                 break;
 539         case I965_PGETBL_SIZE_256KB:
 540                 size = KB(256);
 541                 break;
 542         case I965_PGETBL_SIZE_512KB:
 543                 size = KB(512);
 544                 break;
 545         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 546         case I965_PGETBL_SIZE_1MB:
 547                 size = KB(1024);
 548                 break;
 549         case I965_PGETBL_SIZE_2MB:
 550                 size = KB(2048);
 551                 break;
 552         case I965_PGETBL_SIZE_1_5MB:
 553                 size = KB(1024 + 512);
 554                 break;
 555         default:
 556                 dev_info(&intel_private.pcidev->dev,
 557                          "unknown page table size, assuming 512KB\n");
 558                 size = KB(512);
 559         }
 560
 561         return size/4;
 562 }
 563
 564 static unsigned int intel_gtt_total_entries(void)
 565 {
 566         int size;
 567
 568         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 569                 return i965_gtt_total_entries();
 570         else if (INTEL_GTT_GEN == 6) {
 571                 u16 snb_gmch_ctl;
 572
 573                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 574                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
 575                 default:
 576                 case SNB_GTT_SIZE_0M:
 577                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
 578                         size = MB(0);
 579                         break;
 580                 case SNB_GTT_SIZE_1M:
 581                         size = MB(1);
 582                         break;
 583                 case SNB_GTT_SIZE_2M:
 584                         size = MB(2);
 585                         break;
 586                 }
 587                 return size/4;
 588         } else {
 589                 /* On previous hardware, the GTT size was just what was
 590                  * required to map the aperture.
 591                  */
 592                 return intel_private.base.gtt_mappable_entries;
 593         }
 594 }
 595
 596 static unsigned int intel_gtt_mappable_entries(void)
 597 {
 598         unsigned int aperture_size;
 599
 600         if (INTEL_GTT_GEN == 1) {
 601                 u32 smram_miscc;
 602
 603                 pci_read_config_dword(intel_private.bridge_dev,
 604                                       I810_SMRAM_MISCC, &smram_miscc);
 605
 606                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 607                                 == I810_GFX_MEM_WIN_32M)
 608                         aperture_size = MB(32);
 609                 else
 610                         aperture_size = MB(64);
 611         } else if (INTEL_GTT_GEN == 2) {
 612                 u16 gmch_ctrl;
 613
 614                 pci_read_config_word(intel_private.bridge_dev,
 615                                      I830_GMCH_CTRL, &gmch_ctrl);
 616
 617                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 618                         aperture_size = MB(64);
 619                 else
 620                         aperture_size = MB(128);
 621         } else {
 622                 /* 9xx supports large sizes, just look at the length */
 623                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 624         }
 625
 626         return aperture_size >> PAGE_SHIFT;
 627 }
 628
 629 static void intel_gtt_teardown_scratch_page(void)
 630 {
 631         set_pages_wb(intel_private.scratch_page, 1);
 632         pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
 633                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 634         put_page(intel_private.scratch_page);
 635         __free_page(intel_private.scratch_page);
 636 }
 637
 638 static void intel_gtt_cleanup(void)
 639 {
 640         intel_private.driver->cleanup();
 641
 642         iounmap(intel_private.gtt);
 643         iounmap(intel_private.registers);
 644
 645         intel_gtt_teardown_scratch_page();
 646 }
 647
 648 static int intel_gtt_init(void)
 649 {
 650         u32 gtt_map_size;
 651         int ret;
 652
 653         ret = intel_private.driver->setup();
 654         if (ret != 0)
 655                 return ret;
 656
 657         intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
 658         intel_private.base.gtt_total_entries = intel_gtt_total_entries();
 659
 660         /* save the PGETBL reg for resume */
 661         intel_private.PGETBL_save =
 662                 readl(intel_private.registers+I810_PGETBL_CTL)
 663                         & ~I810_PGETBL_ENABLED;
 664         /* we only ever restore the register when enabling the PGTBL... */
 665         if (HAS_PGTBL_EN)
 666                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 667
 668         dev_info(&intel_private.bridge_dev->dev,
 669                         "detected gtt size: %dK total, %dK mappable\n",
 670                         intel_private.base.gtt_total_entries * 4,
 671                         intel_private.base.gtt_mappable_entries * 4);
 672
 673         gtt_map_size = intel_private.base.gtt_total_entries * 4;
 674
 675         intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
 676                                     gtt_map_size);
 677         if (!intel_private.gtt) {
 678                 intel_private.driver->cleanup();
 679                 iounmap(intel_private.registers);
 680                 return -ENOMEM;
 681         }
 682         intel_private.base.gtt = intel_private.gtt;
 683
 684         global_cache_flush();   /* FIXME: ? */
 685
 686         intel_private.base.stolen_size = intel_gtt_stolen_size();
 687
 688         intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
 689
 690         ret = intel_gtt_setup_scratch_page();
 691         if (ret != 0) {
 692                 intel_gtt_cleanup();
 693                 return ret;
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int intel_fake_agp_fetch_size(void)
 700 {
 701         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 702         unsigned int aper_size;
 703         int i;
 704
 705         aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
 706                     / MB(1);
 707
 708         for (i = 0; i < num_sizes; i++) {
 709                 if (aper_size == intel_fake_agp_sizes[i].size) {
 710                         agp_bridge->current_size =
 711                                 (void *) (intel_fake_agp_sizes + i);
 712                         return aper_size;
 713                 }
 714         }
 715
 716         return 0;
 717 }
 718
 719 static void i830_cleanup(void)
 720 {
 721 }
 722
 723 /* The chipset_flush interface needs to get data that has already been
 724  * flushed out of the CPU all the way out to main memory, because the GPU
 725  * doesn't snoop those buffers.
 726  *
 727  * The 8xx series doesn't have the same lovely interface for flushing the
 728  * chipset write buffers that the later chips do. According to the 865
 729  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 730  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 731  * that it'll push whatever was in there out.  It appears to work.
 732  */
 733 static void i830_chipset_flush(void)
 734 {
 735         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 736
 737         /* Forcibly evict everything from the CPU write buffers.
 738          * clflush appears to be insufficient.
 739          */
 740         wbinvd_on_all_cpus();
 741
 742         /* Now we've only seen documents for this magic bit on 855GM,
 743          * we hope it exists for the other gen2 chipsets...
 744          *
 745          * Also works as advertised on my 845G.
 746          */
 747         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
 748                intel_private.registers+I830_HIC);
 749
 750         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
 751                 if (time_after(jiffies, timeout))
 752                         break;
 753
 754                 udelay(50);
 755         }
 756 }
 757
 758 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 759                              unsigned int flags)
 760 {
 761         u32 pte_flags = I810_PTE_VALID;
 762
 763         if (flags ==  AGP_USER_CACHED_MEMORY)
 764                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 765
 766         writel(addr | pte_flags, intel_private.gtt + entry);
 767 }
 768
 769 static bool intel_enable_gtt(void)
 770 {
 771         u32 gma_addr;
 772         u8 __iomem *reg;
 773
 774         if (INTEL_GTT_GEN <= 2)
 775                 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
 776                                       &gma_addr);
 777         else
 778                 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
 779                                       &gma_addr);
 780
 781         intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 782
 783         if (INTEL_GTT_GEN >= 6)
 784             return true;
 785
 786         if (INTEL_GTT_GEN == 2) {
 787                 u16 gmch_ctrl;
 788
 789                 pci_read_config_word(intel_private.bridge_dev,
 790                                      I830_GMCH_CTRL, &gmch_ctrl);
 791                 gmch_ctrl |= I830_GMCH_ENABLED;
 792                 pci_write_config_word(intel_private.bridge_dev,
 793                                       I830_GMCH_CTRL, gmch_ctrl);
 794
 795                 pci_read_config_word(intel_private.bridge_dev,
 796                                      I830_GMCH_CTRL, &gmch_ctrl);
 797                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 798                         dev_err(&intel_private.pcidev->dev,
 799                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 800                                 gmch_ctrl);
 801                         return false;
 802                 }
 803         }
 804
 805         /* On the resume path we may be adjusting the PGTBL value, so
 806          * be paranoid and flush all chipset write buffers...
 807          */
 808         if (INTEL_GTT_GEN >= 3)
 809                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 810
 811         reg = intel_private.registers+I810_PGETBL_CTL;
 812         writel(intel_private.PGETBL_save, reg);
 813         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 814                 dev_err(&intel_private.pcidev->dev,
 815                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 816                         readl(reg), intel_private.PGETBL_save);
 817                 return false;
 818         }
 819
 820         if (INTEL_GTT_GEN >= 3)
 821                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 822
 823         return true;
 824 }
 825
 826 static int i830_setup(void)
 827 {
 828         u32 reg_addr;
 829
 830         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 831         reg_addr &= 0xfff80000;
 832
 833         intel_private.registers = ioremap(reg_addr, KB(64));
 834         if (!intel_private.registers)
 835                 return -ENOMEM;
 836
 837         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 838
 839         return 0;
 840 }
 841
 842 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 843 {
 844         agp_bridge->gatt_table_real = NULL;
 845         agp_bridge->gatt_table = NULL;
 846         agp_bridge->gatt_bus_addr = 0;
 847
 848         return 0;
 849 }
 850
 851 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 852 {
 853         return 0;
 854 }
 855
 856 static int intel_fake_agp_configure(void)
 857 {
 858         if (!intel_enable_gtt())
 859             return -EIO;
 860
 861         intel_private.clear_fake_agp = true;
 862         agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr;
 863
 864         return 0;
 865 }
 866
 867 static bool i830_check_flags(unsigned int flags)
 868 {
 869         switch (flags) {
 870         case 0:
 871         case AGP_PHYS_MEMORY:
 872         case AGP_USER_CACHED_MEMORY:
 873         case AGP_USER_MEMORY:
 874                 return true;
 875         }
 876
 877         return false;
 878 }
 879
 880 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
 881                                  unsigned int sg_len,
 882                                  unsigned int pg_start,
 883                                  unsigned int flags)
 884 {
 885         struct scatterlist *sg;
 886         unsigned int len, m;
 887         int i, j;
 888
 889         j = pg_start;
 890
 891         /* sg may merge pages, but we have to separate
 892          * per-page addr for GTT */
 893         for_each_sg(sg_list, sg, sg_len, i) {
 894                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 895                 for (m = 0; m < len; m++) {
 896                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 897                         intel_private.driver->write_entry(addr,
 898                                                           j, flags);
 899                         j++;
 900                 }
 901         }
 902         readl(intel_private.gtt+j-1);
 903 }
 904 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 905
 906 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
 907                             struct page **pages, unsigned int flags)
 908 {
 909         int i, j;
 910
 911         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
 912                 dma_addr_t addr = page_to_phys(pages[i]);
 913                 intel_private.driver->write_entry(addr,
 914                                                   j, flags);
 915         }
 916         readl(intel_private.gtt+j-1);
 917 }
 918 EXPORT_SYMBOL(intel_gtt_insert_pages);
 919
 920 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 921                                          off_t pg_start, int type)
 922 {
 923         int ret = -EINVAL;
 924
 925         if (intel_private.base.do_idle_maps)
 926                 return -ENODEV;
 927
 928         if (intel_private.clear_fake_agp) {
 929                 int start = intel_private.base.stolen_size / PAGE_SIZE;
 930                 int end = intel_private.base.gtt_mappable_entries;
 931                 intel_gtt_clear_range(start, end - start);
 932                 intel_private.clear_fake_agp = false;
 933         }
 934
 935         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 936                 return i810_insert_dcache_entries(mem, pg_start, type);
 937
 938         if (mem->page_count == 0)
 939                 goto out;
 940
 941         if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
 942                 goto out_err;
 943
 944         if (type != mem->type)
 945                 goto out_err;
 946
 947         if (!intel_private.driver->check_flags(type))
 948                 goto out_err;
 949
 950         if (!mem->is_flushed)
 951                 global_cache_flush();
 952
 953         if (intel_private.base.needs_dmar) {
 954                 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
 955                                            &mem->sg_list, &mem->num_sg);
 956                 if (ret != 0)
 957                         return ret;
 958
 959                 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
 960                                             pg_start, type);
 961         } else
 962                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
 963                                        type);
 964
 965 out:
 966         ret = 0;
 967 out_err:
 968         mem->is_flushed = true;
 969         return ret;
 970 }
 971
 972 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 973 {
 974         unsigned int i;
 975
 976         for (i = first_entry; i < (first_entry + num_entries); i++) {
 977                 intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
 978                                                   i, 0);
 979         }
 980         readl(intel_private.gtt+i-1);
 981 }
 982 EXPORT_SYMBOL(intel_gtt_clear_range);
 983
 984 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
 985                                          off_t pg_start, int type)
 986 {
 987         if (mem->page_count == 0)
 988                 return 0;
 989
 990         if (intel_private.base.do_idle_maps)
 991                 return -ENODEV;
 992
 993         intel_gtt_clear_range(pg_start, mem->page_count);
 994
 995         if (intel_private.base.needs_dmar) {
 996                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
 997                 mem->sg_list = NULL;
 998                 mem->num_sg = 0;
 999         }
1000
1001         return 0;
1002 }
1003
1004 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1005                                                        int type)
1006 {
1007         struct agp_memory *new;
1008
1009         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1010                 if (pg_count != intel_private.num_dcache_entries)
1011                         return NULL;
1012
1013                 new = agp_create_memory(1);
1014                 if (new == NULL)
1015                         return NULL;
1016
1017                 new->type = AGP_DCACHE_MEMORY;
1018                 new->page_count = pg_count;
1019                 new->num_scratch_pages = 0;
1020                 agp_free_page_array(new);
1021                 return new;
1022         }
1023         if (type == AGP_PHYS_MEMORY)
1024                 return alloc_agpphysmem_i8xx(pg_count, type);
1025         /* always return NULL for other allocation types for now */
1026         return NULL;
1027 }
1028
1029 static int intel_alloc_chipset_flush_resource(void)
1030 {
1031         int ret;
1032         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1033                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1034                                      pcibios_align_resource, intel_private.bridge_dev);
1035
1036         return ret;
1037 }
1038
1039 static void intel_i915_setup_chipset_flush(void)
1040 {
1041         int ret;
1042         u32 temp;
1043
1044         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1045         if (!(temp & 0x1)) {
1046                 intel_alloc_chipset_flush_resource();
1047                 intel_private.resource_valid = 1;
1048                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1049         } else {
1050                 temp &= ~1;
1051
1052                 intel_private.resource_valid = 1;
1053                 intel_private.ifp_resource.start = temp;
1054                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1055                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1056                 /* some BIOSes reserve this area in a pnp some don't */
1057                 if (ret)
1058                         intel_private.resource_valid = 0;
1059         }
1060 }
1061
1062 static void intel_i965_g33_setup_chipset_flush(void)
1063 {
1064         u32 temp_hi, temp_lo;
1065         int ret;
1066
1067         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1068         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1069
1070         if (!(temp_lo & 0x1)) {
1071
1072                 intel_alloc_chipset_flush_resource();
1073
1074                 intel_private.resource_valid = 1;
1075                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1076                         upper_32_bits(intel_private.ifp_resource.start));
1077                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1078         } else {
1079                 u64 l64;
1080
1081                 temp_lo &= ~0x1;
1082                 l64 = ((u64)temp_hi << 32) | temp_lo;
1083
1084                 intel_private.resource_valid = 1;
1085                 intel_private.ifp_resource.start = l64;
1086                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1087                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1088                 /* some BIOSes reserve this area in a pnp some don't */
1089                 if (ret)
1090                         intel_private.resource_valid = 0;
1091         }
1092 }
1093
1094 static void intel_i9xx_setup_flush(void)
1095 {
1096         /* return if already configured */
1097         if (intel_private.ifp_resource.start)
1098                 return;
1099
1100         if (INTEL_GTT_GEN == 6)
1101                 return;
1102
1103         /* setup a resource for this object */
1104         intel_private.ifp_resource.name = "Intel Flush Page";
1105         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1106
1107         /* Setup chipset flush for 915 */
1108         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1109                 intel_i965_g33_setup_chipset_flush();
1110         } else {
1111                 intel_i915_setup_chipset_flush();
1112         }
1113
1114         if (intel_private.ifp_resource.start)
1115                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1116         if (!intel_private.i9xx_flush_page)
1117                 dev_err(&intel_private.pcidev->dev,
1118                         "can't ioremap flush page - no chipset flushing\n");
1119 }
1120
1121 static void i9xx_cleanup(void)
1122 {
1123         if (intel_private.i9xx_flush_page)
1124                 iounmap(intel_private.i9xx_flush_page);
1125         if (intel_private.resource_valid)
1126                 release_resource(&intel_private.ifp_resource);
1127         intel_private.ifp_resource.start = 0;
1128         intel_private.resource_valid = 0;
1129 }
1130
1131 static void i9xx_chipset_flush(void)
1132 {
1133         if (intel_private.i9xx_flush_page)
1134                 writel(1, intel_private.i9xx_flush_page);
1135 }
1136
1137 static void i965_write_entry(dma_addr_t addr,
1138                              unsigned int entry,
1139                              unsigned int flags)
1140 {
1141         u32 pte_flags;
1142
1143         pte_flags = I810_PTE_VALID;
1144         if (flags == AGP_USER_CACHED_MEMORY)
1145                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1146
1147         /* Shift high bits down */
1148         addr |= (addr >> 28) & 0xf0;
1149         writel(addr | pte_flags, intel_private.gtt + entry);
1150 }
1151
1152 static bool gen6_check_flags(unsigned int flags)
1153 {
1154         return true;
1155 }
1156
1157 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1158                              unsigned int flags)
1159 {
1160         unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1161         unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1162         u32 pte_flags;
1163
1164         if (type_mask == AGP_USER_MEMORY)
1165                 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1166         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1167                 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1168                 if (gfdt)
1169                         pte_flags |= GEN6_PTE_GFDT;
1170         } else { /* set 'normal'/'cached' to LLC by default */
1171                 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1172                 if (gfdt)
1173                         pte_flags |= GEN6_PTE_GFDT;
1174         }
1175
1176         /* gen6 has bit11-4 for physical addr bit39-32 */
1177         addr |= (addr >> 28) & 0xff0;
1178         writel(addr | pte_flags, intel_private.gtt + entry);
1179 }
1180
1181 static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
1182                                    unsigned int flags)
1183 {
1184         u32 pte_flags;
1185
1186         pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1187
1188         /* gen6 has bit11-4 for physical addr bit39-32 */
1189         addr |= (addr >> 28) & 0xff0;
1190         writel(addr | pte_flags, intel_private.gtt + entry);
1191
1192         writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);
1193 }
1194
1195 static void gen6_cleanup(void)
1196 {
1197 }
1198
1199 /* Certain Gen5 chipsets require require idling the GPU before
1200  * unmapping anything from the GTT when VT-d is enabled.
1201  */
1202 static inline int needs_idle_maps(void)
1203 {
1204 #ifdef CONFIG_INTEL_IOMMU
1205         const unsigned short gpu_devid = intel_private.pcidev->device;
1206
1207         /* Query intel_iommu to see if we need the workaround. Presumably that
1208          * was loaded first.
1209          */
1210         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1211              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1212              intel_iommu_gfx_mapped)
1213                 return 1;
1214 #endif
1215         return 0;
1216 }
1217
1218 static int i9xx_setup(void)
1219 {
1220         u32 reg_addr;
1221         int size = KB(512);
1222
1223         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1224
1225         reg_addr &= 0xfff80000;
1226
1227         if (INTEL_GTT_GEN >= 7)
1228                 size = MB(2);
1229
1230         intel_private.registers = ioremap(reg_addr, size);
1231         if (!intel_private.registers)
1232                 return -ENOMEM;
1233
1234         if (INTEL_GTT_GEN == 3) {
1235                 u32 gtt_addr;
1236
1237                 pci_read_config_dword(intel_private.pcidev,
1238                                       I915_PTEADDR, &gtt_addr);
1239                 intel_private.gtt_bus_addr = gtt_addr;
1240         } else {
1241                 u32 gtt_offset;
1242
1243                 switch (INTEL_GTT_GEN) {
1244                 case 5:
1245                 case 6:
1246                         gtt_offset = MB(2);
1247                         break;
1248                 case 4:
1249                 default:
1250                         gtt_offset =  KB(512);
1251                         break;
1252                 }
1253                 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1254         }
1255
1256         if (needs_idle_maps())
1257                 intel_private.base.do_idle_maps = 1;
1258
1259         intel_i9xx_setup_flush();
1260
1261         return 0;
1262 }
1263
1264 static const struct agp_bridge_driver intel_fake_agp_driver = {
1265         .owner                  = THIS_MODULE,
1266         .size_type              = FIXED_APER_SIZE,
1267         .aperture_sizes         = intel_fake_agp_sizes,
1268         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1269         .configure              = intel_fake_agp_configure,
1270         .fetch_size             = intel_fake_agp_fetch_size,
1271         .cleanup                = intel_gtt_cleanup,
1272         .agp_enable             = intel_fake_agp_enable,
1273         .cache_flush            = global_cache_flush,
1274         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1275         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1276         .insert_memory          = intel_fake_agp_insert_entries,
1277         .remove_memory          = intel_fake_agp_remove_entries,
1278         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1279         .free_by_type           = intel_i810_free_by_type,
1280         .agp_alloc_page         = agp_generic_alloc_page,
1281         .agp_alloc_pages        = agp_generic_alloc_pages,
1282         .agp_destroy_page       = agp_generic_destroy_page,
1283         .agp_destroy_pages      = agp_generic_destroy_pages,
1284 };
1285
1286 static const struct intel_gtt_driver i81x_gtt_driver = {
1287         .gen = 1,
1288         .has_pgtbl_enable = 1,
1289         .dma_mask_size = 32,
1290         .setup = i810_setup,
1291         .cleanup = i810_cleanup,
1292         .check_flags = i830_check_flags,
1293         .write_entry = i810_write_entry,
1294 };
1295 static const struct intel_gtt_driver i8xx_gtt_driver = {
1296         .gen = 2,
1297         .has_pgtbl_enable = 1,
1298         .setup = i830_setup,
1299         .cleanup = i830_cleanup,
1300         .write_entry = i830_write_entry,
1301         .dma_mask_size = 32,
1302         .check_flags = i830_check_flags,
1303         .chipset_flush = i830_chipset_flush,
1304 };
1305 static const struct intel_gtt_driver i915_gtt_driver = {
1306         .gen = 3,
1307         .has_pgtbl_enable = 1,
1308         .setup = i9xx_setup,
1309         .cleanup = i9xx_cleanup,
1310         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1311         .write_entry = i830_write_entry,
1312         .dma_mask_size = 32,
1313         .check_flags = i830_check_flags,
1314         .chipset_flush = i9xx_chipset_flush,
1315 };
1316 static const struct intel_gtt_driver g33_gtt_driver = {
1317         .gen = 3,
1318         .is_g33 = 1,
1319         .setup = i9xx_setup,
1320         .cleanup = i9xx_cleanup,
1321         .write_entry = i965_write_entry,
1322         .dma_mask_size = 36,
1323         .check_flags = i830_check_flags,
1324         .chipset_flush = i9xx_chipset_flush,
1325 };
1326 static const struct intel_gtt_driver pineview_gtt_driver = {
1327         .gen = 3,
1328         .is_pineview = 1, .is_g33 = 1,
1329         .setup = i9xx_setup,
1330         .cleanup = i9xx_cleanup,
1331         .write_entry = i965_write_entry,
1332         .dma_mask_size = 36,
1333         .check_flags = i830_check_flags,
1334         .chipset_flush = i9xx_chipset_flush,
1335 };
1336 static const struct intel_gtt_driver i965_gtt_driver = {
1337         .gen = 4,
1338         .has_pgtbl_enable = 1,
1339         .setup = i9xx_setup,
1340         .cleanup = i9xx_cleanup,
1341         .write_entry = i965_write_entry,
1342         .dma_mask_size = 36,
1343         .check_flags = i830_check_flags,
1344         .chipset_flush = i9xx_chipset_flush,
1345 };
1346 static const struct intel_gtt_driver g4x_gtt_driver = {
1347         .gen = 5,
1348         .setup = i9xx_setup,
1349         .cleanup = i9xx_cleanup,
1350         .write_entry = i965_write_entry,
1351         .dma_mask_size = 36,
1352         .check_flags = i830_check_flags,
1353         .chipset_flush = i9xx_chipset_flush,
1354 };
1355 static const struct intel_gtt_driver ironlake_gtt_driver = {
1356         .gen = 5,
1357         .is_ironlake = 1,
1358         .setup = i9xx_setup,
1359         .cleanup = i9xx_cleanup,
1360         .write_entry = i965_write_entry,
1361         .dma_mask_size = 36,
1362         .check_flags = i830_check_flags,
1363         .chipset_flush = i9xx_chipset_flush,
1364 };
1365 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1366         .gen = 6,
1367         .setup = i9xx_setup,
1368         .cleanup = gen6_cleanup,
1369         .write_entry = gen6_write_entry,
1370         .dma_mask_size = 40,
1371         .check_flags = gen6_check_flags,
1372         .chipset_flush = i9xx_chipset_flush,
1373 };
1374 static const struct intel_gtt_driver valleyview_gtt_driver = {
1375         .gen = 7,
1376         .setup = i9xx_setup,
1377         .cleanup = gen6_cleanup,
1378         .write_entry = valleyview_write_entry,
1379         .dma_mask_size = 40,
1380         .check_flags = gen6_check_flags,
1381         .chipset_flush = i9xx_chipset_flush,
1382 };
1383
1384 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1385  * driver and gmch_driver must be non-null, and find_gmch will determine
1386  * which one should be used if a gmch_chip_id is present.
1387  */
1388 static const struct intel_gtt_driver_description {
1389         unsigned int gmch_chip_id;
1390         char *name;
1391         const struct intel_gtt_driver *gtt_driver;
1392 } intel_gtt_chipsets[] = {
1393         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1394                 &i81x_gtt_driver},
1395         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1396                 &i81x_gtt_driver},
1397         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1398                 &i81x_gtt_driver},
1399         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1400                 &i81x_gtt_driver},
1401         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1402                 &i8xx_gtt_driver},
1403         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1404                 &i8xx_gtt_driver},
1405         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1406                 &i8xx_gtt_driver},
1407         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1408                 &i8xx_gtt_driver},
1409         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1410                 &i8xx_gtt_driver},
1411         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1412                 &i915_gtt_driver },
1413         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1414                 &i915_gtt_driver },
1415         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1416                 &i915_gtt_driver },
1417         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1418                 &i915_gtt_driver },
1419         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1420                 &i915_gtt_driver },
1421         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1422                 &i915_gtt_driver },
1423         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1424                 &i965_gtt_driver },
1425         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1426                 &i965_gtt_driver },
1427         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1428                 &i965_gtt_driver },
1429         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1430                 &i965_gtt_driver },
1431         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1432                 &i965_gtt_driver },
1433         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1434                 &i965_gtt_driver },
1435         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1436                 &g33_gtt_driver },
1437         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1438                 &g33_gtt_driver },
1439         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1440                 &g33_gtt_driver },
1441         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1442                 &pineview_gtt_driver },
1443         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1444                 &pineview_gtt_driver },
1445         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1446                 &g4x_gtt_driver },
1447         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1448                 &g4x_gtt_driver },
1449         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1450                 &g4x_gtt_driver },
1451         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1452                 &g4x_gtt_driver },
1453         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1454                 &g4x_gtt_driver },
1455         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1456                 &g4x_gtt_driver },
1457         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1458                 &g4x_gtt_driver },
1459         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1460             "HD Graphics", &ironlake_gtt_driver },
1461         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1462             "HD Graphics", &ironlake_gtt_driver },
1463         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1464             "Sandybridge", &sandybridge_gtt_driver },
1465         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1466             "Sandybridge", &sandybridge_gtt_driver },
1467         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1468             "Sandybridge", &sandybridge_gtt_driver },
1469         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1470             "Sandybridge", &sandybridge_gtt_driver },
1471         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1472             "Sandybridge", &sandybridge_gtt_driver },
1473         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1474             "Sandybridge", &sandybridge_gtt_driver },
1475         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1476             "Sandybridge", &sandybridge_gtt_driver },
1477         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
1478             "Ivybridge", &sandybridge_gtt_driver },
1479         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
1480             "Ivybridge", &sandybridge_gtt_driver },
1481         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
1482             "Ivybridge", &sandybridge_gtt_driver },
1483         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
1484             "Ivybridge", &sandybridge_gtt_driver },
1485         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
1486             "Ivybridge", &sandybridge_gtt_driver },
1487         { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
1488             "Ivybridge", &sandybridge_gtt_driver },
1489         { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
1490             "ValleyView", &valleyview_gtt_driver },
1491         { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
1492             "Haswell", &sandybridge_gtt_driver },
1493         { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
1494             "Haswell", &sandybridge_gtt_driver },
1495         { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
1496             "Haswell", &sandybridge_gtt_driver },
1497         { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
1498             "Haswell", &sandybridge_gtt_driver },
1499         { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
1500             "Haswell", &sandybridge_gtt_driver },
1501         { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
1502             "Haswell", &sandybridge_gtt_driver },
1503         { PCI_DEVICE_ID_INTEL_HASWELL_SDV,
1504             "Haswell", &sandybridge_gtt_driver },
1505         { 0, NULL, NULL }
1506 };
1507
1508 static int find_gmch(u16 device)
1509 {
1510         struct pci_dev *gmch_device;
1511
1512         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1513         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1514                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1515                                              device, gmch_device);
1516         }
1517
1518         if (!gmch_device)
1519                 return 0;
1520
1521         intel_private.pcidev = gmch_device;
1522         return 1;
1523 }
1524
1525 int intel_gmch_probe(struct pci_dev *pdev,
1526                                       struct agp_bridge_data *bridge)
1527 {
1528         int i, mask;
1529         intel_private.driver = NULL;
1530
1531         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1532                 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1533                         intel_private.driver =
1534                                 intel_gtt_chipsets[i].gtt_driver;
1535                         break;
1536                 }
1537         }
1538
1539         if (!intel_private.driver)
1540                 return 0;
1541
1542         bridge->driver = &intel_fake_agp_driver;
1543         bridge->dev_private_data = &intel_private;
1544         bridge->dev = pdev;
1545
1546         intel_private.bridge_dev = pci_dev_get(pdev);
1547
1548         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1549
1550         mask = intel_private.driver->dma_mask_size;
1551         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1552                 dev_err(&intel_private.pcidev->dev,
1553                         "set gfx device dma mask %d-bit failed!\n", mask);
1554         else
1555                 pci_set_consistent_dma_mask(intel_private.pcidev,
1556                                             DMA_BIT_MASK(mask));
1557
1558         if (intel_gtt_init() != 0)
1559                 return 0;
1560
1561         return 1;
1562 }
1563 EXPORT_SYMBOL(intel_gmch_probe);
1564
1565 const struct intel_gtt *intel_gtt_get(void)
1566 {
1567         return &intel_private.base;
1568 }
1569 EXPORT_SYMBOL(intel_gtt_get);
1570
1571 void intel_gtt_chipset_flush(void)
1572 {
1573         if (intel_private.driver->chipset_flush)
1574                 intel_private.driver->chipset_flush();
1575 }
1576 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1577
1578 void intel_gmch_remove(struct pci_dev *pdev)
1579 {
1580         if (intel_private.pcidev)
1581                 pci_dev_put(intel_private.pcidev);
1582         if (intel_private.bridge_dev)
1583                 pci_dev_put(intel_private.bridge_dev);
1584 }
1585 EXPORT_SYMBOL(intel_gmch_remove);
1586
1587 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1588 MODULE_LICENSE("GPL and additional rights");