2 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/of_address.h>
24 #include <linux/of_platform.h>
25 #include <linux/slab.h>
26 #include <linux/iopoll.h>
28 #include <linux/platform_data/ti-sysc.h>
30 #include <dt-bindings/bus/ti-sysc.h>
32 #define MAX_MODULE_SOFTRESET_WAIT 10000
34 static const char * const reg_names[] = { "rev", "sysc", "syss", };
50 static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", };
52 #define SYSC_IDLEMODE_MASK 3
53 #define SYSC_CLOCKACTIVITY_MASK 3
56 * struct sysc - TI sysc interconnect target module registers and capabilities
57 * @dev: struct device pointer
58 * @module_pa: physical address of the interconnect target module
59 * @module_size: size of the interconnect target module
60 * @module_va: virtual address of the interconnect target module
61 * @offsets: register offsets from module base
62 * @clocks: clocks used by the interconnect target module
63 * @clock_roles: clock role names for the found clocks
64 * @nr_clocks: number of clocks used by the interconnect target module
65 * @legacy_mode: configured for legacy mode if set
66 * @cap: interconnect target module capabilities
67 * @cfg: interconnect target module configuration
68 * @name: name if available
69 * @revision: interconnect target module revision
70 * @needs_resume: runtime resume needed on resume from suspend
76 void __iomem *module_va;
77 int offsets[SYSC_MAX_REGS];
79 const char **clock_roles;
81 struct reset_control *rsts;
82 const char *legacy_mode;
83 const struct sysc_capabilities *cap;
84 struct sysc_config cfg;
85 struct ti_sysc_cookie cookie;
90 bool child_needs_resume;
91 struct delayed_work idle_work;
94 void sysc_write(struct sysc *ddata, int offset, u32 value)
96 writel_relaxed(value, ddata->module_va + offset);
99 static u32 sysc_read(struct sysc *ddata, int offset)
101 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
104 val = readw_relaxed(ddata->module_va + offset);
105 val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
110 return readl_relaxed(ddata->module_va + offset);
113 static bool sysc_opt_clks_needed(struct sysc *ddata)
115 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
118 static u32 sysc_read_revision(struct sysc *ddata)
120 int offset = ddata->offsets[SYSC_REVISION];
125 return sysc_read(ddata, offset);
128 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
130 int error, i, index = -ENODEV;
132 if (!strncmp(clock_names[SYSC_FCK], name, 3))
134 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
138 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
139 if (!ddata->clocks[i]) {
147 dev_err(ddata->dev, "clock %s not added\n", name);
151 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
152 if (IS_ERR(ddata->clocks[index])) {
153 if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
156 dev_err(ddata->dev, "clock get error for %s: %li\n",
157 name, PTR_ERR(ddata->clocks[index]));
159 return PTR_ERR(ddata->clocks[index]);
162 error = clk_prepare(ddata->clocks[index]);
164 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
173 static int sysc_get_clocks(struct sysc *ddata)
175 struct device_node *np = ddata->dev->of_node;
176 struct property *prop;
178 int nr_fck = 0, nr_ick = 0, i, error = 0;
180 ddata->clock_roles = devm_kcalloc(ddata->dev,
182 sizeof(*ddata->clock_roles),
184 if (!ddata->clock_roles)
187 of_property_for_each_string(np, "clock-names", prop, name) {
188 if (!strncmp(clock_names[SYSC_FCK], name, 3))
190 if (!strncmp(clock_names[SYSC_ICK], name, 3))
192 ddata->clock_roles[ddata->nr_clocks] = name;
196 if (ddata->nr_clocks < 1)
199 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
200 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
205 if (nr_fck > 1 || nr_ick > 1) {
206 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
211 ddata->clocks = devm_kcalloc(ddata->dev,
212 ddata->nr_clocks, sizeof(*ddata->clocks),
217 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
218 const char *name = ddata->clock_roles[i];
223 error = sysc_get_one_clock(ddata, name);
224 if (error && error != -ENOENT)
232 * sysc_init_resets - reset module on init
233 * @ddata: device driver data
235 * A module can have both OCP softreset control and external rstctrl.
236 * If more complicated rstctrl resets are needed, please handle these
237 * directly from the child device driver and map only the module reset
238 * for the parent interconnect target module device.
240 * Automatic reset of the module on init can be skipped with the
241 * "ti,no-reset-on-init" device tree property.
243 static int sysc_init_resets(struct sysc *ddata)
248 devm_reset_control_array_get_optional_exclusive(ddata->dev);
249 if (IS_ERR(ddata->rsts))
250 return PTR_ERR(ddata->rsts);
252 if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
255 error = reset_control_assert(ddata->rsts);
260 error = reset_control_deassert(ddata->rsts);
268 * sysc_parse_and_check_child_range - parses module IO region from ranges
269 * @ddata: device driver data
271 * In general we only need rev, syss, and sysc registers and not the whole
272 * module range. But we do want the offsets for these registers from the
273 * module base. This allows us to check them against the legacy hwmod
274 * platform data. Let's also check the ranges are configured properly.
276 static int sysc_parse_and_check_child_range(struct sysc *ddata)
278 struct device_node *np = ddata->dev->of_node;
279 const __be32 *ranges;
280 u32 nr_addr, nr_size;
283 ranges = of_get_property(np, "ranges", &len);
285 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
290 len /= sizeof(*ranges);
293 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
298 error = of_property_read_u32(np, "#address-cells", &nr_addr);
302 error = of_property_read_u32(np, "#size-cells", &nr_size);
306 if (nr_addr != 1 || nr_size != 1) {
307 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
313 ddata->module_pa = of_translate_address(np, ranges++);
314 ddata->module_size = be32_to_cpup(ranges);
319 static struct device_node *stdout_path;
321 static void sysc_init_stdout_path(struct sysc *ddata)
323 struct device_node *np = NULL;
326 if (IS_ERR(stdout_path))
332 np = of_find_node_by_path("/chosen");
336 uart = of_get_property(np, "stdout-path", NULL);
340 np = of_find_node_by_path(uart);
349 stdout_path = ERR_PTR(-ENODEV);
352 static void sysc_check_quirk_stdout(struct sysc *ddata,
353 struct device_node *np)
355 sysc_init_stdout_path(ddata);
356 if (np != stdout_path)
359 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
360 SYSC_QUIRK_NO_RESET_ON_INIT;
364 * sysc_check_one_child - check child configuration
365 * @ddata: device driver data
366 * @np: child device node
368 * Let's avoid messy situations where we have new interconnect target
369 * node but children have "ti,hwmods". These belong to the interconnect
370 * target node and are managed by this driver.
372 static int sysc_check_one_child(struct sysc *ddata,
373 struct device_node *np)
377 name = of_get_property(np, "ti,hwmods", NULL);
379 dev_warn(ddata->dev, "really a child ti,hwmods property?");
381 sysc_check_quirk_stdout(ddata, np);
386 static int sysc_check_children(struct sysc *ddata)
388 struct device_node *child;
391 for_each_child_of_node(ddata->dev->of_node, child) {
392 error = sysc_check_one_child(ddata, child);
401 * So far only I2C uses 16-bit read access with clockactivity with revision
402 * in two registers with stride of 4. We can detect this based on the rev
403 * register size to configure things far enough to be able to properly read
404 * the revision register.
406 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
408 if (resource_size(res) == 8)
409 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
413 * sysc_parse_one - parses the interconnect target module registers
414 * @ddata: device driver data
415 * @reg: register to parse
417 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
419 struct resource *res;
426 name = reg_names[reg];
432 res = platform_get_resource_byname(to_platform_device(ddata->dev),
433 IORESOURCE_MEM, name);
435 ddata->offsets[reg] = -ENODEV;
440 ddata->offsets[reg] = res->start - ddata->module_pa;
441 if (reg == SYSC_REVISION)
442 sysc_check_quirk_16bit(ddata, res);
447 static int sysc_parse_registers(struct sysc *ddata)
451 for (i = 0; i < SYSC_MAX_REGS; i++) {
452 error = sysc_parse_one(ddata, i);
461 * sysc_check_registers - check for misconfigured register overlaps
462 * @ddata: device driver data
464 static int sysc_check_registers(struct sysc *ddata)
466 int i, j, nr_regs = 0, nr_matches = 0;
468 for (i = 0; i < SYSC_MAX_REGS; i++) {
469 if (ddata->offsets[i] < 0)
472 if (ddata->offsets[i] > (ddata->module_size - 4)) {
473 dev_err(ddata->dev, "register outside module range");
478 for (j = 0; j < SYSC_MAX_REGS; j++) {
479 if (ddata->offsets[j] < 0)
482 if (ddata->offsets[i] == ddata->offsets[j])
489 dev_err(ddata->dev, "missing registers\n");
494 if (nr_matches > nr_regs) {
495 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
496 nr_regs, nr_matches);
505 * syc_ioremap - ioremap register space for the interconnect target module
506 * @ddata: device driver data
508 * Note that the interconnect target module registers can be anywhere
509 * within the interconnect target module range. For example, SGX has
510 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
511 * has them at offset 0x1200 in the CPSW_WR child. Usually the
512 * the interconnect target module registers are at the beginning of
513 * the module range though.
515 static int sysc_ioremap(struct sysc *ddata)
519 size = max3(ddata->offsets[SYSC_REVISION],
520 ddata->offsets[SYSC_SYSCONFIG],
521 ddata->offsets[SYSC_SYSSTATUS]);
523 if (size < 0 || (size + sizeof(u32)) > ddata->module_size)
526 ddata->module_va = devm_ioremap(ddata->dev,
529 if (!ddata->module_va)
536 * sysc_map_and_check_registers - ioremap and check device registers
537 * @ddata: device driver data
539 static int sysc_map_and_check_registers(struct sysc *ddata)
543 error = sysc_parse_and_check_child_range(ddata);
547 error = sysc_check_children(ddata);
551 error = sysc_parse_registers(ddata);
555 error = sysc_ioremap(ddata);
559 error = sysc_check_registers(ddata);
567 * sysc_show_rev - read and show interconnect target module revision
568 * @bufp: buffer to print the information to
569 * @ddata: device driver data
571 static int sysc_show_rev(char *bufp, struct sysc *ddata)
575 if (ddata->offsets[SYSC_REVISION] < 0)
576 return sprintf(bufp, ":NA");
578 len = sprintf(bufp, ":%08x", ddata->revision);
583 static int sysc_show_reg(struct sysc *ddata,
584 char *bufp, enum sysc_registers reg)
586 if (ddata->offsets[reg] < 0)
587 return sprintf(bufp, ":NA");
589 return sprintf(bufp, ":%x", ddata->offsets[reg]);
592 static int sysc_show_name(char *bufp, struct sysc *ddata)
597 return sprintf(bufp, ":%s", ddata->name);
601 * sysc_show_registers - show information about interconnect target module
602 * @ddata: device driver data
604 static void sysc_show_registers(struct sysc *ddata)
610 for (i = 0; i < SYSC_MAX_REGS; i++)
611 bufp += sysc_show_reg(ddata, bufp, i);
613 bufp += sysc_show_rev(bufp, ddata);
614 bufp += sysc_show_name(bufp, ddata);
616 dev_dbg(ddata->dev, "%llx:%x%s\n",
617 ddata->module_pa, ddata->module_size,
621 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
623 struct ti_sysc_platform_data *pdata;
627 ddata = dev_get_drvdata(dev);
632 if (ddata->legacy_mode) {
633 pdata = dev_get_platdata(ddata->dev);
637 if (!pdata->idle_module)
640 error = pdata->idle_module(dev, &ddata->cookie);
642 dev_err(dev, "%s: could not idle: %i\n",
648 for (i = 0; i < ddata->nr_clocks; i++) {
649 if (IS_ERR_OR_NULL(ddata->clocks[i]))
652 if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
655 clk_disable(ddata->clocks[i]);
659 ddata->enabled = false;
664 static int __maybe_unused sysc_runtime_resume(struct device *dev)
666 struct ti_sysc_platform_data *pdata;
670 ddata = dev_get_drvdata(dev);
675 if (ddata->legacy_mode) {
676 pdata = dev_get_platdata(ddata->dev);
680 if (!pdata->enable_module)
683 error = pdata->enable_module(dev, &ddata->cookie);
685 dev_err(dev, "%s: could not enable: %i\n",
691 for (i = 0; i < ddata->nr_clocks; i++) {
692 if (IS_ERR_OR_NULL(ddata->clocks[i]))
695 if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
698 error = clk_enable(ddata->clocks[i]);
704 ddata->enabled = true;
709 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
713 ddata = dev_get_drvdata(dev);
715 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
718 return pm_runtime_force_suspend(dev);
721 static int __maybe_unused sysc_noirq_resume(struct device *dev)
725 ddata = dev_get_drvdata(dev);
727 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
730 return pm_runtime_force_resume(dev);
733 static const struct dev_pm_ops sysc_pm_ops = {
734 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
735 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
740 /* Module revision register based quirks */
741 struct sysc_revision_quirk {
752 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
753 optrev_val, optrevmask, optquirkmask) \
757 .rev_offset = (optrev), \
758 .sysc_offset = (optsysc), \
759 .syss_offset = (optsyss), \
760 .revision = (optrev_val), \
761 .revision_mask = (optrevmask), \
762 .quirks = (optquirkmask), \
765 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
766 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
767 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
768 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
769 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
770 SYSC_QUIRK_LEGACY_IDLE),
771 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
772 SYSC_QUIRK_LEGACY_IDLE),
773 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
774 SYSC_QUIRK_LEGACY_IDLE),
775 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
776 SYSC_QUIRK_LEGACY_IDLE),
777 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
778 SYSC_QUIRK_LEGACY_IDLE),
779 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
780 SYSC_QUIRK_LEGACY_IDLE),
781 /* Some timers on omap4 and later */
782 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
783 SYSC_QUIRK_LEGACY_IDLE),
784 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
785 SYSC_QUIRK_LEGACY_IDLE),
786 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
787 SYSC_QUIRK_LEGACY_IDLE),
788 /* Uarts on omap4 and later */
789 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
790 SYSC_QUIRK_LEGACY_IDLE),
791 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
792 SYSC_QUIRK_LEGACY_IDLE),
795 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
796 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
797 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
798 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
799 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
800 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
802 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
803 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0x00001401, 0xffffffff, 0),
804 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
805 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
806 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
807 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0),
808 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0),
809 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
810 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
811 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0),
812 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
813 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
814 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
815 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
816 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
817 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
818 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
819 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
820 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
821 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
822 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
823 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
824 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
825 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
826 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
827 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
828 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
829 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
830 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
831 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
832 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
833 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
834 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
835 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
836 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
837 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
838 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
839 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
840 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
841 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
842 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
843 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
844 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
845 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
847 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0),
848 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
852 static void sysc_init_revision_quirks(struct sysc *ddata)
854 const struct sysc_revision_quirk *q;
857 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
858 q = &sysc_revision_quirks[i];
860 if (q->base && q->base != ddata->module_pa)
863 if (q->rev_offset >= 0 &&
864 q->rev_offset != ddata->offsets[SYSC_REVISION])
867 if (q->sysc_offset >= 0 &&
868 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
871 if (q->syss_offset >= 0 &&
872 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
875 if (q->revision == ddata->revision ||
876 (q->revision & q->revision_mask) ==
877 (ddata->revision & q->revision_mask)) {
878 ddata->name = q->name;
879 ddata->cfg.quirks |= q->quirks;
884 static int sysc_reset(struct sysc *ddata)
886 int offset = ddata->offsets[SYSC_SYSCONFIG];
889 if (ddata->legacy_mode || offset < 0 ||
890 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
894 * Currently only support reset status in sysstatus.
895 * Warn and return error in all other cases
897 if (!ddata->cfg.syss_mask) {
898 dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n");
902 val = sysc_read(ddata, offset);
903 val |= (0x1 << ddata->cap->regbits->srst_shift);
904 sysc_write(ddata, offset, val);
906 /* Poll on reset status */
907 offset = ddata->offsets[SYSC_SYSSTATUS];
909 return readl_poll_timeout(ddata->module_va + offset, val,
910 (val & ddata->cfg.syss_mask) == 0x0,
911 100, MAX_MODULE_SOFTRESET_WAIT);
914 /* At this point the module is configured enough to read the revision */
915 static int sysc_init_module(struct sysc *ddata)
919 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) {
920 ddata->revision = sysc_read_revision(ddata);
924 error = pm_runtime_get_sync(ddata->dev);
926 pm_runtime_put_noidle(ddata->dev);
931 error = sysc_reset(ddata);
933 dev_err(ddata->dev, "Reset failed with %d\n", error);
934 pm_runtime_put_sync(ddata->dev);
939 ddata->revision = sysc_read_revision(ddata);
940 pm_runtime_put_sync(ddata->dev);
943 sysc_init_revision_quirks(ddata);
948 static int sysc_init_sysc_mask(struct sysc *ddata)
950 struct device_node *np = ddata->dev->of_node;
954 error = of_property_read_u32(np, "ti,sysc-mask", &val);
959 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
961 ddata->cfg.sysc_val = ddata->cap->sysc_mask;
966 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
969 struct device_node *np = ddata->dev->of_node;
970 struct property *prop;
974 of_property_for_each_u32(np, name, prop, p, val) {
975 if (val >= SYSC_NR_IDLEMODES) {
976 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
979 *idlemodes |= (1 << val);
985 static int sysc_init_idlemodes(struct sysc *ddata)
989 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
994 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1003 * Only some devices on omap4 and later have SYSCONFIG reset done
1004 * bit. We can detect this if there is no SYSSTATUS at all, or the
1005 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1006 * have multiple bits for the child devices like OHCI and EHCI.
1007 * Depends on SYSC being parsed first.
1009 static int sysc_init_syss_mask(struct sysc *ddata)
1011 struct device_node *np = ddata->dev->of_node;
1015 error = of_property_read_u32(np, "ti,syss-mask", &val);
1017 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1018 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1019 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1020 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1025 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1026 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1028 ddata->cfg.syss_mask = val;
1034 * Many child device drivers need to have fck and opt clocks available
1035 * to get the clock rate for device internal configuration etc.
1037 static int sysc_child_add_named_clock(struct sysc *ddata,
1038 struct device *child,
1042 struct clk_lookup *l;
1048 clk = clk_get(child, name);
1055 clk = clk_get(ddata->dev, name);
1059 l = clkdev_create(clk, name, dev_name(child));
1068 static int sysc_child_add_clocks(struct sysc *ddata,
1069 struct device *child)
1073 for (i = 0; i < ddata->nr_clocks; i++) {
1074 error = sysc_child_add_named_clock(ddata,
1076 ddata->clock_roles[i]);
1077 if (error && error != -EEXIST) {
1078 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1079 ddata->clock_roles[i], error);
1088 static struct device_type sysc_device_type = {
1091 static struct sysc *sysc_child_to_parent(struct device *dev)
1093 struct device *parent = dev->parent;
1095 if (!parent || parent->type != &sysc_device_type)
1098 return dev_get_drvdata(parent);
1101 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1106 ddata = sysc_child_to_parent(dev);
1108 error = pm_generic_runtime_suspend(dev);
1112 if (!ddata->enabled)
1115 return sysc_runtime_suspend(ddata->dev);
1118 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1123 ddata = sysc_child_to_parent(dev);
1125 if (!ddata->enabled) {
1126 error = sysc_runtime_resume(ddata->dev);
1129 "%s error: %i\n", __func__, error);
1132 return pm_generic_runtime_resume(dev);
1135 #ifdef CONFIG_PM_SLEEP
1136 static int sysc_child_suspend_noirq(struct device *dev)
1141 ddata = sysc_child_to_parent(dev);
1143 dev_dbg(ddata->dev, "%s %s\n", __func__,
1144 ddata->name ? ddata->name : "");
1146 error = pm_generic_suspend_noirq(dev);
1148 dev_err(dev, "%s error at %i: %i\n",
1149 __func__, __LINE__, error);
1154 if (!pm_runtime_status_suspended(dev)) {
1155 error = pm_generic_runtime_suspend(dev);
1157 dev_dbg(dev, "%s busy at %i: %i\n",
1158 __func__, __LINE__, error);
1163 error = sysc_runtime_suspend(ddata->dev);
1165 dev_err(dev, "%s error at %i: %i\n",
1166 __func__, __LINE__, error);
1171 ddata->child_needs_resume = true;
1177 static int sysc_child_resume_noirq(struct device *dev)
1182 ddata = sysc_child_to_parent(dev);
1184 dev_dbg(ddata->dev, "%s %s\n", __func__,
1185 ddata->name ? ddata->name : "");
1187 if (ddata->child_needs_resume) {
1188 ddata->child_needs_resume = false;
1190 error = sysc_runtime_resume(ddata->dev);
1193 "%s runtime resume error: %i\n",
1196 error = pm_generic_runtime_resume(dev);
1199 "%s generic runtime resume: %i\n",
1203 return pm_generic_resume_noirq(dev);
1207 struct dev_pm_domain sysc_child_pm_domain = {
1209 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1210 sysc_child_runtime_resume,
1212 USE_PLATFORM_PM_SLEEP_OPS
1213 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1214 sysc_child_resume_noirq)
1219 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1220 * @ddata: device driver data
1221 * @child: child device driver
1223 * Allow idle for child devices as done with _od_runtime_suspend().
1224 * Otherwise many child devices will not idle because of the permanent
1225 * parent usecount set in pm_runtime_irq_safe().
1227 * Note that the long term solution is to just modify the child device
1228 * drivers to not set pm_runtime_irq_safe() and then this can be just
1231 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1233 if (!ddata->legacy_mode)
1236 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1237 dev_pm_domain_set(child, &sysc_child_pm_domain);
1240 static int sysc_notifier_call(struct notifier_block *nb,
1241 unsigned long event, void *device)
1243 struct device *dev = device;
1247 ddata = sysc_child_to_parent(dev);
1252 case BUS_NOTIFY_ADD_DEVICE:
1253 error = sysc_child_add_clocks(ddata, dev);
1256 sysc_legacy_idle_quirk(ddata, dev);
1265 static struct notifier_block sysc_nb = {
1266 .notifier_call = sysc_notifier_call,
1269 /* Device tree configured quirks */
1270 struct sysc_dts_quirk {
1275 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
1276 { .name = "ti,no-idle-on-init",
1277 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1278 { .name = "ti,no-reset-on-init",
1279 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
1282 static int sysc_init_dts_quirks(struct sysc *ddata)
1284 struct device_node *np = ddata->dev->of_node;
1285 const struct property *prop;
1289 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
1291 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
1292 prop = of_get_property(np, sysc_dts_quirks[i].name, &len);
1296 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
1299 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
1302 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
1306 ddata->cfg.srst_udelay = (u8)val;
1312 static void sysc_unprepare(struct sysc *ddata)
1316 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
1317 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
1318 clk_unprepare(ddata->clocks[i]);
1323 * Common sysc register bits found on omap2, also known as type1
1325 static const struct sysc_regbits sysc_regbits_omap2 = {
1326 .dmadisable_shift = -ENODEV,
1333 .autoidle_shift = 0,
1336 static const struct sysc_capabilities sysc_omap2 = {
1337 .type = TI_SYSC_OMAP2,
1338 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1339 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1340 SYSC_OMAP2_AUTOIDLE,
1341 .regbits = &sysc_regbits_omap2,
1344 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
1345 static const struct sysc_capabilities sysc_omap2_timer = {
1346 .type = TI_SYSC_OMAP2_TIMER,
1347 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1348 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1349 SYSC_OMAP2_AUTOIDLE,
1350 .regbits = &sysc_regbits_omap2,
1351 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
1355 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
1356 * with different sidle position
1358 static const struct sysc_regbits sysc_regbits_omap3_sham = {
1359 .dmadisable_shift = -ENODEV,
1360 .midle_shift = -ENODEV,
1362 .clkact_shift = -ENODEV,
1363 .enwkup_shift = -ENODEV,
1365 .autoidle_shift = 0,
1366 .emufree_shift = -ENODEV,
1369 static const struct sysc_capabilities sysc_omap3_sham = {
1370 .type = TI_SYSC_OMAP3_SHAM,
1371 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1372 .regbits = &sysc_regbits_omap3_sham,
1376 * AES register bits found on omap3 and later, a variant of
1377 * sysc_regbits_omap2 with different sidle position
1379 static const struct sysc_regbits sysc_regbits_omap3_aes = {
1380 .dmadisable_shift = -ENODEV,
1381 .midle_shift = -ENODEV,
1383 .clkact_shift = -ENODEV,
1384 .enwkup_shift = -ENODEV,
1386 .autoidle_shift = 0,
1387 .emufree_shift = -ENODEV,
1390 static const struct sysc_capabilities sysc_omap3_aes = {
1391 .type = TI_SYSC_OMAP3_AES,
1392 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1393 .regbits = &sysc_regbits_omap3_aes,
1397 * Common sysc register bits found on omap4, also known as type2
1399 static const struct sysc_regbits sysc_regbits_omap4 = {
1400 .dmadisable_shift = 16,
1403 .clkact_shift = -ENODEV,
1404 .enwkup_shift = -ENODEV,
1407 .autoidle_shift = -ENODEV,
1410 static const struct sysc_capabilities sysc_omap4 = {
1411 .type = TI_SYSC_OMAP4,
1412 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1413 SYSC_OMAP4_SOFTRESET,
1414 .regbits = &sysc_regbits_omap4,
1417 static const struct sysc_capabilities sysc_omap4_timer = {
1418 .type = TI_SYSC_OMAP4_TIMER,
1419 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1420 SYSC_OMAP4_SOFTRESET,
1421 .regbits = &sysc_regbits_omap4,
1425 * Common sysc register bits found on omap4, also known as type3
1427 static const struct sysc_regbits sysc_regbits_omap4_simple = {
1428 .dmadisable_shift = -ENODEV,
1431 .clkact_shift = -ENODEV,
1432 .enwkup_shift = -ENODEV,
1433 .srst_shift = -ENODEV,
1434 .emufree_shift = -ENODEV,
1435 .autoidle_shift = -ENODEV,
1438 static const struct sysc_capabilities sysc_omap4_simple = {
1439 .type = TI_SYSC_OMAP4_SIMPLE,
1440 .regbits = &sysc_regbits_omap4_simple,
1444 * SmartReflex sysc found on omap34xx
1446 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
1447 .dmadisable_shift = -ENODEV,
1448 .midle_shift = -ENODEV,
1449 .sidle_shift = -ENODEV,
1451 .enwkup_shift = -ENODEV,
1452 .srst_shift = -ENODEV,
1453 .emufree_shift = -ENODEV,
1454 .autoidle_shift = -ENODEV,
1457 static const struct sysc_capabilities sysc_34xx_sr = {
1458 .type = TI_SYSC_OMAP34XX_SR,
1459 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
1460 .regbits = &sysc_regbits_omap34xx_sr,
1461 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
1462 SYSC_QUIRK_LEGACY_IDLE,
1466 * SmartReflex sysc found on omap36xx and later
1468 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
1469 .dmadisable_shift = -ENODEV,
1470 .midle_shift = -ENODEV,
1472 .clkact_shift = -ENODEV,
1474 .srst_shift = -ENODEV,
1475 .emufree_shift = -ENODEV,
1476 .autoidle_shift = -ENODEV,
1479 static const struct sysc_capabilities sysc_36xx_sr = {
1480 .type = TI_SYSC_OMAP36XX_SR,
1481 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
1482 .regbits = &sysc_regbits_omap36xx_sr,
1483 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
1486 static const struct sysc_capabilities sysc_omap4_sr = {
1487 .type = TI_SYSC_OMAP4_SR,
1488 .regbits = &sysc_regbits_omap36xx_sr,
1489 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
1493 * McASP register bits found on omap4 and later
1495 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
1496 .dmadisable_shift = -ENODEV,
1497 .midle_shift = -ENODEV,
1499 .clkact_shift = -ENODEV,
1500 .enwkup_shift = -ENODEV,
1501 .srst_shift = -ENODEV,
1502 .emufree_shift = -ENODEV,
1503 .autoidle_shift = -ENODEV,
1506 static const struct sysc_capabilities sysc_omap4_mcasp = {
1507 .type = TI_SYSC_OMAP4_MCASP,
1508 .regbits = &sysc_regbits_omap4_mcasp,
1509 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
1513 * McASP found on dra7 and later
1515 static const struct sysc_capabilities sysc_dra7_mcasp = {
1516 .type = TI_SYSC_OMAP4_SIMPLE,
1517 .regbits = &sysc_regbits_omap4_simple,
1518 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
1522 * FS USB host found on omap4 and later
1524 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
1525 .dmadisable_shift = -ENODEV,
1526 .midle_shift = -ENODEV,
1528 .clkact_shift = -ENODEV,
1530 .srst_shift = -ENODEV,
1531 .emufree_shift = -ENODEV,
1532 .autoidle_shift = -ENODEV,
1535 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
1536 .type = TI_SYSC_OMAP4_USB_HOST_FS,
1537 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
1538 .regbits = &sysc_regbits_omap4_usb_host_fs,
1541 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
1542 .dmadisable_shift = -ENODEV,
1543 .midle_shift = -ENODEV,
1544 .sidle_shift = -ENODEV,
1545 .clkact_shift = -ENODEV,
1548 .emufree_shift = -ENODEV,
1549 .autoidle_shift = -ENODEV,
1552 static const struct sysc_capabilities sysc_dra7_mcan = {
1553 .type = TI_SYSC_DRA7_MCAN,
1554 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
1555 .regbits = &sysc_regbits_dra7_mcan,
1558 static int sysc_init_pdata(struct sysc *ddata)
1560 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1561 struct ti_sysc_module_data mdata;
1564 if (!pdata || !ddata->legacy_mode)
1567 mdata.name = ddata->legacy_mode;
1568 mdata.module_pa = ddata->module_pa;
1569 mdata.module_size = ddata->module_size;
1570 mdata.offsets = ddata->offsets;
1571 mdata.nr_offsets = SYSC_MAX_REGS;
1572 mdata.cap = ddata->cap;
1573 mdata.cfg = &ddata->cfg;
1575 if (!pdata->init_module)
1578 error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie);
1579 if (error == -EEXIST)
1585 static int sysc_init_match(struct sysc *ddata)
1587 const struct sysc_capabilities *cap;
1589 cap = of_device_get_match_data(ddata->dev);
1595 ddata->cfg.quirks |= ddata->cap->mod_quirks;
1600 static void ti_sysc_idle(struct work_struct *work)
1604 ddata = container_of(work, struct sysc, idle_work.work);
1606 if (pm_runtime_active(ddata->dev))
1607 pm_runtime_put_sync(ddata->dev);
1610 static const struct of_device_id sysc_match_table[] = {
1611 { .compatible = "simple-bus", },
1615 static int sysc_probe(struct platform_device *pdev)
1617 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1621 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
1625 ddata->dev = &pdev->dev;
1626 platform_set_drvdata(pdev, ddata);
1628 error = sysc_init_match(ddata);
1632 error = sysc_init_dts_quirks(ddata);
1636 error = sysc_get_clocks(ddata);
1640 error = sysc_map_and_check_registers(ddata);
1644 error = sysc_init_sysc_mask(ddata);
1648 error = sysc_init_idlemodes(ddata);
1652 error = sysc_init_syss_mask(ddata);
1656 error = sysc_init_pdata(ddata);
1660 error = sysc_init_resets(ddata);
1664 pm_runtime_enable(ddata->dev);
1665 error = sysc_init_module(ddata);
1669 error = pm_runtime_get_sync(ddata->dev);
1671 pm_runtime_put_noidle(ddata->dev);
1672 pm_runtime_disable(ddata->dev);
1676 sysc_show_registers(ddata);
1678 ddata->dev->type = &sysc_device_type;
1679 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
1680 pdata ? pdata->auxdata : NULL,
1685 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
1687 /* At least earlycon won't survive without deferred idle */
1688 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT |
1689 SYSC_QUIRK_NO_RESET_ON_INIT)) {
1690 schedule_delayed_work(&ddata->idle_work, 3000);
1692 pm_runtime_put(&pdev->dev);
1695 if (!of_get_available_child_count(ddata->dev->of_node))
1696 reset_control_assert(ddata->rsts);
1701 pm_runtime_put_sync(&pdev->dev);
1702 pm_runtime_disable(&pdev->dev);
1704 sysc_unprepare(ddata);
1709 static int sysc_remove(struct platform_device *pdev)
1711 struct sysc *ddata = platform_get_drvdata(pdev);
1714 cancel_delayed_work_sync(&ddata->idle_work);
1716 error = pm_runtime_get_sync(ddata->dev);
1718 pm_runtime_put_noidle(ddata->dev);
1719 pm_runtime_disable(ddata->dev);
1723 of_platform_depopulate(&pdev->dev);
1725 pm_runtime_put_sync(&pdev->dev);
1726 pm_runtime_disable(&pdev->dev);
1727 reset_control_assert(ddata->rsts);
1730 sysc_unprepare(ddata);
1735 static const struct of_device_id sysc_match[] = {
1736 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
1737 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
1738 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
1739 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
1740 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
1741 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
1742 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
1743 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
1744 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
1745 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
1746 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
1747 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
1748 { .compatible = "ti,sysc-usb-host-fs",
1749 .data = &sysc_omap4_usb_host_fs, },
1750 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
1753 MODULE_DEVICE_TABLE(of, sysc_match);
1755 static struct platform_driver sysc_driver = {
1756 .probe = sysc_probe,
1757 .remove = sysc_remove,
1760 .of_match_table = sysc_match,
1765 static int __init sysc_init(void)
1767 bus_register_notifier(&platform_bus_type, &sysc_nb);
1769 return platform_driver_register(&sysc_driver);
1771 module_init(sysc_init);
1773 static void __exit sysc_exit(void)
1775 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
1776 platform_driver_unregister(&sysc_driver);
1778 module_exit(sysc_exit);
1780 MODULE_DESCRIPTION("TI sysc interconnect target driver");
1781 MODULE_LICENSE("GPL v2");