1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/list.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_domain.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/slab.h>
19 #include <linux/sys_soc.h>
20 #include <linux/iopoll.h>
22 #include <linux/platform_data/ti-sysc.h>
24 #include <dt-bindings/bus/ti-sysc.h>
26 #define DIS_ISP BIT(2)
27 #define DIS_IVA BIT(1)
28 #define DIS_SGX BIT(0)
30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
32 #define MAX_MODULE_SOFTRESET_WAIT 10000
51 struct list_head node;
54 struct sysc_soc_info {
55 unsigned long general_purpose:1;
57 struct mutex list_lock; /* disabled modules list lock */
58 struct list_head disabled_modules;
75 static struct sysc_soc_info *sysc_soc;
76 static const char * const reg_names[] = { "rev", "sysc", "syss", };
77 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
79 "opt5", "opt6", "opt7",
82 #define SYSC_IDLEMODE_MASK 3
83 #define SYSC_CLOCKACTIVITY_MASK 3
86 * struct sysc - TI sysc interconnect target module registers and capabilities
87 * @dev: struct device pointer
88 * @module_pa: physical address of the interconnect target module
89 * @module_size: size of the interconnect target module
90 * @module_va: virtual address of the interconnect target module
91 * @offsets: register offsets from module base
92 * @mdata: ti-sysc to hwmod translation data for a module
93 * @clocks: clocks used by the interconnect target module
94 * @clock_roles: clock role names for the found clocks
95 * @nr_clocks: number of clocks used by the interconnect target module
96 * @rsts: resets used by the interconnect target module
97 * @legacy_mode: configured for legacy mode if set
98 * @cap: interconnect target module capabilities
99 * @cfg: interconnect target module configuration
100 * @cookie: data used by legacy platform callbacks
101 * @name: name if available
102 * @revision: interconnect target module revision
103 * @enabled: sysc runtime enabled status
104 * @needs_resume: runtime resume needed on resume from suspend
105 * @child_needs_resume: runtime resume needed for child on resume from suspend
106 * @disable_on_idle: status flag used for disabling modules with resets
107 * @idle_work: work structure used to perform delayed idle on a module
108 * @pre_reset_quirk: module specific pre-reset quirk
109 * @post_reset_quirk: module specific post-reset quirk
110 * @reset_done_quirk: module specific reset done quirk
111 * @module_enable_quirk: module specific enable quirk
112 * @module_disable_quirk: module specific disable quirk
113 * @module_unlock_quirk: module specific sysconfig unlock quirk
114 * @module_lock_quirk: module specific sysconfig lock quirk
120 void __iomem *module_va;
121 int offsets[SYSC_MAX_REGS];
122 struct ti_sysc_module_data *mdata;
124 const char **clock_roles;
126 struct reset_control *rsts;
127 const char *legacy_mode;
128 const struct sysc_capabilities *cap;
129 struct sysc_config cfg;
130 struct ti_sysc_cookie cookie;
133 unsigned int enabled:1;
134 unsigned int needs_resume:1;
135 unsigned int child_needs_resume:1;
136 struct delayed_work idle_work;
137 void (*pre_reset_quirk)(struct sysc *sysc);
138 void (*post_reset_quirk)(struct sysc *sysc);
139 void (*reset_done_quirk)(struct sysc *sysc);
140 void (*module_enable_quirk)(struct sysc *sysc);
141 void (*module_disable_quirk)(struct sysc *sysc);
142 void (*module_unlock_quirk)(struct sysc *sysc);
143 void (*module_lock_quirk)(struct sysc *sysc);
146 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
149 static void sysc_write(struct sysc *ddata, int offset, u32 value)
151 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
152 writew_relaxed(value & 0xffff, ddata->module_va + offset);
154 /* Only i2c revision has LO and HI register with stride of 4 */
155 if (ddata->offsets[SYSC_REVISION] >= 0 &&
156 offset == ddata->offsets[SYSC_REVISION]) {
157 u16 hi = value >> 16;
159 writew_relaxed(hi, ddata->module_va + offset + 4);
165 writel_relaxed(value, ddata->module_va + offset);
168 static u32 sysc_read(struct sysc *ddata, int offset)
170 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
173 val = readw_relaxed(ddata->module_va + offset);
175 /* Only i2c revision has LO and HI register with stride of 4 */
176 if (ddata->offsets[SYSC_REVISION] >= 0 &&
177 offset == ddata->offsets[SYSC_REVISION]) {
178 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
186 return readl_relaxed(ddata->module_va + offset);
189 static bool sysc_opt_clks_needed(struct sysc *ddata)
191 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
194 static u32 sysc_read_revision(struct sysc *ddata)
196 int offset = ddata->offsets[SYSC_REVISION];
201 return sysc_read(ddata, offset);
204 static u32 sysc_read_sysconfig(struct sysc *ddata)
206 int offset = ddata->offsets[SYSC_SYSCONFIG];
211 return sysc_read(ddata, offset);
214 static u32 sysc_read_sysstatus(struct sysc *ddata)
216 int offset = ddata->offsets[SYSC_SYSSTATUS];
221 return sysc_read(ddata, offset);
224 /* Poll on reset status */
225 static int sysc_wait_softreset(struct sysc *ddata)
227 u32 sysc_mask, syss_done, rstval;
228 int syss_offset, error = 0;
230 if (ddata->cap->regbits->srst_shift < 0)
233 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
234 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
236 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
239 syss_done = ddata->cfg.syss_mask;
241 if (syss_offset >= 0) {
242 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
243 rstval, (rstval & ddata->cfg.syss_mask) ==
244 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
246 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
247 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
248 rstval, !(rstval & sysc_mask),
249 100, MAX_MODULE_SOFTRESET_WAIT);
255 static int sysc_add_named_clock_from_child(struct sysc *ddata,
257 const char *optfck_name)
259 struct device_node *np = ddata->dev->of_node;
260 struct device_node *child;
261 struct clk_lookup *cl;
270 /* Does the clock alias already exist? */
271 clock = of_clk_get_by_name(np, n);
272 if (!IS_ERR(clock)) {
278 child = of_get_next_available_child(np, NULL);
282 clock = devm_get_clk_from_child(ddata->dev, child, name);
284 return PTR_ERR(clock);
287 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
288 * limit for clk_get(). If cl ever needs to be freed, it should be done
289 * with clkdev_drop().
291 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
296 cl->dev_id = dev_name(ddata->dev);
305 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
307 const char *optfck_name;
310 if (ddata->nr_clocks < SYSC_OPTFCK0)
311 index = SYSC_OPTFCK0;
313 index = ddata->nr_clocks;
318 optfck_name = clock_names[index];
320 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
324 ddata->clock_roles[index] = optfck_name;
330 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
332 int error, i, index = -ENODEV;
334 if (!strncmp(clock_names[SYSC_FCK], name, 3))
336 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
340 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
341 if (!ddata->clocks[i]) {
349 dev_err(ddata->dev, "clock %s not added\n", name);
353 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
354 if (IS_ERR(ddata->clocks[index])) {
355 dev_err(ddata->dev, "clock get error for %s: %li\n",
356 name, PTR_ERR(ddata->clocks[index]));
358 return PTR_ERR(ddata->clocks[index]);
361 error = clk_prepare(ddata->clocks[index]);
363 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
372 static int sysc_get_clocks(struct sysc *ddata)
374 struct device_node *np = ddata->dev->of_node;
375 struct property *prop;
377 int nr_fck = 0, nr_ick = 0, i, error = 0;
379 ddata->clock_roles = devm_kcalloc(ddata->dev,
381 sizeof(*ddata->clock_roles),
383 if (!ddata->clock_roles)
386 of_property_for_each_string(np, "clock-names", prop, name) {
387 if (!strncmp(clock_names[SYSC_FCK], name, 3))
389 if (!strncmp(clock_names[SYSC_ICK], name, 3))
391 ddata->clock_roles[ddata->nr_clocks] = name;
395 if (ddata->nr_clocks < 1)
398 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
399 error = sysc_init_ext_opt_clock(ddata, NULL);
404 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
405 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
410 if (nr_fck > 1 || nr_ick > 1) {
411 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
416 /* Always add a slot for main clocks fck and ick even if unused */
422 ddata->clocks = devm_kcalloc(ddata->dev,
423 ddata->nr_clocks, sizeof(*ddata->clocks),
428 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
429 const char *name = ddata->clock_roles[i];
434 error = sysc_get_one_clock(ddata, name);
442 static int sysc_enable_main_clocks(struct sysc *ddata)
450 for (i = 0; i < SYSC_OPTFCK0; i++) {
451 clock = ddata->clocks[i];
453 /* Main clocks may not have ick */
454 if (IS_ERR_OR_NULL(clock))
457 error = clk_enable(clock);
465 for (i--; i >= 0; i--) {
466 clock = ddata->clocks[i];
468 /* Main clocks may not have ick */
469 if (IS_ERR_OR_NULL(clock))
478 static void sysc_disable_main_clocks(struct sysc *ddata)
486 for (i = 0; i < SYSC_OPTFCK0; i++) {
487 clock = ddata->clocks[i];
488 if (IS_ERR_OR_NULL(clock))
495 static int sysc_enable_opt_clocks(struct sysc *ddata)
500 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
503 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
504 clock = ddata->clocks[i];
506 /* Assume no holes for opt clocks */
507 if (IS_ERR_OR_NULL(clock))
510 error = clk_enable(clock);
518 for (i--; i >= 0; i--) {
519 clock = ddata->clocks[i];
520 if (IS_ERR_OR_NULL(clock))
529 static void sysc_disable_opt_clocks(struct sysc *ddata)
534 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
537 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
538 clock = ddata->clocks[i];
540 /* Assume no holes for opt clocks */
541 if (IS_ERR_OR_NULL(clock))
548 static void sysc_clkdm_deny_idle(struct sysc *ddata)
550 struct ti_sysc_platform_data *pdata;
552 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
555 pdata = dev_get_platdata(ddata->dev);
556 if (pdata && pdata->clkdm_deny_idle)
557 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
560 static void sysc_clkdm_allow_idle(struct sysc *ddata)
562 struct ti_sysc_platform_data *pdata;
564 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
567 pdata = dev_get_platdata(ddata->dev);
568 if (pdata && pdata->clkdm_allow_idle)
569 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
573 * sysc_init_resets - init rstctrl reset line if configured
574 * @ddata: device driver data
576 * See sysc_rstctrl_reset_deassert().
578 static int sysc_init_resets(struct sysc *ddata)
581 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
583 return PTR_ERR_OR_ZERO(ddata->rsts);
587 * sysc_parse_and_check_child_range - parses module IO region from ranges
588 * @ddata: device driver data
590 * In general we only need rev, syss, and sysc registers and not the whole
591 * module range. But we do want the offsets for these registers from the
592 * module base. This allows us to check them against the legacy hwmod
593 * platform data. Let's also check the ranges are configured properly.
595 static int sysc_parse_and_check_child_range(struct sysc *ddata)
597 struct device_node *np = ddata->dev->of_node;
598 const __be32 *ranges;
599 u32 nr_addr, nr_size;
602 ranges = of_get_property(np, "ranges", &len);
604 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
609 len /= sizeof(*ranges);
612 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
617 error = of_property_read_u32(np, "#address-cells", &nr_addr);
621 error = of_property_read_u32(np, "#size-cells", &nr_size);
625 if (nr_addr != 1 || nr_size != 1) {
626 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
632 ddata->module_pa = of_translate_address(np, ranges++);
633 ddata->module_size = be32_to_cpup(ranges);
638 static struct device_node *stdout_path;
640 static void sysc_init_stdout_path(struct sysc *ddata)
642 struct device_node *np = NULL;
645 if (IS_ERR(stdout_path))
651 np = of_find_node_by_path("/chosen");
655 uart = of_get_property(np, "stdout-path", NULL);
659 np = of_find_node_by_path(uart);
668 stdout_path = ERR_PTR(-ENODEV);
671 static void sysc_check_quirk_stdout(struct sysc *ddata,
672 struct device_node *np)
674 sysc_init_stdout_path(ddata);
675 if (np != stdout_path)
678 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
679 SYSC_QUIRK_NO_RESET_ON_INIT;
683 * sysc_check_one_child - check child configuration
684 * @ddata: device driver data
685 * @np: child device node
687 * Let's avoid messy situations where we have new interconnect target
688 * node but children have "ti,hwmods". These belong to the interconnect
689 * target node and are managed by this driver.
691 static void sysc_check_one_child(struct sysc *ddata,
692 struct device_node *np)
696 name = of_get_property(np, "ti,hwmods", NULL);
697 if (name && !of_device_is_compatible(np, "ti,sysc"))
698 dev_warn(ddata->dev, "really a child ti,hwmods property?");
700 sysc_check_quirk_stdout(ddata, np);
701 sysc_parse_dts_quirks(ddata, np, true);
704 static void sysc_check_children(struct sysc *ddata)
706 struct device_node *child;
708 for_each_child_of_node(ddata->dev->of_node, child)
709 sysc_check_one_child(ddata, child);
713 * So far only I2C uses 16-bit read access with clockactivity with revision
714 * in two registers with stride of 4. We can detect this based on the rev
715 * register size to configure things far enough to be able to properly read
716 * the revision register.
718 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
720 if (resource_size(res) == 8)
721 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
725 * sysc_parse_one - parses the interconnect target module registers
726 * @ddata: device driver data
727 * @reg: register to parse
729 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
731 struct resource *res;
738 name = reg_names[reg];
744 res = platform_get_resource_byname(to_platform_device(ddata->dev),
745 IORESOURCE_MEM, name);
747 ddata->offsets[reg] = -ENODEV;
752 ddata->offsets[reg] = res->start - ddata->module_pa;
753 if (reg == SYSC_REVISION)
754 sysc_check_quirk_16bit(ddata, res);
759 static int sysc_parse_registers(struct sysc *ddata)
763 for (i = 0; i < SYSC_MAX_REGS; i++) {
764 error = sysc_parse_one(ddata, i);
773 * sysc_check_registers - check for misconfigured register overlaps
774 * @ddata: device driver data
776 static int sysc_check_registers(struct sysc *ddata)
778 int i, j, nr_regs = 0, nr_matches = 0;
780 for (i = 0; i < SYSC_MAX_REGS; i++) {
781 if (ddata->offsets[i] < 0)
784 if (ddata->offsets[i] > (ddata->module_size - 4)) {
785 dev_err(ddata->dev, "register outside module range");
790 for (j = 0; j < SYSC_MAX_REGS; j++) {
791 if (ddata->offsets[j] < 0)
794 if (ddata->offsets[i] == ddata->offsets[j])
800 if (nr_matches > nr_regs) {
801 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
802 nr_regs, nr_matches);
811 * syc_ioremap - ioremap register space for the interconnect target module
812 * @ddata: device driver data
814 * Note that the interconnect target module registers can be anywhere
815 * within the interconnect target module range. For example, SGX has
816 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
817 * has them at offset 0x1200 in the CPSW_WR child. Usually the
818 * the interconnect target module registers are at the beginning of
819 * the module range though.
821 static int sysc_ioremap(struct sysc *ddata)
825 if (ddata->offsets[SYSC_REVISION] < 0 &&
826 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
827 ddata->offsets[SYSC_SYSSTATUS] < 0) {
828 size = ddata->module_size;
830 size = max3(ddata->offsets[SYSC_REVISION],
831 ddata->offsets[SYSC_SYSCONFIG],
832 ddata->offsets[SYSC_SYSSTATUS]);
837 if ((size + sizeof(u32)) > ddata->module_size)
838 size = ddata->module_size;
841 ddata->module_va = devm_ioremap(ddata->dev,
844 if (!ddata->module_va)
851 * sysc_map_and_check_registers - ioremap and check device registers
852 * @ddata: device driver data
854 static int sysc_map_and_check_registers(struct sysc *ddata)
858 error = sysc_parse_and_check_child_range(ddata);
862 sysc_check_children(ddata);
864 error = sysc_parse_registers(ddata);
868 error = sysc_ioremap(ddata);
872 error = sysc_check_registers(ddata);
880 * sysc_show_rev - read and show interconnect target module revision
881 * @bufp: buffer to print the information to
882 * @ddata: device driver data
884 static int sysc_show_rev(char *bufp, struct sysc *ddata)
888 if (ddata->offsets[SYSC_REVISION] < 0)
889 return sprintf(bufp, ":NA");
891 len = sprintf(bufp, ":%08x", ddata->revision);
896 static int sysc_show_reg(struct sysc *ddata,
897 char *bufp, enum sysc_registers reg)
899 if (ddata->offsets[reg] < 0)
900 return sprintf(bufp, ":NA");
902 return sprintf(bufp, ":%x", ddata->offsets[reg]);
905 static int sysc_show_name(char *bufp, struct sysc *ddata)
910 return sprintf(bufp, ":%s", ddata->name);
914 * sysc_show_registers - show information about interconnect target module
915 * @ddata: device driver data
917 static void sysc_show_registers(struct sysc *ddata)
923 for (i = 0; i < SYSC_MAX_REGS; i++)
924 bufp += sysc_show_reg(ddata, bufp, i);
926 bufp += sysc_show_rev(bufp, ddata);
927 bufp += sysc_show_name(bufp, ddata);
929 dev_dbg(ddata->dev, "%llx:%x%s\n",
930 ddata->module_pa, ddata->module_size,
935 * sysc_write_sysconfig - handle sysconfig quirks for register write
936 * @ddata: device driver data
937 * @value: register value
939 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
941 if (ddata->module_unlock_quirk)
942 ddata->module_unlock_quirk(ddata);
944 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
946 if (ddata->module_lock_quirk)
947 ddata->module_lock_quirk(ddata);
950 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
951 #define SYSC_CLOCACT_ICK 2
953 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
954 static int sysc_enable_module(struct device *dev)
957 const struct sysc_regbits *regbits;
958 u32 reg, idlemodes, best_mode;
961 ddata = dev_get_drvdata(dev);
964 * Some modules like DSS reset automatically on idle. Enable optional
965 * reset clocks and wait for OCP softreset to complete.
967 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
968 error = sysc_enable_opt_clocks(ddata);
971 "Optional clocks failed for enable: %i\n",
977 * Some modules like i2c and hdq1w have unusable reset status unless
978 * the module reset quirk is enabled. Skip status check on enable.
980 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
981 error = sysc_wait_softreset(ddata);
983 dev_warn(ddata->dev, "OCP softreset timed out\n");
985 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
986 sysc_disable_opt_clocks(ddata);
989 * Some subsystem private interconnects, like DSS top level module,
990 * need only the automatic OCP softreset handling with no sysconfig
991 * register bits to configure.
993 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
996 regbits = ddata->cap->regbits;
997 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1000 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1001 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1002 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1004 if (regbits->clkact_shift >= 0 &&
1005 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1006 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1008 /* Set SIDLE mode */
1009 idlemodes = ddata->cfg.sidlemodes;
1010 if (!idlemodes || regbits->sidle_shift < 0)
1013 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1014 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1015 best_mode = SYSC_IDLE_NO;
1017 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1018 if (best_mode > SYSC_IDLE_MASK) {
1019 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1024 if (regbits->enwkup_shift >= 0 &&
1025 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1026 reg |= BIT(regbits->enwkup_shift);
1029 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1030 reg |= best_mode << regbits->sidle_shift;
1031 sysc_write_sysconfig(ddata, reg);
1034 /* Set MIDLE mode */
1035 idlemodes = ddata->cfg.midlemodes;
1036 if (!idlemodes || regbits->midle_shift < 0)
1039 best_mode = fls(ddata->cfg.midlemodes) - 1;
1040 if (best_mode > SYSC_IDLE_MASK) {
1041 dev_err(dev, "%s: invalid midlemode\n", __func__);
1045 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1046 best_mode = SYSC_IDLE_NO;
1048 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1049 reg |= best_mode << regbits->midle_shift;
1050 sysc_write_sysconfig(ddata, reg);
1053 /* Autoidle bit must enabled separately if available */
1054 if (regbits->autoidle_shift >= 0 &&
1055 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1056 reg |= 1 << regbits->autoidle_shift;
1057 sysc_write_sysconfig(ddata, reg);
1060 /* Flush posted write */
1061 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1063 if (ddata->module_enable_quirk)
1064 ddata->module_enable_quirk(ddata);
1069 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1071 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1072 *best_mode = SYSC_IDLE_SMART_WKUP;
1073 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1074 *best_mode = SYSC_IDLE_SMART;
1075 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1076 *best_mode = SYSC_IDLE_FORCE;
1083 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1084 static int sysc_disable_module(struct device *dev)
1087 const struct sysc_regbits *regbits;
1088 u32 reg, idlemodes, best_mode;
1091 ddata = dev_get_drvdata(dev);
1092 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1095 if (ddata->module_disable_quirk)
1096 ddata->module_disable_quirk(ddata);
1098 regbits = ddata->cap->regbits;
1099 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1101 /* Set MIDLE mode */
1102 idlemodes = ddata->cfg.midlemodes;
1103 if (!idlemodes || regbits->midle_shift < 0)
1106 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1108 dev_err(dev, "%s: invalid midlemode\n", __func__);
1112 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1113 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1114 best_mode = SYSC_IDLE_FORCE;
1116 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1117 reg |= best_mode << regbits->midle_shift;
1118 sysc_write_sysconfig(ddata, reg);
1121 /* Set SIDLE mode */
1122 idlemodes = ddata->cfg.sidlemodes;
1123 if (!idlemodes || regbits->sidle_shift < 0)
1126 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1127 best_mode = SYSC_IDLE_FORCE;
1129 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1131 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1136 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1137 reg |= best_mode << regbits->sidle_shift;
1138 if (regbits->autoidle_shift >= 0 &&
1139 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1140 reg |= 1 << regbits->autoidle_shift;
1141 sysc_write_sysconfig(ddata, reg);
1143 /* Flush posted write */
1144 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1149 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1152 struct ti_sysc_platform_data *pdata;
1155 pdata = dev_get_platdata(ddata->dev);
1159 if (!pdata->idle_module)
1162 error = pdata->idle_module(dev, &ddata->cookie);
1164 dev_err(dev, "%s: could not idle: %i\n",
1167 reset_control_assert(ddata->rsts);
1172 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1175 struct ti_sysc_platform_data *pdata;
1178 pdata = dev_get_platdata(ddata->dev);
1182 if (!pdata->enable_module)
1185 error = pdata->enable_module(dev, &ddata->cookie);
1187 dev_err(dev, "%s: could not enable: %i\n",
1190 reset_control_deassert(ddata->rsts);
1195 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1200 ddata = dev_get_drvdata(dev);
1202 if (!ddata->enabled)
1205 sysc_clkdm_deny_idle(ddata);
1207 if (ddata->legacy_mode) {
1208 error = sysc_runtime_suspend_legacy(dev, ddata);
1210 goto err_allow_idle;
1212 error = sysc_disable_module(dev);
1214 goto err_allow_idle;
1217 sysc_disable_main_clocks(ddata);
1219 if (sysc_opt_clks_needed(ddata))
1220 sysc_disable_opt_clocks(ddata);
1222 ddata->enabled = false;
1225 reset_control_assert(ddata->rsts);
1227 sysc_clkdm_allow_idle(ddata);
1232 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1237 ddata = dev_get_drvdata(dev);
1243 sysc_clkdm_deny_idle(ddata);
1245 if (sysc_opt_clks_needed(ddata)) {
1246 error = sysc_enable_opt_clocks(ddata);
1248 goto err_allow_idle;
1251 error = sysc_enable_main_clocks(ddata);
1253 goto err_opt_clocks;
1255 reset_control_deassert(ddata->rsts);
1257 if (ddata->legacy_mode) {
1258 error = sysc_runtime_resume_legacy(dev, ddata);
1260 goto err_main_clocks;
1262 error = sysc_enable_module(dev);
1264 goto err_main_clocks;
1267 ddata->enabled = true;
1269 sysc_clkdm_allow_idle(ddata);
1274 sysc_disable_main_clocks(ddata);
1276 if (sysc_opt_clks_needed(ddata))
1277 sysc_disable_opt_clocks(ddata);
1279 sysc_clkdm_allow_idle(ddata);
1284 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1288 ddata = dev_get_drvdata(dev);
1290 if (ddata->cfg.quirks &
1291 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1294 return pm_runtime_force_suspend(dev);
1297 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1301 ddata = dev_get_drvdata(dev);
1303 if (ddata->cfg.quirks &
1304 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1307 return pm_runtime_force_resume(dev);
1310 static const struct dev_pm_ops sysc_pm_ops = {
1311 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1312 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1313 sysc_runtime_resume,
1317 /* Module revision register based quirks */
1318 struct sysc_revision_quirk {
1329 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1330 optrev_val, optrevmask, optquirkmask) \
1332 .name = (optname), \
1333 .base = (optbase), \
1334 .rev_offset = (optrev), \
1335 .sysc_offset = (optsysc), \
1336 .syss_offset = (optsyss), \
1337 .revision = (optrev_val), \
1338 .revision_mask = (optrevmask), \
1339 .quirks = (optquirkmask), \
1342 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1343 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1344 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1345 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1346 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1347 SYSC_QUIRK_LEGACY_IDLE),
1348 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
1349 SYSC_QUIRK_LEGACY_IDLE),
1350 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
1351 SYSC_QUIRK_LEGACY_IDLE),
1352 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1353 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1354 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1355 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1356 /* Uarts on omap4 and later */
1357 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1358 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1359 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1360 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1362 /* Quirks that need to be set based on the module address */
1363 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1364 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1365 SYSC_QUIRK_SWSUP_SIDLE),
1367 /* Quirks that need to be set based on detected module */
1368 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1369 SYSC_MODULE_QUIRK_AESS),
1370 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1371 SYSC_QUIRK_CLKDM_NOAUTO),
1372 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1373 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1374 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1375 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1376 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1377 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1378 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1379 SYSC_QUIRK_CLKDM_NOAUTO),
1380 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1381 SYSC_QUIRK_CLKDM_NOAUTO),
1382 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1383 SYSC_QUIRK_OPT_CLKS_NEEDED),
1384 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1385 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1386 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1387 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1388 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1389 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1390 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1391 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1392 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1393 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1394 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1395 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1396 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1397 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1398 SYSC_MODULE_QUIRK_SGX),
1399 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1400 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1401 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1402 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1403 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1404 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1405 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1406 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1407 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1408 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1409 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1410 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1411 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1412 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1413 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1414 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1415 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1416 SYSC_MODULE_QUIRK_WDT),
1417 /* PRUSS on am3, am4 and am5 */
1418 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1419 SYSC_MODULE_QUIRK_PRUSS),
1420 /* Watchdog on am3 and am4 */
1421 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1422 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1425 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1426 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1427 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1428 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1429 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1431 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1432 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1433 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1434 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1435 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1436 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1437 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1438 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1439 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1440 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1441 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1442 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1443 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1444 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1445 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1446 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1447 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1448 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1449 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1450 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1451 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1452 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1453 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1454 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1455 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1456 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1457 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1458 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1459 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1460 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1461 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1462 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1463 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1464 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1465 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1466 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1467 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1468 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1469 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1470 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1471 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1472 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1473 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1474 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1475 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1476 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1477 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1478 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1479 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1480 /* Some timers on omap4 and later */
1481 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1482 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1483 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1484 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1485 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1486 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1487 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1488 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1489 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1490 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1495 * Early quirks based on module base and register offsets only that are
1496 * needed before the module revision can be read
1498 static void sysc_init_early_quirks(struct sysc *ddata)
1500 const struct sysc_revision_quirk *q;
1503 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1504 q = &sysc_revision_quirks[i];
1509 if (q->base != ddata->module_pa)
1512 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1515 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1518 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1521 ddata->name = q->name;
1522 ddata->cfg.quirks |= q->quirks;
1526 /* Quirks that also consider the revision register value */
1527 static void sysc_init_revision_quirks(struct sysc *ddata)
1529 const struct sysc_revision_quirk *q;
1532 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1533 q = &sysc_revision_quirks[i];
1535 if (q->base && q->base != ddata->module_pa)
1538 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1541 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1544 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1547 if (q->revision == ddata->revision ||
1548 (q->revision & q->revision_mask) ==
1549 (ddata->revision & q->revision_mask)) {
1550 ddata->name = q->name;
1551 ddata->cfg.quirks |= q->quirks;
1557 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1558 * enabled DSS interrupts. Eventually we may be able to do this on
1559 * dispc init rather than top-level DSS init.
1561 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1564 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1565 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1567 bool framedonetv_irq = true;
1568 u32 val, irq_mask = 0;
1570 switch (sysc_soc->soc) {
1571 case SOC_2420 ... SOC_3630:
1573 framedonetv_irq = false;
1575 case SOC_4430 ... SOC_4470:
1584 framedonetv_irq = false;
1591 /* Remap the whole module range to be able to reset dispc outputs */
1592 devm_iounmap(ddata->dev, ddata->module_va);
1593 ddata->module_va = devm_ioremap(ddata->dev,
1595 ddata->module_size);
1596 if (!ddata->module_va)
1600 val = sysc_read(ddata, dispc_offset + 0x40);
1601 lcd_en = val & lcd_en_mask;
1602 digit_en = val & digit_en_mask;
1604 irq_mask |= BIT(0); /* FRAMEDONE */
1606 if (framedonetv_irq)
1607 irq_mask |= BIT(24); /* FRAMEDONETV */
1609 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1611 if (disable & (lcd_en | digit_en))
1612 sysc_write(ddata, dispc_offset + 0x40,
1613 val & ~(lcd_en_mask | digit_en_mask));
1615 if (manager_count <= 2)
1618 /* DISPC_CONTROL2 */
1619 val = sysc_read(ddata, dispc_offset + 0x238);
1620 lcd2_en = val & lcd_en_mask;
1622 irq_mask |= BIT(22); /* FRAMEDONE2 */
1623 if (disable && lcd2_en)
1624 sysc_write(ddata, dispc_offset + 0x238,
1625 val & ~lcd_en_mask);
1627 if (manager_count <= 3)
1630 /* DISPC_CONTROL3 */
1631 val = sysc_read(ddata, dispc_offset + 0x848);
1632 lcd3_en = val & lcd_en_mask;
1634 irq_mask |= BIT(30); /* FRAMEDONE3 */
1635 if (disable && lcd3_en)
1636 sysc_write(ddata, dispc_offset + 0x848,
1637 val & ~lcd_en_mask);
1642 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1643 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1645 const int dispc_offset = 0x1000;
1649 /* Get enabled outputs */
1650 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1654 /* Clear IRQSTATUS */
1655 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1657 /* Disable outputs */
1658 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1660 /* Poll IRQSTATUS */
1661 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1662 val, val != irq_mask, 100, 50);
1664 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1665 __func__, val, irq_mask);
1667 if (sysc_soc->soc == SOC_3430) {
1668 /* Clear DSS_SDI_CONTROL */
1669 sysc_write(ddata, 0x44, 0);
1671 /* Clear DSS_PLL_CONTROL */
1672 sysc_write(ddata, 0x48, 0);
1675 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1676 sysc_write(ddata, 0x40, 0);
1679 /* 1-wire needs module's internal clocks enabled for reset */
1680 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1682 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1685 val = sysc_read(ddata, offset);
1687 sysc_write(ddata, offset, val);
1690 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1691 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1693 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1695 sysc_write(ddata, offset, 1);
1698 /* I2C needs to be disabled for reset */
1699 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1704 /* I2C_CON, omap2/3 is different from omap4 and later */
1705 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1711 val = sysc_read(ddata, offset);
1716 sysc_write(ddata, offset, val);
1719 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1721 sysc_clk_quirk_i2c(ddata, false);
1724 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1726 sysc_clk_quirk_i2c(ddata, true);
1729 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1730 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1732 u32 val, kick0_val = 0, kick1_val = 0;
1733 unsigned long flags;
1737 kick0_val = 0x83e70b13;
1738 kick1_val = 0x95a4f1e0;
1741 local_irq_save(flags);
1742 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1743 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1744 !(val & BIT(0)), 100, 50);
1746 dev_warn(ddata->dev, "rtc busy timeout\n");
1747 /* Now we have ~15 microseconds to read/write various registers */
1748 sysc_write(ddata, 0x6c, kick0_val);
1749 sysc_write(ddata, 0x70, kick1_val);
1750 local_irq_restore(flags);
1753 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1755 sysc_quirk_rtc(ddata, false);
1758 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1760 sysc_quirk_rtc(ddata, true);
1763 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1764 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1766 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1767 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1769 sysc_write(ddata, offset, val);
1772 /* Watchdog timer needs a disable sequence after reset */
1773 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1775 int wps, spr, error;
1781 sysc_write(ddata, spr, 0xaaaa);
1782 error = readl_poll_timeout(ddata->module_va + wps, val,
1784 MAX_MODULE_SOFTRESET_WAIT);
1786 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1788 sysc_write(ddata, spr, 0x5555);
1789 error = readl_poll_timeout(ddata->module_va + wps, val,
1791 MAX_MODULE_SOFTRESET_WAIT);
1793 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1796 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1797 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1801 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1802 reg |= SYSC_PRUSS_STANDBY_INIT;
1803 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1806 static void sysc_init_module_quirks(struct sysc *ddata)
1808 if (ddata->legacy_mode || !ddata->name)
1811 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1812 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1817 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1818 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1819 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
1824 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1825 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1827 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
1828 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
1830 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1831 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1832 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1837 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1838 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1840 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1841 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1842 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1845 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
1846 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
1849 static int sysc_clockdomain_init(struct sysc *ddata)
1851 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1852 struct clk *fck = NULL, *ick = NULL;
1855 if (!pdata || !pdata->init_clockdomain)
1858 switch (ddata->nr_clocks) {
1860 ick = ddata->clocks[SYSC_ICK];
1863 fck = ddata->clocks[SYSC_FCK];
1869 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1870 if (!error || error == -ENODEV)
1877 * Note that pdata->init_module() typically does a reset first. After
1878 * pdata->init_module() is done, PM runtime can be used for the interconnect
1881 static int sysc_legacy_init(struct sysc *ddata)
1883 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1886 if (!pdata || !pdata->init_module)
1889 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1890 if (error == -EEXIST)
1897 * Note that the caller must ensure the interconnect target module is enabled
1898 * before calling reset. Otherwise reset will not complete.
1900 static int sysc_reset(struct sysc *ddata)
1902 int sysc_offset, sysc_val, error;
1905 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1907 if (ddata->legacy_mode ||
1908 ddata->cap->regbits->srst_shift < 0 ||
1909 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1912 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1914 if (ddata->pre_reset_quirk)
1915 ddata->pre_reset_quirk(ddata);
1917 if (sysc_offset >= 0) {
1918 sysc_val = sysc_read_sysconfig(ddata);
1919 sysc_val |= sysc_mask;
1920 sysc_write(ddata, sysc_offset, sysc_val);
1923 if (ddata->cfg.srst_udelay)
1924 usleep_range(ddata->cfg.srst_udelay,
1925 ddata->cfg.srst_udelay * 2);
1927 if (ddata->post_reset_quirk)
1928 ddata->post_reset_quirk(ddata);
1930 error = sysc_wait_softreset(ddata);
1932 dev_warn(ddata->dev, "OCP softreset timed out\n");
1934 if (ddata->reset_done_quirk)
1935 ddata->reset_done_quirk(ddata);
1941 * At this point the module is configured enough to read the revision but
1942 * module may not be completely configured yet to use PM runtime. Enable
1943 * all clocks directly during init to configure the quirks needed for PM
1944 * runtime based on the revision register.
1946 static int sysc_init_module(struct sysc *ddata)
1950 error = sysc_clockdomain_init(ddata);
1954 sysc_clkdm_deny_idle(ddata);
1957 * Always enable clocks. The bootloader may or may not have enabled
1958 * the related clocks.
1960 error = sysc_enable_opt_clocks(ddata);
1964 error = sysc_enable_main_clocks(ddata);
1966 goto err_opt_clocks;
1968 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1969 error = reset_control_deassert(ddata->rsts);
1971 goto err_main_clocks;
1974 ddata->revision = sysc_read_revision(ddata);
1975 sysc_init_revision_quirks(ddata);
1976 sysc_init_module_quirks(ddata);
1978 if (ddata->legacy_mode) {
1979 error = sysc_legacy_init(ddata);
1984 if (!ddata->legacy_mode) {
1985 error = sysc_enable_module(ddata->dev);
1990 error = sysc_reset(ddata);
1992 dev_err(ddata->dev, "Reset failed with %d\n", error);
1994 if (error && !ddata->legacy_mode)
1995 sysc_disable_module(ddata->dev);
1998 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
1999 reset_control_assert(ddata->rsts);
2003 sysc_disable_main_clocks(ddata);
2005 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2007 sysc_disable_opt_clocks(ddata);
2008 sysc_clkdm_allow_idle(ddata);
2014 static int sysc_init_sysc_mask(struct sysc *ddata)
2016 struct device_node *np = ddata->dev->of_node;
2020 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2024 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2029 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2032 struct device_node *np = ddata->dev->of_node;
2033 struct property *prop;
2037 of_property_for_each_u32(np, name, prop, p, val) {
2038 if (val >= SYSC_NR_IDLEMODES) {
2039 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2042 *idlemodes |= (1 << val);
2048 static int sysc_init_idlemodes(struct sysc *ddata)
2052 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2057 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2066 * Only some devices on omap4 and later have SYSCONFIG reset done
2067 * bit. We can detect this if there is no SYSSTATUS at all, or the
2068 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2069 * have multiple bits for the child devices like OHCI and EHCI.
2070 * Depends on SYSC being parsed first.
2072 static int sysc_init_syss_mask(struct sysc *ddata)
2074 struct device_node *np = ddata->dev->of_node;
2078 error = of_property_read_u32(np, "ti,syss-mask", &val);
2080 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2081 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2082 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2083 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2088 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2089 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2091 ddata->cfg.syss_mask = val;
2097 * Many child device drivers need to have fck and opt clocks available
2098 * to get the clock rate for device internal configuration etc.
2100 static int sysc_child_add_named_clock(struct sysc *ddata,
2101 struct device *child,
2105 struct clk_lookup *l;
2111 clk = clk_get(child, name);
2117 clk = clk_get(ddata->dev, name);
2121 l = clkdev_create(clk, name, dev_name(child));
2130 static int sysc_child_add_clocks(struct sysc *ddata,
2131 struct device *child)
2135 for (i = 0; i < ddata->nr_clocks; i++) {
2136 error = sysc_child_add_named_clock(ddata,
2138 ddata->clock_roles[i]);
2139 if (error && error != -EEXIST) {
2140 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2141 ddata->clock_roles[i], error);
2150 static struct device_type sysc_device_type = {
2153 static struct sysc *sysc_child_to_parent(struct device *dev)
2155 struct device *parent = dev->parent;
2157 if (!parent || parent->type != &sysc_device_type)
2160 return dev_get_drvdata(parent);
2163 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2168 ddata = sysc_child_to_parent(dev);
2170 error = pm_generic_runtime_suspend(dev);
2174 if (!ddata->enabled)
2177 return sysc_runtime_suspend(ddata->dev);
2180 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2185 ddata = sysc_child_to_parent(dev);
2187 if (!ddata->enabled) {
2188 error = sysc_runtime_resume(ddata->dev);
2191 "%s error: %i\n", __func__, error);
2194 return pm_generic_runtime_resume(dev);
2197 #ifdef CONFIG_PM_SLEEP
2198 static int sysc_child_suspend_noirq(struct device *dev)
2203 ddata = sysc_child_to_parent(dev);
2205 dev_dbg(ddata->dev, "%s %s\n", __func__,
2206 ddata->name ? ddata->name : "");
2208 error = pm_generic_suspend_noirq(dev);
2210 dev_err(dev, "%s error at %i: %i\n",
2211 __func__, __LINE__, error);
2216 if (!pm_runtime_status_suspended(dev)) {
2217 error = pm_generic_runtime_suspend(dev);
2219 dev_dbg(dev, "%s busy at %i: %i\n",
2220 __func__, __LINE__, error);
2225 error = sysc_runtime_suspend(ddata->dev);
2227 dev_err(dev, "%s error at %i: %i\n",
2228 __func__, __LINE__, error);
2233 ddata->child_needs_resume = true;
2239 static int sysc_child_resume_noirq(struct device *dev)
2244 ddata = sysc_child_to_parent(dev);
2246 dev_dbg(ddata->dev, "%s %s\n", __func__,
2247 ddata->name ? ddata->name : "");
2249 if (ddata->child_needs_resume) {
2250 ddata->child_needs_resume = false;
2252 error = sysc_runtime_resume(ddata->dev);
2255 "%s runtime resume error: %i\n",
2258 error = pm_generic_runtime_resume(dev);
2261 "%s generic runtime resume: %i\n",
2265 return pm_generic_resume_noirq(dev);
2269 static struct dev_pm_domain sysc_child_pm_domain = {
2271 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2272 sysc_child_runtime_resume,
2274 USE_PLATFORM_PM_SLEEP_OPS
2275 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2276 sysc_child_resume_noirq)
2281 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2282 * @ddata: device driver data
2283 * @child: child device driver
2285 * Allow idle for child devices as done with _od_runtime_suspend().
2286 * Otherwise many child devices will not idle because of the permanent
2287 * parent usecount set in pm_runtime_irq_safe().
2289 * Note that the long term solution is to just modify the child device
2290 * drivers to not set pm_runtime_irq_safe() and then this can be just
2293 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2295 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2296 dev_pm_domain_set(child, &sysc_child_pm_domain);
2299 static int sysc_notifier_call(struct notifier_block *nb,
2300 unsigned long event, void *device)
2302 struct device *dev = device;
2306 ddata = sysc_child_to_parent(dev);
2311 case BUS_NOTIFY_ADD_DEVICE:
2312 error = sysc_child_add_clocks(ddata, dev);
2315 sysc_legacy_idle_quirk(ddata, dev);
2324 static struct notifier_block sysc_nb = {
2325 .notifier_call = sysc_notifier_call,
2328 /* Device tree configured quirks */
2329 struct sysc_dts_quirk {
2334 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2335 { .name = "ti,no-idle-on-init",
2336 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2337 { .name = "ti,no-reset-on-init",
2338 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2339 { .name = "ti,no-idle",
2340 .mask = SYSC_QUIRK_NO_IDLE, },
2343 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2346 const struct property *prop;
2349 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2350 const char *name = sysc_dts_quirks[i].name;
2352 prop = of_get_property(np, name, &len);
2356 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2358 dev_warn(ddata->dev,
2359 "dts flag should be at module level for %s\n",
2365 static int sysc_init_dts_quirks(struct sysc *ddata)
2367 struct device_node *np = ddata->dev->of_node;
2371 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2373 sysc_parse_dts_quirks(ddata, np, false);
2374 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2377 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2381 ddata->cfg.srst_udelay = (u8)val;
2387 static void sysc_unprepare(struct sysc *ddata)
2394 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2395 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2396 clk_unprepare(ddata->clocks[i]);
2401 * Common sysc register bits found on omap2, also known as type1
2403 static const struct sysc_regbits sysc_regbits_omap2 = {
2404 .dmadisable_shift = -ENODEV,
2411 .autoidle_shift = 0,
2414 static const struct sysc_capabilities sysc_omap2 = {
2415 .type = TI_SYSC_OMAP2,
2416 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2417 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2418 SYSC_OMAP2_AUTOIDLE,
2419 .regbits = &sysc_regbits_omap2,
2422 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2423 static const struct sysc_capabilities sysc_omap2_timer = {
2424 .type = TI_SYSC_OMAP2_TIMER,
2425 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2426 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2427 SYSC_OMAP2_AUTOIDLE,
2428 .regbits = &sysc_regbits_omap2,
2429 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2433 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2434 * with different sidle position
2436 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2437 .dmadisable_shift = -ENODEV,
2438 .midle_shift = -ENODEV,
2440 .clkact_shift = -ENODEV,
2441 .enwkup_shift = -ENODEV,
2443 .autoidle_shift = 0,
2444 .emufree_shift = -ENODEV,
2447 static const struct sysc_capabilities sysc_omap3_sham = {
2448 .type = TI_SYSC_OMAP3_SHAM,
2449 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2450 .regbits = &sysc_regbits_omap3_sham,
2454 * AES register bits found on omap3 and later, a variant of
2455 * sysc_regbits_omap2 with different sidle position
2457 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2458 .dmadisable_shift = -ENODEV,
2459 .midle_shift = -ENODEV,
2461 .clkact_shift = -ENODEV,
2462 .enwkup_shift = -ENODEV,
2464 .autoidle_shift = 0,
2465 .emufree_shift = -ENODEV,
2468 static const struct sysc_capabilities sysc_omap3_aes = {
2469 .type = TI_SYSC_OMAP3_AES,
2470 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2471 .regbits = &sysc_regbits_omap3_aes,
2475 * Common sysc register bits found on omap4, also known as type2
2477 static const struct sysc_regbits sysc_regbits_omap4 = {
2478 .dmadisable_shift = 16,
2481 .clkact_shift = -ENODEV,
2482 .enwkup_shift = -ENODEV,
2485 .autoidle_shift = -ENODEV,
2488 static const struct sysc_capabilities sysc_omap4 = {
2489 .type = TI_SYSC_OMAP4,
2490 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2491 SYSC_OMAP4_SOFTRESET,
2492 .regbits = &sysc_regbits_omap4,
2495 static const struct sysc_capabilities sysc_omap4_timer = {
2496 .type = TI_SYSC_OMAP4_TIMER,
2497 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2498 SYSC_OMAP4_SOFTRESET,
2499 .regbits = &sysc_regbits_omap4,
2503 * Common sysc register bits found on omap4, also known as type3
2505 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2506 .dmadisable_shift = -ENODEV,
2509 .clkact_shift = -ENODEV,
2510 .enwkup_shift = -ENODEV,
2511 .srst_shift = -ENODEV,
2512 .emufree_shift = -ENODEV,
2513 .autoidle_shift = -ENODEV,
2516 static const struct sysc_capabilities sysc_omap4_simple = {
2517 .type = TI_SYSC_OMAP4_SIMPLE,
2518 .regbits = &sysc_regbits_omap4_simple,
2522 * SmartReflex sysc found on omap34xx
2524 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2525 .dmadisable_shift = -ENODEV,
2526 .midle_shift = -ENODEV,
2527 .sidle_shift = -ENODEV,
2529 .enwkup_shift = -ENODEV,
2530 .srst_shift = -ENODEV,
2531 .emufree_shift = -ENODEV,
2532 .autoidle_shift = -ENODEV,
2535 static const struct sysc_capabilities sysc_34xx_sr = {
2536 .type = TI_SYSC_OMAP34XX_SR,
2537 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2538 .regbits = &sysc_regbits_omap34xx_sr,
2539 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2540 SYSC_QUIRK_LEGACY_IDLE,
2544 * SmartReflex sysc found on omap36xx and later
2546 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2547 .dmadisable_shift = -ENODEV,
2548 .midle_shift = -ENODEV,
2550 .clkact_shift = -ENODEV,
2552 .srst_shift = -ENODEV,
2553 .emufree_shift = -ENODEV,
2554 .autoidle_shift = -ENODEV,
2557 static const struct sysc_capabilities sysc_36xx_sr = {
2558 .type = TI_SYSC_OMAP36XX_SR,
2559 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2560 .regbits = &sysc_regbits_omap36xx_sr,
2561 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2564 static const struct sysc_capabilities sysc_omap4_sr = {
2565 .type = TI_SYSC_OMAP4_SR,
2566 .regbits = &sysc_regbits_omap36xx_sr,
2567 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2571 * McASP register bits found on omap4 and later
2573 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2574 .dmadisable_shift = -ENODEV,
2575 .midle_shift = -ENODEV,
2577 .clkact_shift = -ENODEV,
2578 .enwkup_shift = -ENODEV,
2579 .srst_shift = -ENODEV,
2580 .emufree_shift = -ENODEV,
2581 .autoidle_shift = -ENODEV,
2584 static const struct sysc_capabilities sysc_omap4_mcasp = {
2585 .type = TI_SYSC_OMAP4_MCASP,
2586 .regbits = &sysc_regbits_omap4_mcasp,
2587 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2591 * McASP found on dra7 and later
2593 static const struct sysc_capabilities sysc_dra7_mcasp = {
2594 .type = TI_SYSC_OMAP4_SIMPLE,
2595 .regbits = &sysc_regbits_omap4_simple,
2596 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2600 * FS USB host found on omap4 and later
2602 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2603 .dmadisable_shift = -ENODEV,
2604 .midle_shift = -ENODEV,
2606 .clkact_shift = -ENODEV,
2608 .srst_shift = -ENODEV,
2609 .emufree_shift = -ENODEV,
2610 .autoidle_shift = -ENODEV,
2613 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2614 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2615 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2616 .regbits = &sysc_regbits_omap4_usb_host_fs,
2619 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2620 .dmadisable_shift = -ENODEV,
2621 .midle_shift = -ENODEV,
2622 .sidle_shift = -ENODEV,
2623 .clkact_shift = -ENODEV,
2626 .emufree_shift = -ENODEV,
2627 .autoidle_shift = -ENODEV,
2630 static const struct sysc_capabilities sysc_dra7_mcan = {
2631 .type = TI_SYSC_DRA7_MCAN,
2632 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2633 .regbits = &sysc_regbits_dra7_mcan,
2634 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2638 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2640 static const struct sysc_capabilities sysc_pruss = {
2641 .type = TI_SYSC_PRUSS,
2642 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2643 .regbits = &sysc_regbits_omap4_simple,
2644 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2647 static int sysc_init_pdata(struct sysc *ddata)
2649 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2650 struct ti_sysc_module_data *mdata;
2655 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2659 if (ddata->legacy_mode) {
2660 mdata->name = ddata->legacy_mode;
2661 mdata->module_pa = ddata->module_pa;
2662 mdata->module_size = ddata->module_size;
2663 mdata->offsets = ddata->offsets;
2664 mdata->nr_offsets = SYSC_MAX_REGS;
2665 mdata->cap = ddata->cap;
2666 mdata->cfg = &ddata->cfg;
2669 ddata->mdata = mdata;
2674 static int sysc_init_match(struct sysc *ddata)
2676 const struct sysc_capabilities *cap;
2678 cap = of_device_get_match_data(ddata->dev);
2684 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2689 static void ti_sysc_idle(struct work_struct *work)
2693 ddata = container_of(work, struct sysc, idle_work.work);
2696 * One time decrement of clock usage counts if left on from init.
2697 * Note that we disable opt clocks unconditionally in this case
2698 * as they are enabled unconditionally during init without
2699 * considering sysc_opt_clks_needed() at that point.
2701 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2702 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2703 sysc_disable_main_clocks(ddata);
2704 sysc_disable_opt_clocks(ddata);
2705 sysc_clkdm_allow_idle(ddata);
2708 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2709 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2713 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2714 * and SYSC_QUIRK_NO_RESET_ON_INIT
2716 if (pm_runtime_active(ddata->dev))
2717 pm_runtime_put_sync(ddata->dev);
2721 * SoC model and features detection. Only needed for SoCs that need
2722 * special handling for quirks, no need to list others.
2724 static const struct soc_device_attribute sysc_soc_match[] = {
2725 SOC_FLAG("OMAP242*", SOC_2420),
2726 SOC_FLAG("OMAP243*", SOC_2430),
2727 SOC_FLAG("OMAP3[45]*", SOC_3430),
2728 SOC_FLAG("OMAP3[67]*", SOC_3630),
2729 SOC_FLAG("OMAP443*", SOC_4430),
2730 SOC_FLAG("OMAP446*", SOC_4460),
2731 SOC_FLAG("OMAP447*", SOC_4470),
2732 SOC_FLAG("OMAP54*", SOC_5430),
2733 SOC_FLAG("AM433", SOC_AM3),
2734 SOC_FLAG("AM43*", SOC_AM4),
2735 SOC_FLAG("DRA7*", SOC_DRA7),
2741 * List of SoCs variants with disabled features. By default we assume all
2742 * devices in the device tree are available so no need to list those SoCs.
2744 static const struct soc_device_attribute sysc_soc_feat_match[] = {
2745 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2746 SOC_FLAG("AM3505", DIS_SGX),
2747 SOC_FLAG("OMAP3525", DIS_SGX),
2748 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2749 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2751 /* OMAP3630/DM3730 variants with some accelerators disabled */
2752 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2753 SOC_FLAG("DM3725", DIS_SGX),
2754 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2755 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2756 SOC_FLAG("OMAP3621", DIS_ISP),
2761 static int sysc_add_disabled(unsigned long base)
2763 struct sysc_address *disabled_module;
2765 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2766 if (!disabled_module)
2769 disabled_module->base = base;
2771 mutex_lock(&sysc_soc->list_lock);
2772 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
2773 mutex_unlock(&sysc_soc->list_lock);
2779 * One time init to detect the booted SoC and disable unavailable features.
2780 * Note that we initialize static data shared across all ti-sysc instances
2781 * so ddata is only used for SoC type. This can be called from module_init
2782 * once we no longer need to rely on platform data.
2784 static int sysc_init_soc(struct sysc *ddata)
2786 const struct soc_device_attribute *match;
2787 struct ti_sysc_platform_data *pdata;
2788 unsigned long features = 0;
2793 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
2797 mutex_init(&sysc_soc->list_lock);
2798 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
2799 sysc_soc->general_purpose = true;
2801 pdata = dev_get_platdata(ddata->dev);
2802 if (pdata && pdata->soc_type_gp)
2803 sysc_soc->general_purpose = pdata->soc_type_gp();
2805 match = soc_device_match(sysc_soc_match);
2806 if (match && match->data)
2807 sysc_soc->soc = (int)match->data;
2809 /* Ignore devices that are not available on HS and EMU SoCs */
2810 if (!sysc_soc->general_purpose) {
2811 switch (sysc_soc->soc) {
2812 case SOC_3430 ... SOC_3630:
2813 sysc_add_disabled(0x48304000); /* timer12 */
2820 match = soc_device_match(sysc_soc_feat_match);
2825 features = (unsigned long)match->data;
2828 * Add disabled devices to the list based on the module base.
2829 * Note that this must be done before we attempt to access the
2830 * device and have module revision checks working.
2832 if (features & DIS_ISP)
2833 sysc_add_disabled(0x480bd400);
2834 if (features & DIS_IVA)
2835 sysc_add_disabled(0x5d000000);
2836 if (features & DIS_SGX)
2837 sysc_add_disabled(0x50000000);
2842 static void sysc_cleanup_soc(void)
2844 struct sysc_address *disabled_module;
2845 struct list_head *pos, *tmp;
2850 mutex_lock(&sysc_soc->list_lock);
2851 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
2852 disabled_module = list_entry(pos, struct sysc_address, node);
2854 kfree(disabled_module);
2856 mutex_unlock(&sysc_soc->list_lock);
2859 static int sysc_check_disabled_devices(struct sysc *ddata)
2861 struct sysc_address *disabled_module;
2862 struct list_head *pos;
2865 mutex_lock(&sysc_soc->list_lock);
2866 list_for_each(pos, &sysc_soc->disabled_modules) {
2867 disabled_module = list_entry(pos, struct sysc_address, node);
2868 if (ddata->module_pa == disabled_module->base) {
2869 dev_dbg(ddata->dev, "module disabled for this SoC\n");
2874 mutex_unlock(&sysc_soc->list_lock);
2880 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
2881 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
2882 * are needed, we could also look at the timer register configuration.
2884 static int sysc_check_active_timer(struct sysc *ddata)
2886 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
2887 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
2890 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
2891 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
2897 static const struct of_device_id sysc_match_table[] = {
2898 { .compatible = "simple-bus", },
2902 static int sysc_probe(struct platform_device *pdev)
2904 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2908 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2912 ddata->dev = &pdev->dev;
2913 platform_set_drvdata(pdev, ddata);
2915 error = sysc_init_soc(ddata);
2919 error = sysc_init_match(ddata);
2923 error = sysc_init_dts_quirks(ddata);
2927 error = sysc_map_and_check_registers(ddata);
2931 error = sysc_init_sysc_mask(ddata);
2935 error = sysc_init_idlemodes(ddata);
2939 error = sysc_init_syss_mask(ddata);
2943 error = sysc_init_pdata(ddata);
2947 sysc_init_early_quirks(ddata);
2949 error = sysc_check_disabled_devices(ddata);
2953 error = sysc_check_active_timer(ddata);
2957 error = sysc_get_clocks(ddata);
2961 error = sysc_init_resets(ddata);
2965 error = sysc_init_module(ddata);
2969 pm_runtime_enable(ddata->dev);
2970 error = pm_runtime_get_sync(ddata->dev);
2972 pm_runtime_put_noidle(ddata->dev);
2973 pm_runtime_disable(ddata->dev);
2977 /* Balance use counts as PM runtime should have enabled these all */
2978 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2979 reset_control_assert(ddata->rsts);
2981 if (!(ddata->cfg.quirks &
2982 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
2983 sysc_disable_main_clocks(ddata);
2984 sysc_disable_opt_clocks(ddata);
2985 sysc_clkdm_allow_idle(ddata);
2988 sysc_show_registers(ddata);
2990 ddata->dev->type = &sysc_device_type;
2991 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2992 pdata ? pdata->auxdata : NULL,
2997 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2999 /* At least earlycon won't survive without deferred idle */
3000 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3001 SYSC_QUIRK_NO_IDLE_ON_INIT |
3002 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3003 schedule_delayed_work(&ddata->idle_work, 3000);
3005 pm_runtime_put(&pdev->dev);
3011 pm_runtime_put_sync(&pdev->dev);
3012 pm_runtime_disable(&pdev->dev);
3014 sysc_unprepare(ddata);
3019 static int sysc_remove(struct platform_device *pdev)
3021 struct sysc *ddata = platform_get_drvdata(pdev);
3024 cancel_delayed_work_sync(&ddata->idle_work);
3026 error = pm_runtime_get_sync(ddata->dev);
3028 pm_runtime_put_noidle(ddata->dev);
3029 pm_runtime_disable(ddata->dev);
3033 of_platform_depopulate(&pdev->dev);
3035 pm_runtime_put_sync(&pdev->dev);
3036 pm_runtime_disable(&pdev->dev);
3037 reset_control_assert(ddata->rsts);
3040 sysc_unprepare(ddata);
3045 static const struct of_device_id sysc_match[] = {
3046 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3047 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3048 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3049 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3050 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3051 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3052 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3053 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3054 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3055 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3056 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3057 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3058 { .compatible = "ti,sysc-usb-host-fs",
3059 .data = &sysc_omap4_usb_host_fs, },
3060 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3061 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3064 MODULE_DEVICE_TABLE(of, sysc_match);
3066 static struct platform_driver sysc_driver = {
3067 .probe = sysc_probe,
3068 .remove = sysc_remove,
3071 .of_match_table = sysc_match,
3076 static int __init sysc_init(void)
3078 bus_register_notifier(&platform_bus_type, &sysc_nb);
3080 return platform_driver_register(&sysc_driver);
3082 module_init(sysc_init);
3084 static void __exit sysc_exit(void)
3086 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3087 platform_driver_unregister(&sysc_driver);
3090 module_exit(sysc_exit);
3092 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3093 MODULE_LICENSE("GPL v2");