1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MHI PCI driver - MHI over PCI controller driver
5 * This module is a generic driver for registering MHI-over-PCI devices,
6 * such as PCIe QCOM modems.
8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
11 #include <linux/aer.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/mhi.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/timer.h>
19 #include <linux/workqueue.h>
21 #define MHI_PCI_DEFAULT_BAR_NUM 0
23 #define MHI_POST_RESET_DELAY_MS 500
25 #define HEALTH_CHECK_PERIOD (HZ * 2)
28 * struct mhi_pci_dev_info - MHI PCI device specific information
29 * @config: MHI controller configuration
30 * @name: name of the PCI module
31 * @fw: firmware path (if any)
32 * @edl: emergency download mode firmware path (if any)
33 * @bar_num: PCI base address register to use for MHI MMIO register space
34 * @dma_data_width: DMA transfer word size (32 or 64 bits)
35 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
36 * of inband wake support (such as sdx24)
38 struct mhi_pci_dev_info {
39 const struct mhi_controller_config *config;
44 unsigned int dma_data_width;
48 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
52 .num_elements = el_count, \
53 .event_ring = ev_ring, \
54 .dir = DMA_TO_DEVICE, \
55 .ee_mask = BIT(MHI_EE_AMSS), \
57 .doorbell = MHI_DB_BRST_DISABLE, \
58 .lpm_notify = false, \
59 .offload_channel = false, \
60 .doorbell_mode_switch = false, \
63 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
67 .num_elements = el_count, \
68 .event_ring = ev_ring, \
69 .dir = DMA_FROM_DEVICE, \
70 .ee_mask = BIT(MHI_EE_AMSS), \
72 .doorbell = MHI_DB_BRST_DISABLE, \
73 .lpm_notify = false, \
74 .offload_channel = false, \
75 .doorbell_mode_switch = false, \
78 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
82 .num_elements = el_count, \
83 .event_ring = ev_ring, \
84 .dir = DMA_FROM_DEVICE, \
85 .ee_mask = BIT(MHI_EE_AMSS), \
87 .doorbell = MHI_DB_BRST_DISABLE, \
88 .lpm_notify = false, \
89 .offload_channel = false, \
90 .doorbell_mode_switch = false, \
94 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
96 .num_elements = el_count, \
97 .irq_moderation_ms = 0, \
98 .irq = (ev_ring) + 1, \
100 .mode = MHI_DB_BRST_DISABLE, \
101 .data_type = MHI_ER_CTRL, \
102 .hardware_event = false, \
103 .client_managed = false, \
104 .offload_channel = false, \
107 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \
111 .num_elements = el_count, \
112 .event_ring = ev_ring, \
113 .dir = DMA_TO_DEVICE, \
114 .ee_mask = BIT(MHI_EE_AMSS), \
116 .doorbell = MHI_DB_BRST_ENABLE, \
117 .lpm_notify = false, \
118 .offload_channel = false, \
119 .doorbell_mode_switch = true, \
122 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \
126 .num_elements = el_count, \
127 .event_ring = ev_ring, \
128 .dir = DMA_FROM_DEVICE, \
129 .ee_mask = BIT(MHI_EE_AMSS), \
131 .doorbell = MHI_DB_BRST_ENABLE, \
132 .lpm_notify = false, \
133 .offload_channel = false, \
134 .doorbell_mode_switch = true, \
137 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
141 .num_elements = el_count, \
142 .event_ring = ev_ring, \
143 .dir = DMA_TO_DEVICE, \
144 .ee_mask = BIT(MHI_EE_SBL), \
146 .doorbell = MHI_DB_BRST_DISABLE, \
147 .lpm_notify = false, \
148 .offload_channel = false, \
149 .doorbell_mode_switch = false, \
152 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
156 .num_elements = el_count, \
157 .event_ring = ev_ring, \
158 .dir = DMA_FROM_DEVICE, \
159 .ee_mask = BIT(MHI_EE_SBL), \
161 .doorbell = MHI_DB_BRST_DISABLE, \
162 .lpm_notify = false, \
163 .offload_channel = false, \
164 .doorbell_mode_switch = false, \
167 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \
171 .num_elements = el_count, \
172 .event_ring = ev_ring, \
173 .dir = DMA_TO_DEVICE, \
174 .ee_mask = BIT(MHI_EE_FP), \
176 .doorbell = MHI_DB_BRST_DISABLE, \
177 .lpm_notify = false, \
178 .offload_channel = false, \
179 .doorbell_mode_switch = false, \
182 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \
186 .num_elements = el_count, \
187 .event_ring = ev_ring, \
188 .dir = DMA_FROM_DEVICE, \
189 .ee_mask = BIT(MHI_EE_FP), \
191 .doorbell = MHI_DB_BRST_DISABLE, \
192 .lpm_notify = false, \
193 .offload_channel = false, \
194 .doorbell_mode_switch = false, \
197 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
199 .num_elements = el_count, \
200 .irq_moderation_ms = 5, \
201 .irq = (ev_ring) + 1, \
203 .mode = MHI_DB_BRST_DISABLE, \
204 .data_type = MHI_ER_DATA, \
205 .hardware_event = false, \
206 .client_managed = false, \
207 .offload_channel = false, \
210 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
212 .num_elements = el_count, \
213 .irq_moderation_ms = 1, \
214 .irq = (ev_ring) + 1, \
216 .mode = MHI_DB_BRST_DISABLE, \
217 .data_type = MHI_ER_DATA, \
218 .hardware_event = true, \
219 .client_managed = false, \
220 .offload_channel = false, \
224 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
225 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
226 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
227 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
228 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
229 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
230 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
231 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
232 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
233 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
234 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
235 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
236 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
239 static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
240 /* first ring is control+data ring */
241 MHI_EVENT_CONFIG_CTRL(0, 64),
242 /* DIAG dedicated event ring */
243 MHI_EVENT_CONFIG_DATA(1, 128),
244 /* Hardware channels request dedicated hardware event rings */
245 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
246 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
249 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
252 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
253 .ch_cfg = modem_qcom_v1_mhi_channels,
254 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
255 .event_cfg = modem_qcom_v1_mhi_events,
258 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
259 .name = "qcom-sdx65m",
260 .fw = "qcom/sdx65m/xbl.elf",
261 .edl = "qcom/sdx65m/edl.mbn",
262 .config = &modem_qcom_v1_mhiv_config,
263 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
264 .dma_data_width = 32,
265 .sideband_wake = false,
268 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
269 .name = "qcom-sdx55m",
270 .fw = "qcom/sdx55m/sbl1.mbn",
271 .edl = "qcom/sdx55m/edl.mbn",
272 .config = &modem_qcom_v1_mhiv_config,
273 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
274 .dma_data_width = 32,
275 .sideband_wake = false,
278 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
279 .name = "qcom-sdx24",
280 .edl = "qcom/prog_firehose_sdx24.mbn",
281 .config = &modem_qcom_v1_mhiv_config,
282 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
283 .dma_data_width = 32,
284 .sideband_wake = true,
287 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
288 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
289 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
290 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
291 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
292 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
293 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
294 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
295 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
296 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
297 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
298 /* The EDL firmware is a flash-programmer exposing firehose protocol */
299 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
300 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
301 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
302 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
305 static struct mhi_event_config mhi_quectel_em1xx_events[] = {
306 MHI_EVENT_CONFIG_CTRL(0, 128),
307 MHI_EVENT_CONFIG_DATA(1, 128),
308 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
309 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
312 static const struct mhi_controller_config modem_quectel_em1xx_config = {
315 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
316 .ch_cfg = mhi_quectel_em1xx_channels,
317 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
318 .event_cfg = mhi_quectel_em1xx_events,
321 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
322 .name = "quectel-em1xx",
323 .edl = "qcom/prog_firehose_sdx24.mbn",
324 .config = &modem_quectel_em1xx_config,
325 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
326 .dma_data_width = 32,
327 .sideband_wake = true,
330 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
331 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
332 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
333 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
334 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
335 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
336 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
337 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
338 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
339 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
340 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
343 static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
344 MHI_EVENT_CONFIG_CTRL(0, 128),
345 MHI_EVENT_CONFIG_DATA(1, 128),
346 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
347 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
350 static const struct mhi_controller_config modem_foxconn_sdx55_config = {
353 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
354 .ch_cfg = mhi_foxconn_sdx55_channels,
355 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
356 .event_cfg = mhi_foxconn_sdx55_events,
359 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
360 .name = "foxconn-sdx55",
361 .fw = "qcom/sdx55m/sbl1.mbn",
362 .edl = "qcom/sdx55m/edl.mbn",
363 .config = &modem_foxconn_sdx55_config,
364 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
365 .dma_data_width = 32,
366 .sideband_wake = false,
369 static const struct pci_device_id mhi_pci_id_table[] = {
370 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
371 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
372 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
373 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
374 { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */
375 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
376 { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
377 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
378 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
379 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
380 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
381 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
382 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
383 /* DW5930e (sdx55), With eSIM, It's also T99W175 */
384 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
385 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
386 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
387 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
388 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
391 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
393 enum mhi_pci_device_status {
395 MHI_PCI_DEV_SUSPENDED,
398 struct mhi_pci_device {
399 struct mhi_controller mhi_cntrl;
400 struct pci_saved_state *pci_state;
401 struct work_struct recovery_work;
402 struct timer_list health_check_timer;
403 unsigned long status;
406 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
407 void __iomem *addr, u32 *out)
413 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
414 void __iomem *addr, u32 val)
419 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
420 enum mhi_callback cb)
422 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
424 /* Nothing to do for now */
426 case MHI_CB_FATAL_ERROR:
427 case MHI_CB_SYS_ERROR:
428 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);
429 pm_runtime_forbid(&pdev->dev);
431 case MHI_CB_EE_MISSION_MODE:
432 pm_runtime_allow(&pdev->dev);
439 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force)
444 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override)
449 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl)
454 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl)
456 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
459 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor))
462 if (vendor == (u16) ~0 || vendor == 0)
468 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
469 unsigned int bar_num, u64 dma_mask)
471 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
474 err = pci_assign_resource(pdev, bar_num);
478 err = pcim_enable_device(pdev);
480 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
484 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
486 dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
489 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
491 err = pci_set_dma_mask(pdev, dma_mask);
493 dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
497 err = pci_set_consistent_dma_mask(pdev, dma_mask);
499 dev_err(&pdev->dev, "set consistent dma mask failed\n");
503 pci_set_master(pdev);
508 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
509 const struct mhi_controller_config *mhi_cntrl_config)
511 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
516 * Alloc one MSI vector for BHI + one vector per event ring, ideally...
517 * No explicit pci_free_irq_vectors required, done by pcim_release.
519 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
521 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
522 if (nr_vectors < 0) {
523 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
528 if (nr_vectors < mhi_cntrl->nr_irqs) {
529 dev_warn(&pdev->dev, "using shared MSI\n");
531 /* Patch msi vectors, use only one (shared) */
532 for (i = 0; i < mhi_cntrl_config->num_events; i++)
533 mhi_cntrl_config->event_cfg[i].irq = 0;
534 mhi_cntrl->nr_irqs = 1;
537 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
541 for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
542 int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
544 irq[i] = pci_irq_vector(pdev, vector);
547 mhi_cntrl->irq = irq;
552 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
554 /* The runtime_get() MHI callback means:
555 * Do whatever is requested to leave M3.
557 return pm_runtime_get(mhi_cntrl->cntrl_dev);
560 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
562 /* The runtime_put() MHI callback means:
563 * Device can be moved in M3 state.
565 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);
566 pm_runtime_put(mhi_cntrl->cntrl_dev);
569 static void mhi_pci_recovery_work(struct work_struct *work)
571 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device,
573 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
574 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
577 dev_warn(&pdev->dev, "device recovery started\n");
579 del_timer(&mhi_pdev->health_check_timer);
580 pm_runtime_forbid(&pdev->dev);
582 /* Clean up MHI state */
583 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
584 mhi_power_down(mhi_cntrl, false);
585 mhi_unprepare_after_power_down(mhi_cntrl);
588 pci_set_power_state(pdev, PCI_D0);
589 pci_load_saved_state(pdev, mhi_pdev->pci_state);
590 pci_restore_state(pdev);
592 if (!mhi_pci_is_alive(mhi_cntrl))
595 err = mhi_prepare_for_power_up(mhi_cntrl);
599 err = mhi_sync_power_up(mhi_cntrl);
603 dev_dbg(&pdev->dev, "Recovery completed\n");
605 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
606 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
610 mhi_unprepare_after_power_down(mhi_cntrl);
612 if (pci_reset_function(pdev))
613 dev_err(&pdev->dev, "Recovery failed\n");
616 static void health_check(struct timer_list *t)
618 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer);
619 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
621 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
622 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
625 if (!mhi_pci_is_alive(mhi_cntrl)) {
626 dev_err(mhi_cntrl->cntrl_dev, "Device died\n");
627 queue_work(system_long_wq, &mhi_pdev->recovery_work);
631 /* reschedule in two seconds */
632 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
635 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
637 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
638 const struct mhi_controller_config *mhi_cntrl_config;
639 struct mhi_pci_device *mhi_pdev;
640 struct mhi_controller *mhi_cntrl;
643 dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name);
645 /* mhi_pdev.mhi_cntrl must be zero-initialized */
646 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);
650 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);
651 timer_setup(&mhi_pdev->health_check_timer, health_check, 0);
653 mhi_cntrl_config = info->config;
654 mhi_cntrl = &mhi_pdev->mhi_cntrl;
656 mhi_cntrl->cntrl_dev = &pdev->dev;
657 mhi_cntrl->iova_start = 0;
658 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);
659 mhi_cntrl->fw_image = info->fw;
660 mhi_cntrl->edl_image = info->edl;
662 mhi_cntrl->read_reg = mhi_pci_read_reg;
663 mhi_cntrl->write_reg = mhi_pci_write_reg;
664 mhi_cntrl->status_cb = mhi_pci_status_cb;
665 mhi_cntrl->runtime_get = mhi_pci_runtime_get;
666 mhi_cntrl->runtime_put = mhi_pci_runtime_put;
668 if (info->sideband_wake) {
669 mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
670 mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
671 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
674 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
678 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
682 pci_set_drvdata(pdev, mhi_pdev);
684 /* Have stored pci confspace at hand for restore in sudden PCI error.
685 * cache the state locally and discard the PCI core one.
687 pci_save_state(pdev);
688 mhi_pdev->pci_state = pci_store_saved_state(pdev);
689 pci_load_saved_state(pdev, NULL);
691 pci_enable_pcie_error_reporting(pdev);
693 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
695 goto err_disable_reporting;
697 /* MHI bus does not power up the controller by default */
698 err = mhi_prepare_for_power_up(mhi_cntrl);
700 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
704 err = mhi_sync_power_up(mhi_cntrl);
706 dev_err(&pdev->dev, "failed to power up MHI controller\n");
710 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
712 /* start health check */
713 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
715 /* Only allow runtime-suspend if PME capable (for wakeup) */
716 if (pci_pme_capable(pdev, PCI_D3hot)) {
717 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
718 pm_runtime_use_autosuspend(&pdev->dev);
719 pm_runtime_mark_last_busy(&pdev->dev);
720 pm_runtime_put_noidle(&pdev->dev);
726 mhi_unprepare_after_power_down(mhi_cntrl);
728 mhi_unregister_controller(mhi_cntrl);
729 err_disable_reporting:
730 pci_disable_pcie_error_reporting(pdev);
735 static void mhi_pci_remove(struct pci_dev *pdev)
737 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
738 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
740 del_timer_sync(&mhi_pdev->health_check_timer);
741 cancel_work_sync(&mhi_pdev->recovery_work);
743 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
744 mhi_power_down(mhi_cntrl, true);
745 mhi_unprepare_after_power_down(mhi_cntrl);
748 /* balancing probe put_noidle */
749 if (pci_pme_capable(pdev, PCI_D3hot))
750 pm_runtime_get_noresume(&pdev->dev);
752 mhi_unregister_controller(mhi_cntrl);
753 pci_disable_pcie_error_reporting(pdev);
756 static void mhi_pci_shutdown(struct pci_dev *pdev)
758 mhi_pci_remove(pdev);
759 pci_set_power_state(pdev, PCI_D3hot);
762 static void mhi_pci_reset_prepare(struct pci_dev *pdev)
764 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
765 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
767 dev_info(&pdev->dev, "reset\n");
769 del_timer(&mhi_pdev->health_check_timer);
771 /* Clean up MHI state */
772 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
773 mhi_power_down(mhi_cntrl, false);
774 mhi_unprepare_after_power_down(mhi_cntrl);
777 /* cause internal device reset */
778 mhi_soc_reset(mhi_cntrl);
780 /* Be sure device reset has been executed */
781 msleep(MHI_POST_RESET_DELAY_MS);
784 static void mhi_pci_reset_done(struct pci_dev *pdev)
786 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
787 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
790 /* Restore initial known working PCI state */
791 pci_load_saved_state(pdev, mhi_pdev->pci_state);
792 pci_restore_state(pdev);
794 /* Is device status available ? */
795 if (!mhi_pci_is_alive(mhi_cntrl)) {
796 dev_err(&pdev->dev, "reset failed\n");
800 err = mhi_prepare_for_power_up(mhi_cntrl);
802 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
806 err = mhi_sync_power_up(mhi_cntrl);
808 dev_err(&pdev->dev, "failed to power up MHI controller\n");
809 mhi_unprepare_after_power_down(mhi_cntrl);
813 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
814 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
817 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev,
818 pci_channel_state_t state)
820 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
821 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
823 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);
825 if (state == pci_channel_io_perm_failure)
826 return PCI_ERS_RESULT_DISCONNECT;
828 /* Clean up MHI state */
829 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
830 mhi_power_down(mhi_cntrl, false);
831 mhi_unprepare_after_power_down(mhi_cntrl);
834 return PCI_ERS_RESULT_RECOVERED;
837 pci_disable_device(pdev);
839 return PCI_ERS_RESULT_NEED_RESET;
842 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev)
844 if (pci_enable_device(pdev)) {
845 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
846 return PCI_ERS_RESULT_DISCONNECT;
849 return PCI_ERS_RESULT_RECOVERED;
852 static void mhi_pci_io_resume(struct pci_dev *pdev)
854 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
856 dev_err(&pdev->dev, "PCI slot reset done\n");
858 queue_work(system_long_wq, &mhi_pdev->recovery_work);
861 static const struct pci_error_handlers mhi_pci_err_handler = {
862 .error_detected = mhi_pci_error_detected,
863 .slot_reset = mhi_pci_slot_reset,
864 .resume = mhi_pci_io_resume,
865 .reset_prepare = mhi_pci_reset_prepare,
866 .reset_done = mhi_pci_reset_done,
869 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev)
871 struct pci_dev *pdev = to_pci_dev(dev);
872 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
873 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
876 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
879 del_timer(&mhi_pdev->health_check_timer);
880 cancel_work_sync(&mhi_pdev->recovery_work);
882 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
883 mhi_cntrl->ee != MHI_EE_AMSS)
884 goto pci_suspend; /* Nothing to do at MHI level */
886 /* Transition to M3 state */
887 err = mhi_pm_suspend(mhi_cntrl);
889 dev_err(&pdev->dev, "failed to suspend device: %d\n", err);
890 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);
895 pci_disable_device(pdev);
896 pci_wake_from_d3(pdev, true);
901 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev)
903 struct pci_dev *pdev = to_pci_dev(dev);
904 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
905 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
908 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
911 err = pci_enable_device(pdev);
915 pci_set_master(pdev);
916 pci_wake_from_d3(pdev, false);
918 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
919 mhi_cntrl->ee != MHI_EE_AMSS)
920 return 0; /* Nothing to do at MHI level */
922 /* Exit M3, transition to M0 state */
923 err = mhi_pm_resume(mhi_cntrl);
925 dev_err(&pdev->dev, "failed to resume device: %d\n", err);
929 /* Resume health check */
930 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
932 /* It can be a remote wakeup (no mhi runtime_get), update access time */
933 pm_runtime_mark_last_busy(dev);
938 /* Do not fail to not mess up our PCI device state, the device likely
939 * lost power (d3cold) and we simply need to reset it from the recovery
940 * procedure, trigger the recovery asynchronously to prevent system
941 * suspend exit delaying.
943 queue_work(system_long_wq, &mhi_pdev->recovery_work);
944 pm_runtime_mark_last_busy(dev);
949 static int __maybe_unused mhi_pci_suspend(struct device *dev)
951 pm_runtime_disable(dev);
952 return mhi_pci_runtime_suspend(dev);
955 static int __maybe_unused mhi_pci_resume(struct device *dev)
959 /* Depending the platform, device may have lost power (d3cold), we need
960 * to resume it now to check its state and recover when necessary.
962 ret = mhi_pci_runtime_resume(dev);
963 pm_runtime_enable(dev);
968 static int __maybe_unused mhi_pci_freeze(struct device *dev)
970 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
971 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
973 /* We want to stop all operations, hibernation does not guarantee that
974 * device will be in the same state as before freezing, especially if
975 * the intermediate restore kernel reinitializes MHI device with new
978 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
979 mhi_power_down(mhi_cntrl, false);
980 mhi_unprepare_after_power_down(mhi_cntrl);
986 static int __maybe_unused mhi_pci_restore(struct device *dev)
988 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
990 /* Reinitialize the device */
991 queue_work(system_long_wq, &mhi_pdev->recovery_work);
996 static const struct dev_pm_ops mhi_pci_pm_ops = {
997 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
998 #ifdef CONFIG_PM_SLEEP
999 .suspend = mhi_pci_suspend,
1000 .resume = mhi_pci_resume,
1001 .freeze = mhi_pci_freeze,
1002 .thaw = mhi_pci_restore,
1003 .restore = mhi_pci_restore,
1007 static struct pci_driver mhi_pci_driver = {
1008 .name = "mhi-pci-generic",
1009 .id_table = mhi_pci_id_table,
1010 .probe = mhi_pci_probe,
1011 .remove = mhi_pci_remove,
1012 .shutdown = mhi_pci_shutdown,
1013 .err_handler = &mhi_pci_err_handler,
1014 .driver.pm = &mhi_pci_pm_ops
1016 module_pci_driver(mhi_pci_driver);
1018 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
1019 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
1020 MODULE_LICENSE("GPL");