1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MHI PCI driver - MHI over PCI controller driver
5 * This module is a generic driver for registering MHI-over-PCI devices,
6 * such as PCIe QCOM modems.
8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
11 #include <linux/aer.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/mhi.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/timer.h>
19 #include <linux/workqueue.h>
21 #define MHI_PCI_DEFAULT_BAR_NUM 0
23 #define MHI_POST_RESET_DELAY_MS 500
25 #define HEALTH_CHECK_PERIOD (HZ * 2)
28 * struct mhi_pci_dev_info - MHI PCI device specific information
29 * @config: MHI controller configuration
30 * @name: name of the PCI module
31 * @fw: firmware path (if any)
32 * @edl: emergency download mode firmware path (if any)
33 * @bar_num: PCI base address register to use for MHI MMIO register space
34 * @dma_data_width: DMA transfer word size (32 or 64 bits)
35 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
36 * of inband wake support (such as sdx24)
38 struct mhi_pci_dev_info {
39 const struct mhi_controller_config *config;
44 unsigned int dma_data_width;
48 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
52 .num_elements = el_count, \
53 .event_ring = ev_ring, \
54 .dir = DMA_TO_DEVICE, \
55 .ee_mask = BIT(MHI_EE_AMSS), \
57 .doorbell = MHI_DB_BRST_DISABLE, \
58 .lpm_notify = false, \
59 .offload_channel = false, \
60 .doorbell_mode_switch = false, \
63 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
67 .num_elements = el_count, \
68 .event_ring = ev_ring, \
69 .dir = DMA_FROM_DEVICE, \
70 .ee_mask = BIT(MHI_EE_AMSS), \
72 .doorbell = MHI_DB_BRST_DISABLE, \
73 .lpm_notify = false, \
74 .offload_channel = false, \
75 .doorbell_mode_switch = false, \
78 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
82 .num_elements = el_count, \
83 .event_ring = ev_ring, \
84 .dir = DMA_FROM_DEVICE, \
85 .ee_mask = BIT(MHI_EE_AMSS), \
87 .doorbell = MHI_DB_BRST_DISABLE, \
88 .lpm_notify = false, \
89 .offload_channel = false, \
90 .doorbell_mode_switch = false, \
94 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
96 .num_elements = el_count, \
97 .irq_moderation_ms = 0, \
98 .irq = (ev_ring) + 1, \
100 .mode = MHI_DB_BRST_DISABLE, \
101 .data_type = MHI_ER_CTRL, \
102 .hardware_event = false, \
103 .client_managed = false, \
104 .offload_channel = false, \
107 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \
111 .num_elements = el_count, \
112 .event_ring = ev_ring, \
113 .dir = DMA_TO_DEVICE, \
114 .ee_mask = BIT(MHI_EE_AMSS), \
116 .doorbell = MHI_DB_BRST_ENABLE, \
117 .lpm_notify = false, \
118 .offload_channel = false, \
119 .doorbell_mode_switch = true, \
122 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \
126 .num_elements = el_count, \
127 .event_ring = ev_ring, \
128 .dir = DMA_FROM_DEVICE, \
129 .ee_mask = BIT(MHI_EE_AMSS), \
131 .doorbell = MHI_DB_BRST_ENABLE, \
132 .lpm_notify = false, \
133 .offload_channel = false, \
134 .doorbell_mode_switch = true, \
137 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
141 .num_elements = el_count, \
142 .event_ring = ev_ring, \
143 .dir = DMA_TO_DEVICE, \
144 .ee_mask = BIT(MHI_EE_SBL), \
146 .doorbell = MHI_DB_BRST_DISABLE, \
147 .lpm_notify = false, \
148 .offload_channel = false, \
149 .doorbell_mode_switch = false, \
152 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
156 .num_elements = el_count, \
157 .event_ring = ev_ring, \
158 .dir = DMA_FROM_DEVICE, \
159 .ee_mask = BIT(MHI_EE_SBL), \
161 .doorbell = MHI_DB_BRST_DISABLE, \
162 .lpm_notify = false, \
163 .offload_channel = false, \
164 .doorbell_mode_switch = false, \
167 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \
171 .num_elements = el_count, \
172 .event_ring = ev_ring, \
173 .dir = DMA_TO_DEVICE, \
174 .ee_mask = BIT(MHI_EE_FP), \
176 .doorbell = MHI_DB_BRST_DISABLE, \
177 .lpm_notify = false, \
178 .offload_channel = false, \
179 .doorbell_mode_switch = false, \
182 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \
186 .num_elements = el_count, \
187 .event_ring = ev_ring, \
188 .dir = DMA_FROM_DEVICE, \
189 .ee_mask = BIT(MHI_EE_FP), \
191 .doorbell = MHI_DB_BRST_DISABLE, \
192 .lpm_notify = false, \
193 .offload_channel = false, \
194 .doorbell_mode_switch = false, \
197 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
199 .num_elements = el_count, \
200 .irq_moderation_ms = 5, \
201 .irq = (ev_ring) + 1, \
203 .mode = MHI_DB_BRST_DISABLE, \
204 .data_type = MHI_ER_DATA, \
205 .hardware_event = false, \
206 .client_managed = false, \
207 .offload_channel = false, \
210 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
212 .num_elements = el_count, \
213 .irq_moderation_ms = 1, \
214 .irq = (ev_ring) + 1, \
216 .mode = MHI_DB_BRST_DISABLE, \
217 .data_type = MHI_ER_DATA, \
218 .hardware_event = true, \
219 .client_managed = false, \
220 .offload_channel = false, \
224 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
225 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
226 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
227 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
228 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
229 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
230 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
231 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
232 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
233 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
234 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
235 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
236 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
239 static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
240 /* first ring is control+data ring */
241 MHI_EVENT_CONFIG_CTRL(0, 64),
242 /* DIAG dedicated event ring */
243 MHI_EVENT_CONFIG_DATA(1, 128),
244 /* Hardware channels request dedicated hardware event rings */
245 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
246 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
249 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
252 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
253 .ch_cfg = modem_qcom_v1_mhi_channels,
254 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
255 .event_cfg = modem_qcom_v1_mhi_events,
258 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
259 .name = "qcom-sdx65m",
260 .fw = "qcom/sdx65m/xbl.elf",
261 .edl = "qcom/sdx65m/edl.mbn",
262 .config = &modem_qcom_v1_mhiv_config,
263 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
264 .dma_data_width = 32,
265 .sideband_wake = false,
268 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
269 .name = "qcom-sdx55m",
270 .fw = "qcom/sdx55m/sbl1.mbn",
271 .edl = "qcom/sdx55m/edl.mbn",
272 .config = &modem_qcom_v1_mhiv_config,
273 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
274 .dma_data_width = 32,
275 .sideband_wake = false,
278 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
279 .name = "qcom-sdx24",
280 .edl = "qcom/prog_firehose_sdx24.mbn",
281 .config = &modem_qcom_v1_mhiv_config,
282 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
283 .dma_data_width = 32,
284 .sideband_wake = true,
287 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
288 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
289 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
290 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
291 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
292 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
293 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
294 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
295 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
296 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
297 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
298 /* The EDL firmware is a flash-programmer exposing firehose protocol */
299 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
300 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
301 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
302 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
305 static struct mhi_event_config mhi_quectel_em1xx_events[] = {
306 MHI_EVENT_CONFIG_CTRL(0, 128),
307 MHI_EVENT_CONFIG_DATA(1, 128),
308 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
309 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
312 static const struct mhi_controller_config modem_quectel_em1xx_config = {
315 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
316 .ch_cfg = mhi_quectel_em1xx_channels,
317 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
318 .event_cfg = mhi_quectel_em1xx_events,
321 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
322 .name = "quectel-em1xx",
323 .edl = "qcom/prog_firehose_sdx24.mbn",
324 .config = &modem_quectel_em1xx_config,
325 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
326 .dma_data_width = 32,
327 .sideband_wake = true,
330 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
331 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
332 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
333 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
334 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
335 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
336 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
337 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
338 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
339 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
340 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
343 static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
344 MHI_EVENT_CONFIG_CTRL(0, 128),
345 MHI_EVENT_CONFIG_DATA(1, 128),
346 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
347 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
350 static const struct mhi_controller_config modem_foxconn_sdx55_config = {
353 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
354 .ch_cfg = mhi_foxconn_sdx55_channels,
355 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
356 .event_cfg = mhi_foxconn_sdx55_events,
359 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
360 .name = "foxconn-sdx55",
361 .fw = "qcom/sdx55m/sbl1.mbn",
362 .edl = "qcom/sdx55m/edl.mbn",
363 .config = &modem_foxconn_sdx55_config,
364 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
365 .dma_data_width = 32,
366 .sideband_wake = false,
369 static const struct mhi_channel_config mhi_mv31_channels[] = {
370 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0),
371 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0),
372 /* MBIM Control Channel */
373 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0),
374 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0),
375 /* MBIM Data Channel */
376 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2),
377 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3),
380 static struct mhi_event_config mhi_mv31_events[] = {
381 MHI_EVENT_CONFIG_CTRL(0, 256),
382 MHI_EVENT_CONFIG_DATA(1, 256),
383 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
384 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101),
387 static const struct mhi_controller_config modem_mv31_config = {
390 .num_channels = ARRAY_SIZE(mhi_mv31_channels),
391 .ch_cfg = mhi_mv31_channels,
392 .num_events = ARRAY_SIZE(mhi_mv31_events),
393 .event_cfg = mhi_mv31_events,
396 static const struct mhi_pci_dev_info mhi_mv31_info = {
397 .name = "cinterion-mv31",
398 .config = &modem_mv31_config,
399 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
400 .dma_data_width = 32,
403 static const struct pci_device_id mhi_pci_id_table[] = {
404 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
405 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
406 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
407 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
408 { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */
409 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
410 { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
411 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
412 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
413 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
414 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
415 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
416 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
417 /* DW5930e (sdx55), With eSIM, It's also T99W175 */
418 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
419 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
420 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
421 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
422 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
423 /* MV31-W (Cinterion) */
424 { PCI_DEVICE(0x1269, 0x00b3),
425 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
428 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
430 enum mhi_pci_device_status {
432 MHI_PCI_DEV_SUSPENDED,
435 struct mhi_pci_device {
436 struct mhi_controller mhi_cntrl;
437 struct pci_saved_state *pci_state;
438 struct work_struct recovery_work;
439 struct timer_list health_check_timer;
440 unsigned long status;
443 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
444 void __iomem *addr, u32 *out)
450 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
451 void __iomem *addr, u32 val)
456 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
457 enum mhi_callback cb)
459 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
461 /* Nothing to do for now */
463 case MHI_CB_FATAL_ERROR:
464 case MHI_CB_SYS_ERROR:
465 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);
466 pm_runtime_forbid(&pdev->dev);
468 case MHI_CB_EE_MISSION_MODE:
469 pm_runtime_allow(&pdev->dev);
476 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force)
481 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override)
486 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl)
491 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl)
493 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
496 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor))
499 if (vendor == (u16) ~0 || vendor == 0)
505 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
506 unsigned int bar_num, u64 dma_mask)
508 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
511 err = pci_assign_resource(pdev, bar_num);
515 err = pcim_enable_device(pdev);
517 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
521 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
523 dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
526 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
527 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
529 err = pci_set_dma_mask(pdev, dma_mask);
531 dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
535 err = pci_set_consistent_dma_mask(pdev, dma_mask);
537 dev_err(&pdev->dev, "set consistent dma mask failed\n");
541 pci_set_master(pdev);
546 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
547 const struct mhi_controller_config *mhi_cntrl_config)
549 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
554 * Alloc one MSI vector for BHI + one vector per event ring, ideally...
555 * No explicit pci_free_irq_vectors required, done by pcim_release.
557 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
559 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
560 if (nr_vectors < 0) {
561 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
566 if (nr_vectors < mhi_cntrl->nr_irqs) {
567 dev_warn(&pdev->dev, "using shared MSI\n");
569 /* Patch msi vectors, use only one (shared) */
570 for (i = 0; i < mhi_cntrl_config->num_events; i++)
571 mhi_cntrl_config->event_cfg[i].irq = 0;
572 mhi_cntrl->nr_irqs = 1;
575 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
579 for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
580 int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
582 irq[i] = pci_irq_vector(pdev, vector);
585 mhi_cntrl->irq = irq;
590 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
592 /* The runtime_get() MHI callback means:
593 * Do whatever is requested to leave M3.
595 return pm_runtime_get(mhi_cntrl->cntrl_dev);
598 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
600 /* The runtime_put() MHI callback means:
601 * Device can be moved in M3 state.
603 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);
604 pm_runtime_put(mhi_cntrl->cntrl_dev);
607 static void mhi_pci_recovery_work(struct work_struct *work)
609 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device,
611 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
612 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
615 dev_warn(&pdev->dev, "device recovery started\n");
617 del_timer(&mhi_pdev->health_check_timer);
618 pm_runtime_forbid(&pdev->dev);
620 /* Clean up MHI state */
621 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
622 mhi_power_down(mhi_cntrl, false);
623 mhi_unprepare_after_power_down(mhi_cntrl);
626 pci_set_power_state(pdev, PCI_D0);
627 pci_load_saved_state(pdev, mhi_pdev->pci_state);
628 pci_restore_state(pdev);
630 if (!mhi_pci_is_alive(mhi_cntrl))
633 err = mhi_prepare_for_power_up(mhi_cntrl);
637 err = mhi_sync_power_up(mhi_cntrl);
641 dev_dbg(&pdev->dev, "Recovery completed\n");
643 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
644 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
648 mhi_unprepare_after_power_down(mhi_cntrl);
650 if (pci_reset_function(pdev))
651 dev_err(&pdev->dev, "Recovery failed\n");
654 static void health_check(struct timer_list *t)
656 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer);
657 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
659 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
660 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
663 if (!mhi_pci_is_alive(mhi_cntrl)) {
664 dev_err(mhi_cntrl->cntrl_dev, "Device died\n");
665 queue_work(system_long_wq, &mhi_pdev->recovery_work);
669 /* reschedule in two seconds */
670 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
673 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
675 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
676 const struct mhi_controller_config *mhi_cntrl_config;
677 struct mhi_pci_device *mhi_pdev;
678 struct mhi_controller *mhi_cntrl;
681 dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name);
683 /* mhi_pdev.mhi_cntrl must be zero-initialized */
684 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);
688 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);
689 timer_setup(&mhi_pdev->health_check_timer, health_check, 0);
691 mhi_cntrl_config = info->config;
692 mhi_cntrl = &mhi_pdev->mhi_cntrl;
694 mhi_cntrl->cntrl_dev = &pdev->dev;
695 mhi_cntrl->iova_start = 0;
696 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);
697 mhi_cntrl->fw_image = info->fw;
698 mhi_cntrl->edl_image = info->edl;
700 mhi_cntrl->read_reg = mhi_pci_read_reg;
701 mhi_cntrl->write_reg = mhi_pci_write_reg;
702 mhi_cntrl->status_cb = mhi_pci_status_cb;
703 mhi_cntrl->runtime_get = mhi_pci_runtime_get;
704 mhi_cntrl->runtime_put = mhi_pci_runtime_put;
706 if (info->sideband_wake) {
707 mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
708 mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
709 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
712 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
716 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
720 pci_set_drvdata(pdev, mhi_pdev);
722 /* Have stored pci confspace at hand for restore in sudden PCI error.
723 * cache the state locally and discard the PCI core one.
725 pci_save_state(pdev);
726 mhi_pdev->pci_state = pci_store_saved_state(pdev);
727 pci_load_saved_state(pdev, NULL);
729 pci_enable_pcie_error_reporting(pdev);
731 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
733 goto err_disable_reporting;
735 /* MHI bus does not power up the controller by default */
736 err = mhi_prepare_for_power_up(mhi_cntrl);
738 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
742 err = mhi_sync_power_up(mhi_cntrl);
744 dev_err(&pdev->dev, "failed to power up MHI controller\n");
748 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
750 /* start health check */
751 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
753 /* Only allow runtime-suspend if PME capable (for wakeup) */
754 if (pci_pme_capable(pdev, PCI_D3hot)) {
755 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
756 pm_runtime_use_autosuspend(&pdev->dev);
757 pm_runtime_mark_last_busy(&pdev->dev);
758 pm_runtime_put_noidle(&pdev->dev);
764 mhi_unprepare_after_power_down(mhi_cntrl);
766 mhi_unregister_controller(mhi_cntrl);
767 err_disable_reporting:
768 pci_disable_pcie_error_reporting(pdev);
773 static void mhi_pci_remove(struct pci_dev *pdev)
775 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
776 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
778 del_timer_sync(&mhi_pdev->health_check_timer);
779 cancel_work_sync(&mhi_pdev->recovery_work);
781 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
782 mhi_power_down(mhi_cntrl, true);
783 mhi_unprepare_after_power_down(mhi_cntrl);
786 /* balancing probe put_noidle */
787 if (pci_pme_capable(pdev, PCI_D3hot))
788 pm_runtime_get_noresume(&pdev->dev);
790 mhi_unregister_controller(mhi_cntrl);
791 pci_disable_pcie_error_reporting(pdev);
794 static void mhi_pci_shutdown(struct pci_dev *pdev)
796 mhi_pci_remove(pdev);
797 pci_set_power_state(pdev, PCI_D3hot);
800 static void mhi_pci_reset_prepare(struct pci_dev *pdev)
802 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
803 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
805 dev_info(&pdev->dev, "reset\n");
807 del_timer(&mhi_pdev->health_check_timer);
809 /* Clean up MHI state */
810 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
811 mhi_power_down(mhi_cntrl, false);
812 mhi_unprepare_after_power_down(mhi_cntrl);
815 /* cause internal device reset */
816 mhi_soc_reset(mhi_cntrl);
818 /* Be sure device reset has been executed */
819 msleep(MHI_POST_RESET_DELAY_MS);
822 static void mhi_pci_reset_done(struct pci_dev *pdev)
824 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
825 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
828 /* Restore initial known working PCI state */
829 pci_load_saved_state(pdev, mhi_pdev->pci_state);
830 pci_restore_state(pdev);
832 /* Is device status available ? */
833 if (!mhi_pci_is_alive(mhi_cntrl)) {
834 dev_err(&pdev->dev, "reset failed\n");
838 err = mhi_prepare_for_power_up(mhi_cntrl);
840 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
844 err = mhi_sync_power_up(mhi_cntrl);
846 dev_err(&pdev->dev, "failed to power up MHI controller\n");
847 mhi_unprepare_after_power_down(mhi_cntrl);
851 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
852 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
855 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev,
856 pci_channel_state_t state)
858 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
859 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
861 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);
863 if (state == pci_channel_io_perm_failure)
864 return PCI_ERS_RESULT_DISCONNECT;
866 /* Clean up MHI state */
867 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
868 mhi_power_down(mhi_cntrl, false);
869 mhi_unprepare_after_power_down(mhi_cntrl);
872 return PCI_ERS_RESULT_RECOVERED;
875 pci_disable_device(pdev);
877 return PCI_ERS_RESULT_NEED_RESET;
880 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev)
882 if (pci_enable_device(pdev)) {
883 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
884 return PCI_ERS_RESULT_DISCONNECT;
887 return PCI_ERS_RESULT_RECOVERED;
890 static void mhi_pci_io_resume(struct pci_dev *pdev)
892 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
894 dev_err(&pdev->dev, "PCI slot reset done\n");
896 queue_work(system_long_wq, &mhi_pdev->recovery_work);
899 static const struct pci_error_handlers mhi_pci_err_handler = {
900 .error_detected = mhi_pci_error_detected,
901 .slot_reset = mhi_pci_slot_reset,
902 .resume = mhi_pci_io_resume,
903 .reset_prepare = mhi_pci_reset_prepare,
904 .reset_done = mhi_pci_reset_done,
907 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev)
909 struct pci_dev *pdev = to_pci_dev(dev);
910 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
911 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
914 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
917 del_timer(&mhi_pdev->health_check_timer);
918 cancel_work_sync(&mhi_pdev->recovery_work);
920 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
921 mhi_cntrl->ee != MHI_EE_AMSS)
922 goto pci_suspend; /* Nothing to do at MHI level */
924 /* Transition to M3 state */
925 err = mhi_pm_suspend(mhi_cntrl);
927 dev_err(&pdev->dev, "failed to suspend device: %d\n", err);
928 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);
933 pci_disable_device(pdev);
934 pci_wake_from_d3(pdev, true);
939 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev)
941 struct pci_dev *pdev = to_pci_dev(dev);
942 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
943 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
946 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
949 err = pci_enable_device(pdev);
953 pci_set_master(pdev);
954 pci_wake_from_d3(pdev, false);
956 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
957 mhi_cntrl->ee != MHI_EE_AMSS)
958 return 0; /* Nothing to do at MHI level */
960 /* Exit M3, transition to M0 state */
961 err = mhi_pm_resume(mhi_cntrl);
963 dev_err(&pdev->dev, "failed to resume device: %d\n", err);
967 /* Resume health check */
968 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
970 /* It can be a remote wakeup (no mhi runtime_get), update access time */
971 pm_runtime_mark_last_busy(dev);
976 /* Do not fail to not mess up our PCI device state, the device likely
977 * lost power (d3cold) and we simply need to reset it from the recovery
978 * procedure, trigger the recovery asynchronously to prevent system
979 * suspend exit delaying.
981 queue_work(system_long_wq, &mhi_pdev->recovery_work);
982 pm_runtime_mark_last_busy(dev);
987 static int __maybe_unused mhi_pci_suspend(struct device *dev)
989 pm_runtime_disable(dev);
990 return mhi_pci_runtime_suspend(dev);
993 static int __maybe_unused mhi_pci_resume(struct device *dev)
997 /* Depending the platform, device may have lost power (d3cold), we need
998 * to resume it now to check its state and recover when necessary.
1000 ret = mhi_pci_runtime_resume(dev);
1001 pm_runtime_enable(dev);
1006 static int __maybe_unused mhi_pci_freeze(struct device *dev)
1008 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1009 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1011 /* We want to stop all operations, hibernation does not guarantee that
1012 * device will be in the same state as before freezing, especially if
1013 * the intermediate restore kernel reinitializes MHI device with new
1016 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1017 mhi_power_down(mhi_cntrl, false);
1018 mhi_unprepare_after_power_down(mhi_cntrl);
1024 static int __maybe_unused mhi_pci_restore(struct device *dev)
1026 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1028 /* Reinitialize the device */
1029 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1034 static const struct dev_pm_ops mhi_pci_pm_ops = {
1035 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
1036 #ifdef CONFIG_PM_SLEEP
1037 .suspend = mhi_pci_suspend,
1038 .resume = mhi_pci_resume,
1039 .freeze = mhi_pci_freeze,
1040 .thaw = mhi_pci_restore,
1041 .restore = mhi_pci_restore,
1045 static struct pci_driver mhi_pci_driver = {
1046 .name = "mhi-pci-generic",
1047 .id_table = mhi_pci_id_table,
1048 .probe = mhi_pci_probe,
1049 .remove = mhi_pci_remove,
1050 .shutdown = mhi_pci_shutdown,
1051 .err_handler = &mhi_pci_err_handler,
1052 .driver.pm = &mhi_pci_pm_ops
1054 module_pci_driver(mhi_pci_driver);
1056 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
1057 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
1058 MODULE_LICENSE("GPL");