1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MHI PCI driver - MHI over PCI controller driver
5 * This module is a generic driver for registering MHI-over-PCI devices,
6 * such as PCIe QCOM modems.
8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
11 #include <linux/aer.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/mhi.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/timer.h>
19 #include <linux/workqueue.h>
21 #define MHI_PCI_DEFAULT_BAR_NUM 0
23 #define MHI_POST_RESET_DELAY_MS 2000
25 #define HEALTH_CHECK_PERIOD (HZ * 2)
28 * struct mhi_pci_dev_info - MHI PCI device specific information
29 * @config: MHI controller configuration
30 * @name: name of the PCI module
31 * @fw: firmware path (if any)
32 * @edl: emergency download mode firmware path (if any)
33 * @bar_num: PCI base address register to use for MHI MMIO register space
34 * @dma_data_width: DMA transfer word size (32 or 64 bits)
35 * @mru_default: default MRU size for MBIM network packets
36 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
37 * of inband wake support (such as sdx24)
39 struct mhi_pci_dev_info {
40 const struct mhi_controller_config *config;
45 unsigned int dma_data_width;
46 unsigned int mru_default;
50 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
54 .num_elements = el_count, \
55 .event_ring = ev_ring, \
56 .dir = DMA_TO_DEVICE, \
57 .ee_mask = BIT(MHI_EE_AMSS), \
59 .doorbell = MHI_DB_BRST_DISABLE, \
60 .lpm_notify = false, \
61 .offload_channel = false, \
62 .doorbell_mode_switch = false, \
65 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
69 .num_elements = el_count, \
70 .event_ring = ev_ring, \
71 .dir = DMA_FROM_DEVICE, \
72 .ee_mask = BIT(MHI_EE_AMSS), \
74 .doorbell = MHI_DB_BRST_DISABLE, \
75 .lpm_notify = false, \
76 .offload_channel = false, \
77 .doorbell_mode_switch = false, \
80 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
84 .num_elements = el_count, \
85 .event_ring = ev_ring, \
86 .dir = DMA_FROM_DEVICE, \
87 .ee_mask = BIT(MHI_EE_AMSS), \
89 .doorbell = MHI_DB_BRST_DISABLE, \
90 .lpm_notify = false, \
91 .offload_channel = false, \
92 .doorbell_mode_switch = false, \
96 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
98 .num_elements = el_count, \
99 .irq_moderation_ms = 0, \
100 .irq = (ev_ring) + 1, \
102 .mode = MHI_DB_BRST_DISABLE, \
103 .data_type = MHI_ER_CTRL, \
104 .hardware_event = false, \
105 .client_managed = false, \
106 .offload_channel = false, \
109 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \
113 .num_elements = el_count, \
114 .event_ring = ev_ring, \
115 .dir = DMA_TO_DEVICE, \
116 .ee_mask = BIT(MHI_EE_AMSS), \
118 .doorbell = MHI_DB_BRST_ENABLE, \
119 .lpm_notify = false, \
120 .offload_channel = false, \
121 .doorbell_mode_switch = true, \
124 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \
128 .num_elements = el_count, \
129 .event_ring = ev_ring, \
130 .dir = DMA_FROM_DEVICE, \
131 .ee_mask = BIT(MHI_EE_AMSS), \
133 .doorbell = MHI_DB_BRST_ENABLE, \
134 .lpm_notify = false, \
135 .offload_channel = false, \
136 .doorbell_mode_switch = true, \
139 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
143 .num_elements = el_count, \
144 .event_ring = ev_ring, \
145 .dir = DMA_TO_DEVICE, \
146 .ee_mask = BIT(MHI_EE_SBL), \
148 .doorbell = MHI_DB_BRST_DISABLE, \
149 .lpm_notify = false, \
150 .offload_channel = false, \
151 .doorbell_mode_switch = false, \
154 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
158 .num_elements = el_count, \
159 .event_ring = ev_ring, \
160 .dir = DMA_FROM_DEVICE, \
161 .ee_mask = BIT(MHI_EE_SBL), \
163 .doorbell = MHI_DB_BRST_DISABLE, \
164 .lpm_notify = false, \
165 .offload_channel = false, \
166 .doorbell_mode_switch = false, \
169 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \
173 .num_elements = el_count, \
174 .event_ring = ev_ring, \
175 .dir = DMA_TO_DEVICE, \
176 .ee_mask = BIT(MHI_EE_FP), \
178 .doorbell = MHI_DB_BRST_DISABLE, \
179 .lpm_notify = false, \
180 .offload_channel = false, \
181 .doorbell_mode_switch = false, \
184 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \
188 .num_elements = el_count, \
189 .event_ring = ev_ring, \
190 .dir = DMA_FROM_DEVICE, \
191 .ee_mask = BIT(MHI_EE_FP), \
193 .doorbell = MHI_DB_BRST_DISABLE, \
194 .lpm_notify = false, \
195 .offload_channel = false, \
196 .doorbell_mode_switch = false, \
199 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
201 .num_elements = el_count, \
202 .irq_moderation_ms = 5, \
203 .irq = (ev_ring) + 1, \
205 .mode = MHI_DB_BRST_DISABLE, \
206 .data_type = MHI_ER_DATA, \
207 .hardware_event = false, \
208 .client_managed = false, \
209 .offload_channel = false, \
212 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
214 .num_elements = el_count, \
215 .irq_moderation_ms = 1, \
216 .irq = (ev_ring) + 1, \
218 .mode = MHI_DB_BRST_DISABLE, \
219 .data_type = MHI_ER_DATA, \
220 .hardware_event = true, \
221 .client_managed = false, \
222 .offload_channel = false, \
226 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
227 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
228 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
229 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
230 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
231 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
232 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
233 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
234 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
235 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
236 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
237 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
238 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
241 static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
242 /* first ring is control+data ring */
243 MHI_EVENT_CONFIG_CTRL(0, 64),
244 /* DIAG dedicated event ring */
245 MHI_EVENT_CONFIG_DATA(1, 128),
246 /* Hardware channels request dedicated hardware event rings */
247 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
248 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
251 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
254 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
255 .ch_cfg = modem_qcom_v1_mhi_channels,
256 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
257 .event_cfg = modem_qcom_v1_mhi_events,
260 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
261 .name = "qcom-sdx65m",
262 .fw = "qcom/sdx65m/xbl.elf",
263 .edl = "qcom/sdx65m/edl.mbn",
264 .config = &modem_qcom_v1_mhiv_config,
265 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
266 .dma_data_width = 32,
267 .sideband_wake = false,
270 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
271 .name = "qcom-sdx55m",
272 .fw = "qcom/sdx55m/sbl1.mbn",
273 .edl = "qcom/sdx55m/edl.mbn",
274 .config = &modem_qcom_v1_mhiv_config,
275 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
276 .dma_data_width = 32,
277 .mru_default = 32768,
278 .sideband_wake = false,
281 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
282 .name = "qcom-sdx24",
283 .edl = "qcom/prog_firehose_sdx24.mbn",
284 .config = &modem_qcom_v1_mhiv_config,
285 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
286 .dma_data_width = 32,
287 .sideband_wake = true,
290 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
291 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
292 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
293 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
294 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
295 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
296 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
297 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
298 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
299 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
300 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
301 /* The EDL firmware is a flash-programmer exposing firehose protocol */
302 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
303 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
304 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
305 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
308 static struct mhi_event_config mhi_quectel_em1xx_events[] = {
309 MHI_EVENT_CONFIG_CTRL(0, 128),
310 MHI_EVENT_CONFIG_DATA(1, 128),
311 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
312 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
315 static const struct mhi_controller_config modem_quectel_em1xx_config = {
318 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
319 .ch_cfg = mhi_quectel_em1xx_channels,
320 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
321 .event_cfg = mhi_quectel_em1xx_events,
324 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
325 .name = "quectel-em1xx",
326 .edl = "qcom/prog_firehose_sdx24.mbn",
327 .config = &modem_quectel_em1xx_config,
328 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
329 .dma_data_width = 32,
330 .sideband_wake = true,
333 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
334 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
335 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
336 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
337 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
338 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
339 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
340 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
341 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
342 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
343 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
346 static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
347 MHI_EVENT_CONFIG_CTRL(0, 128),
348 MHI_EVENT_CONFIG_DATA(1, 128),
349 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
350 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
353 static const struct mhi_controller_config modem_foxconn_sdx55_config = {
356 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
357 .ch_cfg = mhi_foxconn_sdx55_channels,
358 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
359 .event_cfg = mhi_foxconn_sdx55_events,
362 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
363 .name = "foxconn-sdx55",
364 .fw = "qcom/sdx55m/sbl1.mbn",
365 .edl = "qcom/sdx55m/edl.mbn",
366 .config = &modem_foxconn_sdx55_config,
367 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
368 .dma_data_width = 32,
369 .sideband_wake = false,
372 static const struct mhi_channel_config mhi_mv31_channels[] = {
373 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0),
374 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0),
375 /* MBIM Control Channel */
376 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0),
377 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0),
378 /* MBIM Data Channel */
379 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2),
380 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3),
383 static struct mhi_event_config mhi_mv31_events[] = {
384 MHI_EVENT_CONFIG_CTRL(0, 256),
385 MHI_EVENT_CONFIG_DATA(1, 256),
386 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
387 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101),
390 static const struct mhi_controller_config modem_mv31_config = {
393 .num_channels = ARRAY_SIZE(mhi_mv31_channels),
394 .ch_cfg = mhi_mv31_channels,
395 .num_events = ARRAY_SIZE(mhi_mv31_events),
396 .event_cfg = mhi_mv31_events,
399 static const struct mhi_pci_dev_info mhi_mv31_info = {
400 .name = "cinterion-mv31",
401 .config = &modem_mv31_config,
402 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
403 .dma_data_width = 32,
406 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = {
407 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
408 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0),
409 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0),
410 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0),
411 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0),
412 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0),
413 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
414 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
415 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
416 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
417 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1),
418 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2),
421 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = {
422 /* first ring is control+data and DIAG ring */
423 MHI_EVENT_CONFIG_CTRL(0, 2048),
424 /* Hardware channels request dedicated hardware event rings */
425 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100),
426 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101)
429 static const struct mhi_controller_config modem_sierra_em919x_config = {
432 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels),
433 .ch_cfg = mhi_sierra_em919x_channels,
434 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events),
435 .event_cfg = modem_sierra_em919x_mhi_events,
438 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = {
439 .name = "sierra-em919x",
440 .config = &modem_sierra_em919x_config,
441 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
442 .dma_data_width = 32,
443 .sideband_wake = false,
446 static const struct pci_device_id mhi_pci_id_table[] = {
447 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */
448 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200),
449 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info },
450 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
451 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
452 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
453 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
454 { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */
455 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
456 { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
457 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
458 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
459 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
460 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
461 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
462 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
463 /* DW5930e (sdx55), With eSIM, It's also T99W175 */
464 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
465 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
466 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
467 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
468 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
469 /* T99W175 (sdx55), Based on Qualcomm new baseline */
470 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf),
471 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
472 /* MV31-W (Cinterion) */
473 { PCI_DEVICE(0x1269, 0x00b3),
474 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
477 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
479 enum mhi_pci_device_status {
481 MHI_PCI_DEV_SUSPENDED,
484 struct mhi_pci_device {
485 struct mhi_controller mhi_cntrl;
486 struct pci_saved_state *pci_state;
487 struct work_struct recovery_work;
488 struct timer_list health_check_timer;
489 unsigned long status;
492 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
493 void __iomem *addr, u32 *out)
499 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
500 void __iomem *addr, u32 val)
505 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
506 enum mhi_callback cb)
508 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
510 /* Nothing to do for now */
512 case MHI_CB_FATAL_ERROR:
513 case MHI_CB_SYS_ERROR:
514 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);
515 pm_runtime_forbid(&pdev->dev);
517 case MHI_CB_EE_MISSION_MODE:
518 pm_runtime_allow(&pdev->dev);
525 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force)
530 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override)
535 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl)
540 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl)
542 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
545 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor))
548 if (vendor == (u16) ~0 || vendor == 0)
554 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
555 unsigned int bar_num, u64 dma_mask)
557 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
560 err = pci_assign_resource(pdev, bar_num);
564 err = pcim_enable_device(pdev);
566 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
570 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
572 dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
575 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
576 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
578 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
580 dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
584 pci_set_master(pdev);
589 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
590 const struct mhi_controller_config *mhi_cntrl_config)
592 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
597 * Alloc one MSI vector for BHI + one vector per event ring, ideally...
598 * No explicit pci_free_irq_vectors required, done by pcim_release.
600 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
602 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
603 if (nr_vectors < 0) {
604 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
609 if (nr_vectors < mhi_cntrl->nr_irqs) {
610 dev_warn(&pdev->dev, "using shared MSI\n");
612 /* Patch msi vectors, use only one (shared) */
613 for (i = 0; i < mhi_cntrl_config->num_events; i++)
614 mhi_cntrl_config->event_cfg[i].irq = 0;
615 mhi_cntrl->nr_irqs = 1;
618 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
622 for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
623 int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
625 irq[i] = pci_irq_vector(pdev, vector);
628 mhi_cntrl->irq = irq;
633 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
635 /* The runtime_get() MHI callback means:
636 * Do whatever is requested to leave M3.
638 return pm_runtime_get(mhi_cntrl->cntrl_dev);
641 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
643 /* The runtime_put() MHI callback means:
644 * Device can be moved in M3 state.
646 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);
647 pm_runtime_put(mhi_cntrl->cntrl_dev);
650 static void mhi_pci_recovery_work(struct work_struct *work)
652 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device,
654 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
655 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
658 dev_warn(&pdev->dev, "device recovery started\n");
660 del_timer(&mhi_pdev->health_check_timer);
661 pm_runtime_forbid(&pdev->dev);
663 /* Clean up MHI state */
664 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
665 mhi_power_down(mhi_cntrl, false);
666 mhi_unprepare_after_power_down(mhi_cntrl);
669 pci_set_power_state(pdev, PCI_D0);
670 pci_load_saved_state(pdev, mhi_pdev->pci_state);
671 pci_restore_state(pdev);
673 if (!mhi_pci_is_alive(mhi_cntrl))
676 err = mhi_prepare_for_power_up(mhi_cntrl);
680 err = mhi_sync_power_up(mhi_cntrl);
684 dev_dbg(&pdev->dev, "Recovery completed\n");
686 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
687 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
691 mhi_unprepare_after_power_down(mhi_cntrl);
693 if (pci_reset_function(pdev))
694 dev_err(&pdev->dev, "Recovery failed\n");
697 static void health_check(struct timer_list *t)
699 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer);
700 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
702 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
703 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
706 if (!mhi_pci_is_alive(mhi_cntrl)) {
707 dev_err(mhi_cntrl->cntrl_dev, "Device died\n");
708 queue_work(system_long_wq, &mhi_pdev->recovery_work);
712 /* reschedule in two seconds */
713 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
716 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
718 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
719 const struct mhi_controller_config *mhi_cntrl_config;
720 struct mhi_pci_device *mhi_pdev;
721 struct mhi_controller *mhi_cntrl;
724 dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name);
726 /* mhi_pdev.mhi_cntrl must be zero-initialized */
727 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);
731 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);
732 timer_setup(&mhi_pdev->health_check_timer, health_check, 0);
734 mhi_cntrl_config = info->config;
735 mhi_cntrl = &mhi_pdev->mhi_cntrl;
737 mhi_cntrl->cntrl_dev = &pdev->dev;
738 mhi_cntrl->iova_start = 0;
739 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);
740 mhi_cntrl->fw_image = info->fw;
741 mhi_cntrl->edl_image = info->edl;
743 mhi_cntrl->read_reg = mhi_pci_read_reg;
744 mhi_cntrl->write_reg = mhi_pci_write_reg;
745 mhi_cntrl->status_cb = mhi_pci_status_cb;
746 mhi_cntrl->runtime_get = mhi_pci_runtime_get;
747 mhi_cntrl->runtime_put = mhi_pci_runtime_put;
748 mhi_cntrl->mru = info->mru_default;
750 if (info->sideband_wake) {
751 mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
752 mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
753 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
756 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
760 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
764 pci_set_drvdata(pdev, mhi_pdev);
766 /* Have stored pci confspace at hand for restore in sudden PCI error.
767 * cache the state locally and discard the PCI core one.
769 pci_save_state(pdev);
770 mhi_pdev->pci_state = pci_store_saved_state(pdev);
771 pci_load_saved_state(pdev, NULL);
773 pci_enable_pcie_error_reporting(pdev);
775 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
777 goto err_disable_reporting;
779 /* MHI bus does not power up the controller by default */
780 err = mhi_prepare_for_power_up(mhi_cntrl);
782 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
786 err = mhi_sync_power_up(mhi_cntrl);
788 dev_err(&pdev->dev, "failed to power up MHI controller\n");
792 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
794 /* start health check */
795 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
797 /* Only allow runtime-suspend if PME capable (for wakeup) */
798 if (pci_pme_capable(pdev, PCI_D3hot)) {
799 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
800 pm_runtime_use_autosuspend(&pdev->dev);
801 pm_runtime_mark_last_busy(&pdev->dev);
802 pm_runtime_put_noidle(&pdev->dev);
808 mhi_unprepare_after_power_down(mhi_cntrl);
810 mhi_unregister_controller(mhi_cntrl);
811 err_disable_reporting:
812 pci_disable_pcie_error_reporting(pdev);
817 static void mhi_pci_remove(struct pci_dev *pdev)
819 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
820 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
822 del_timer_sync(&mhi_pdev->health_check_timer);
823 cancel_work_sync(&mhi_pdev->recovery_work);
825 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
826 mhi_power_down(mhi_cntrl, true);
827 mhi_unprepare_after_power_down(mhi_cntrl);
830 /* balancing probe put_noidle */
831 if (pci_pme_capable(pdev, PCI_D3hot))
832 pm_runtime_get_noresume(&pdev->dev);
834 mhi_unregister_controller(mhi_cntrl);
835 pci_disable_pcie_error_reporting(pdev);
838 static void mhi_pci_shutdown(struct pci_dev *pdev)
840 mhi_pci_remove(pdev);
841 pci_set_power_state(pdev, PCI_D3hot);
844 static void mhi_pci_reset_prepare(struct pci_dev *pdev)
846 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
847 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
849 dev_info(&pdev->dev, "reset\n");
851 del_timer(&mhi_pdev->health_check_timer);
853 /* Clean up MHI state */
854 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
855 mhi_power_down(mhi_cntrl, false);
856 mhi_unprepare_after_power_down(mhi_cntrl);
859 /* cause internal device reset */
860 mhi_soc_reset(mhi_cntrl);
862 /* Be sure device reset has been executed */
863 msleep(MHI_POST_RESET_DELAY_MS);
866 static void mhi_pci_reset_done(struct pci_dev *pdev)
868 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
869 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
872 /* Restore initial known working PCI state */
873 pci_load_saved_state(pdev, mhi_pdev->pci_state);
874 pci_restore_state(pdev);
876 /* Is device status available ? */
877 if (!mhi_pci_is_alive(mhi_cntrl)) {
878 dev_err(&pdev->dev, "reset failed\n");
882 err = mhi_prepare_for_power_up(mhi_cntrl);
884 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
888 err = mhi_sync_power_up(mhi_cntrl);
890 dev_err(&pdev->dev, "failed to power up MHI controller\n");
891 mhi_unprepare_after_power_down(mhi_cntrl);
895 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
896 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
899 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev,
900 pci_channel_state_t state)
902 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
903 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
905 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);
907 if (state == pci_channel_io_perm_failure)
908 return PCI_ERS_RESULT_DISCONNECT;
910 /* Clean up MHI state */
911 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
912 mhi_power_down(mhi_cntrl, false);
913 mhi_unprepare_after_power_down(mhi_cntrl);
916 return PCI_ERS_RESULT_RECOVERED;
919 pci_disable_device(pdev);
921 return PCI_ERS_RESULT_NEED_RESET;
924 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev)
926 if (pci_enable_device(pdev)) {
927 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
928 return PCI_ERS_RESULT_DISCONNECT;
931 return PCI_ERS_RESULT_RECOVERED;
934 static void mhi_pci_io_resume(struct pci_dev *pdev)
936 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
938 dev_err(&pdev->dev, "PCI slot reset done\n");
940 queue_work(system_long_wq, &mhi_pdev->recovery_work);
943 static const struct pci_error_handlers mhi_pci_err_handler = {
944 .error_detected = mhi_pci_error_detected,
945 .slot_reset = mhi_pci_slot_reset,
946 .resume = mhi_pci_io_resume,
947 .reset_prepare = mhi_pci_reset_prepare,
948 .reset_done = mhi_pci_reset_done,
951 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev)
953 struct pci_dev *pdev = to_pci_dev(dev);
954 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
955 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
958 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
961 del_timer(&mhi_pdev->health_check_timer);
962 cancel_work_sync(&mhi_pdev->recovery_work);
964 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
965 mhi_cntrl->ee != MHI_EE_AMSS)
966 goto pci_suspend; /* Nothing to do at MHI level */
968 /* Transition to M3 state */
969 err = mhi_pm_suspend(mhi_cntrl);
971 dev_err(&pdev->dev, "failed to suspend device: %d\n", err);
972 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);
977 pci_disable_device(pdev);
978 pci_wake_from_d3(pdev, true);
983 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev)
985 struct pci_dev *pdev = to_pci_dev(dev);
986 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
987 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
990 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
993 err = pci_enable_device(pdev);
997 pci_set_master(pdev);
998 pci_wake_from_d3(pdev, false);
1000 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1001 mhi_cntrl->ee != MHI_EE_AMSS)
1002 return 0; /* Nothing to do at MHI level */
1004 /* Exit M3, transition to M0 state */
1005 err = mhi_pm_resume(mhi_cntrl);
1007 dev_err(&pdev->dev, "failed to resume device: %d\n", err);
1011 /* Resume health check */
1012 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1014 /* It can be a remote wakeup (no mhi runtime_get), update access time */
1015 pm_runtime_mark_last_busy(dev);
1020 /* Do not fail to not mess up our PCI device state, the device likely
1021 * lost power (d3cold) and we simply need to reset it from the recovery
1022 * procedure, trigger the recovery asynchronously to prevent system
1023 * suspend exit delaying.
1025 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1026 pm_runtime_mark_last_busy(dev);
1031 static int __maybe_unused mhi_pci_suspend(struct device *dev)
1033 pm_runtime_disable(dev);
1034 return mhi_pci_runtime_suspend(dev);
1037 static int __maybe_unused mhi_pci_resume(struct device *dev)
1041 /* Depending the platform, device may have lost power (d3cold), we need
1042 * to resume it now to check its state and recover when necessary.
1044 ret = mhi_pci_runtime_resume(dev);
1045 pm_runtime_enable(dev);
1050 static int __maybe_unused mhi_pci_freeze(struct device *dev)
1052 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1053 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1055 /* We want to stop all operations, hibernation does not guarantee that
1056 * device will be in the same state as before freezing, especially if
1057 * the intermediate restore kernel reinitializes MHI device with new
1060 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1061 mhi_power_down(mhi_cntrl, true);
1062 mhi_unprepare_after_power_down(mhi_cntrl);
1068 static int __maybe_unused mhi_pci_restore(struct device *dev)
1070 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1072 /* Reinitialize the device */
1073 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1078 static const struct dev_pm_ops mhi_pci_pm_ops = {
1079 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
1080 #ifdef CONFIG_PM_SLEEP
1081 .suspend = mhi_pci_suspend,
1082 .resume = mhi_pci_resume,
1083 .freeze = mhi_pci_freeze,
1084 .thaw = mhi_pci_restore,
1085 .restore = mhi_pci_restore,
1089 static struct pci_driver mhi_pci_driver = {
1090 .name = "mhi-pci-generic",
1091 .id_table = mhi_pci_id_table,
1092 .probe = mhi_pci_probe,
1093 .remove = mhi_pci_remove,
1094 .shutdown = mhi_pci_shutdown,
1095 .err_handler = &mhi_pci_err_handler,
1096 .driver.pm = &mhi_pci_pm_ops
1098 module_pci_driver(mhi_pci_driver);
1100 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
1101 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
1102 MODULE_LICENSE("GPL");