1 // SPDX-License-Identifier: GPL-2.0
3 // Register map access API - MMIO support
5 // Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/module.h>
11 #include <linux/regmap.h>
12 #include <linux/slab.h>
13 #include <linux/swab.h>
17 struct regmap_mmio_context {
19 unsigned int val_bytes;
25 void (*reg_write)(struct regmap_mmio_context *ctx,
26 unsigned int reg, unsigned int val);
27 unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
31 static int regmap_mmio_regbits_check(size_t reg_bits)
43 static int regmap_mmio_get_min_stride(size_t val_bits)
49 /* The core treats 0 as 1 */
65 static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
69 writeb(val, ctx->regs + reg);
72 static void regmap_mmio_write8_relaxed(struct regmap_mmio_context *ctx,
76 writeb_relaxed(val, ctx->regs + reg);
79 static void regmap_mmio_iowrite8(struct regmap_mmio_context *ctx,
80 unsigned int reg, unsigned int val)
82 iowrite8(val, ctx->regs + reg);
85 static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
89 writew(val, ctx->regs + reg);
92 static void regmap_mmio_write16le_relaxed(struct regmap_mmio_context *ctx,
96 writew_relaxed(val, ctx->regs + reg);
99 static void regmap_mmio_iowrite16le(struct regmap_mmio_context *ctx,
100 unsigned int reg, unsigned int val)
102 iowrite16(val, ctx->regs + reg);
105 static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
109 writew(swab16(val), ctx->regs + reg);
112 static void regmap_mmio_iowrite16be(struct regmap_mmio_context *ctx,
113 unsigned int reg, unsigned int val)
115 iowrite16be(val, ctx->regs + reg);
118 static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
122 writel(val, ctx->regs + reg);
125 static void regmap_mmio_write32le_relaxed(struct regmap_mmio_context *ctx,
129 writel_relaxed(val, ctx->regs + reg);
132 static void regmap_mmio_iowrite32le(struct regmap_mmio_context *ctx,
133 unsigned int reg, unsigned int val)
135 iowrite32(val, ctx->regs + reg);
138 static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
142 writel(swab32(val), ctx->regs + reg);
145 static void regmap_mmio_iowrite32be(struct regmap_mmio_context *ctx,
146 unsigned int reg, unsigned int val)
148 iowrite32be(val, ctx->regs + reg);
151 static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
153 struct regmap_mmio_context *ctx = context;
156 if (!IS_ERR(ctx->clk)) {
157 ret = clk_enable(ctx->clk);
162 ctx->reg_write(ctx, reg, val);
164 if (!IS_ERR(ctx->clk))
165 clk_disable(ctx->clk);
170 static int regmap_mmio_noinc_write(void *context, unsigned int reg,
171 const void *val, size_t val_count)
173 struct regmap_mmio_context *ctx = context;
177 if (!IS_ERR(ctx->clk)) {
178 ret = clk_enable(ctx->clk);
184 * There are no native, assembly-optimized write single register
185 * operations for big endian, so fall back to emulation if this
186 * is needed. (Single bytes are fine, they are not affected by
189 if (ctx->big_endian && (ctx->val_bytes > 1)) {
190 switch (ctx->val_bytes) {
193 const u16 *valp = (const u16 *)val;
194 for (i = 0; i < val_count; i++)
195 writew(swab16(valp[i]), ctx->regs + reg);
200 const u32 *valp = (const u32 *)val;
201 for (i = 0; i < val_count; i++)
202 writel(swab32(valp[i]), ctx->regs + reg);
208 const u64 *valp = (const u64 *)val;
209 for (i = 0; i < val_count; i++)
210 writeq(swab64(valp[i]), ctx->regs + reg);
220 switch (ctx->val_bytes) {
222 writesb(ctx->regs + reg, (const u8 *)val, val_count);
225 writesw(ctx->regs + reg, (const u16 *)val, val_count);
228 writesl(ctx->regs + reg, (const u32 *)val, val_count);
232 writesq(ctx->regs + reg, (const u64 *)val, val_count);
241 if (!IS_ERR(ctx->clk))
242 clk_disable(ctx->clk);
247 static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
250 return readb(ctx->regs + reg);
253 static unsigned int regmap_mmio_read8_relaxed(struct regmap_mmio_context *ctx,
256 return readb_relaxed(ctx->regs + reg);
259 static unsigned int regmap_mmio_ioread8(struct regmap_mmio_context *ctx,
262 return ioread8(ctx->regs + reg);
265 static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
268 return readw(ctx->regs + reg);
271 static unsigned int regmap_mmio_read16le_relaxed(struct regmap_mmio_context *ctx,
274 return readw_relaxed(ctx->regs + reg);
277 static unsigned int regmap_mmio_ioread16le(struct regmap_mmio_context *ctx,
280 return ioread16(ctx->regs + reg);
283 static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
286 return swab16(readw(ctx->regs + reg));
289 static unsigned int regmap_mmio_ioread16be(struct regmap_mmio_context *ctx,
292 return ioread16be(ctx->regs + reg);
295 static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
298 return readl(ctx->regs + reg);
301 static unsigned int regmap_mmio_read32le_relaxed(struct regmap_mmio_context *ctx,
304 return readl_relaxed(ctx->regs + reg);
307 static unsigned int regmap_mmio_ioread32le(struct regmap_mmio_context *ctx,
310 return ioread32(ctx->regs + reg);
313 static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
316 return swab32(readl(ctx->regs + reg));
319 static unsigned int regmap_mmio_ioread32be(struct regmap_mmio_context *ctx,
322 return ioread32be(ctx->regs + reg);
325 static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
327 struct regmap_mmio_context *ctx = context;
330 if (!IS_ERR(ctx->clk)) {
331 ret = clk_enable(ctx->clk);
336 *val = ctx->reg_read(ctx, reg);
338 if (!IS_ERR(ctx->clk))
339 clk_disable(ctx->clk);
344 static int regmap_mmio_noinc_read(void *context, unsigned int reg,
345 void *val, size_t val_count)
347 struct regmap_mmio_context *ctx = context;
350 if (!IS_ERR(ctx->clk)) {
351 ret = clk_enable(ctx->clk);
356 switch (ctx->val_bytes) {
358 readsb(ctx->regs + reg, (u8 *)val, val_count);
361 readsw(ctx->regs + reg, (u16 *)val, val_count);
364 readsl(ctx->regs + reg, (u32 *)val, val_count);
368 readsq(ctx->regs + reg, (u64 *)val, val_count);
377 * There are no native, assembly-optimized write single register
378 * operations for big endian, so fall back to emulation if this
379 * is needed. (Single bytes are fine, they are not affected by
382 if (ctx->big_endian && (ctx->val_bytes > 1)) {
383 switch (ctx->val_bytes) {
385 swab16_array(val, val_count);
388 swab32_array(val, val_count);
392 swab64_array(val, val_count);
402 if (!IS_ERR(ctx->clk))
403 clk_disable(ctx->clk);
409 static void regmap_mmio_free_context(void *context)
411 struct regmap_mmio_context *ctx = context;
413 if (!IS_ERR(ctx->clk)) {
414 clk_unprepare(ctx->clk);
415 if (!ctx->attached_clk)
421 static const struct regmap_bus regmap_mmio = {
423 .reg_write = regmap_mmio_write,
424 .reg_read = regmap_mmio_read,
425 .reg_noinc_write = regmap_mmio_noinc_write,
426 .reg_noinc_read = regmap_mmio_noinc_read,
427 .free_context = regmap_mmio_free_context,
428 .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
431 static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
434 const struct regmap_config *config)
436 struct regmap_mmio_context *ctx;
440 ret = regmap_mmio_regbits_check(config->reg_bits);
444 if (config->pad_bits)
445 return ERR_PTR(-EINVAL);
447 min_stride = regmap_mmio_get_min_stride(config->val_bits);
449 return ERR_PTR(min_stride);
451 if (config->reg_stride && config->reg_stride < min_stride)
452 return ERR_PTR(-EINVAL);
454 if (config->use_relaxed_mmio && config->io_port)
455 return ERR_PTR(-EINVAL);
457 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
459 return ERR_PTR(-ENOMEM);
462 ctx->val_bytes = config->val_bits / 8;
463 ctx->clk = ERR_PTR(-ENODEV);
465 switch (regmap_get_val_endian(dev, ®map_mmio, config)) {
466 case REGMAP_ENDIAN_DEFAULT:
467 case REGMAP_ENDIAN_LITTLE:
468 #ifdef __LITTLE_ENDIAN
469 case REGMAP_ENDIAN_NATIVE:
471 switch (config->val_bits) {
473 if (config->io_port) {
474 ctx->reg_read = regmap_mmio_ioread8;
475 ctx->reg_write = regmap_mmio_iowrite8;
476 } else if (config->use_relaxed_mmio) {
477 ctx->reg_read = regmap_mmio_read8_relaxed;
478 ctx->reg_write = regmap_mmio_write8_relaxed;
480 ctx->reg_read = regmap_mmio_read8;
481 ctx->reg_write = regmap_mmio_write8;
485 if (config->io_port) {
486 ctx->reg_read = regmap_mmio_ioread16le;
487 ctx->reg_write = regmap_mmio_iowrite16le;
488 } else if (config->use_relaxed_mmio) {
489 ctx->reg_read = regmap_mmio_read16le_relaxed;
490 ctx->reg_write = regmap_mmio_write16le_relaxed;
492 ctx->reg_read = regmap_mmio_read16le;
493 ctx->reg_write = regmap_mmio_write16le;
497 if (config->io_port) {
498 ctx->reg_read = regmap_mmio_ioread32le;
499 ctx->reg_write = regmap_mmio_iowrite32le;
500 } else if (config->use_relaxed_mmio) {
501 ctx->reg_read = regmap_mmio_read32le_relaxed;
502 ctx->reg_write = regmap_mmio_write32le_relaxed;
504 ctx->reg_read = regmap_mmio_read32le;
505 ctx->reg_write = regmap_mmio_write32le;
513 case REGMAP_ENDIAN_BIG:
515 case REGMAP_ENDIAN_NATIVE:
517 ctx->big_endian = true;
518 switch (config->val_bits) {
520 if (config->io_port) {
521 ctx->reg_read = regmap_mmio_ioread8;
522 ctx->reg_write = regmap_mmio_iowrite8;
524 ctx->reg_read = regmap_mmio_read8;
525 ctx->reg_write = regmap_mmio_write8;
529 if (config->io_port) {
530 ctx->reg_read = regmap_mmio_ioread16be;
531 ctx->reg_write = regmap_mmio_iowrite16be;
533 ctx->reg_read = regmap_mmio_read16be;
534 ctx->reg_write = regmap_mmio_write16be;
538 if (config->io_port) {
539 ctx->reg_read = regmap_mmio_ioread32be;
540 ctx->reg_write = regmap_mmio_iowrite32be;
542 ctx->reg_read = regmap_mmio_read32be;
543 ctx->reg_write = regmap_mmio_write32be;
559 ctx->clk = clk_get(dev, clk_id);
560 if (IS_ERR(ctx->clk)) {
561 ret = PTR_ERR(ctx->clk);
565 ret = clk_prepare(ctx->clk);
579 struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
581 const struct regmap_config *config,
582 struct lock_class_key *lock_key,
583 const char *lock_name)
585 struct regmap_mmio_context *ctx;
587 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
589 return ERR_CAST(ctx);
591 return __regmap_init(dev, ®map_mmio, ctx, config,
592 lock_key, lock_name);
594 EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
596 struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
599 const struct regmap_config *config,
600 struct lock_class_key *lock_key,
601 const char *lock_name)
603 struct regmap_mmio_context *ctx;
605 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
607 return ERR_CAST(ctx);
609 return __devm_regmap_init(dev, ®map_mmio, ctx, config,
610 lock_key, lock_name);
612 EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
614 int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
616 struct regmap_mmio_context *ctx = map->bus_context;
619 ctx->attached_clk = true;
621 return clk_prepare(ctx->clk);
623 EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);
625 void regmap_mmio_detach_clk(struct regmap *map)
627 struct regmap_mmio_context *ctx = map->bus_context;
629 clk_unprepare(ctx->clk);
631 ctx->attached_clk = false;
634 EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
636 MODULE_LICENSE("GPL v2");