2 * regmap based irq_chip
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/device.h>
14 #include <linux/export.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
24 struct regmap_irq_chip_data {
26 struct irq_chip irq_chip;
29 const struct regmap_irq_chip *chip;
32 struct irq_domain *domain;
38 unsigned int *status_buf;
39 unsigned int *mask_buf;
40 unsigned int *mask_buf_def;
41 unsigned int *wake_buf;
42 unsigned int *type_buf;
43 unsigned int *type_buf_def;
45 unsigned int irq_reg_stride;
46 unsigned int type_reg_stride;
52 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
55 return &data->chip->irqs[irq];
58 static void regmap_irq_lock(struct irq_data *data)
60 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
65 static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
66 unsigned int reg, unsigned int mask,
69 if (d->chip->mask_writeonly)
70 return regmap_write_bits(d->map, reg, mask, val);
72 return regmap_update_bits(d->map, reg, mask, val);
75 static void regmap_irq_sync_unlock(struct irq_data *data)
77 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
78 struct regmap *map = d->map;
84 if (d->chip->runtime_pm) {
85 ret = pm_runtime_get_sync(map->dev);
87 dev_err(map->dev, "IRQ sync failed to resume: %d\n",
91 if (d->clear_status) {
92 for (i = 0; i < d->chip->num_regs; i++) {
93 reg = d->chip->status_base +
94 (i * map->reg_stride * d->irq_reg_stride);
96 ret = regmap_read(map, reg, &val);
99 "Failed to clear the interrupt status bits\n");
102 d->clear_status = false;
106 * If there's been a change in the mask write it back to the
107 * hardware. We rely on the use of the regmap core cache to
108 * suppress pointless writes.
110 for (i = 0; i < d->chip->num_regs; i++) {
111 if (!d->chip->mask_base)
114 reg = d->chip->mask_base +
115 (i * map->reg_stride * d->irq_reg_stride);
116 if (d->chip->mask_invert) {
117 ret = regmap_irq_update_bits(d, reg,
118 d->mask_buf_def[i], ~d->mask_buf[i]);
119 } else if (d->chip->unmask_base) {
120 /* set mask with mask_base register */
121 ret = regmap_irq_update_bits(d, reg,
122 d->mask_buf_def[i], ~d->mask_buf[i]);
125 "Failed to sync unmasks in %x\n",
127 unmask_offset = d->chip->unmask_base -
129 /* clear mask with unmask_base register */
130 ret = regmap_irq_update_bits(d,
135 ret = regmap_irq_update_bits(d, reg,
136 d->mask_buf_def[i], d->mask_buf[i]);
139 dev_err(d->map->dev, "Failed to sync masks in %x\n",
142 reg = d->chip->wake_base +
143 (i * map->reg_stride * d->irq_reg_stride);
145 if (d->chip->wake_invert)
146 ret = regmap_irq_update_bits(d, reg,
150 ret = regmap_irq_update_bits(d, reg,
155 "Failed to sync wakes in %x: %d\n",
159 if (!d->chip->init_ack_masked)
162 * Ack all the masked interrupts unconditionally,
163 * OR if there is masked interrupt which hasn't been Acked,
164 * it'll be ignored in irq handler, then may introduce irq storm
166 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
167 reg = d->chip->ack_base +
168 (i * map->reg_stride * d->irq_reg_stride);
169 /* some chips ack by write 0 */
170 if (d->chip->ack_invert)
171 ret = regmap_write(map, reg, ~d->mask_buf[i]);
173 ret = regmap_write(map, reg, d->mask_buf[i]);
175 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
180 /* Don't update the type bits if we're using mask bits for irq type. */
181 if (!d->chip->type_in_mask) {
182 for (i = 0; i < d->chip->num_type_reg; i++) {
183 if (!d->type_buf_def[i])
185 reg = d->chip->type_base +
186 (i * map->reg_stride * d->type_reg_stride);
187 if (d->chip->type_invert)
188 ret = regmap_irq_update_bits(d, reg,
189 d->type_buf_def[i], ~d->type_buf[i]);
191 ret = regmap_irq_update_bits(d, reg,
192 d->type_buf_def[i], d->type_buf[i]);
194 dev_err(d->map->dev, "Failed to sync type in %x\n",
199 if (d->chip->runtime_pm)
200 pm_runtime_put(map->dev);
202 /* If we've changed our wakeup count propagate it to the parent */
203 if (d->wake_count < 0)
204 for (i = d->wake_count; i < 0; i++)
205 irq_set_irq_wake(d->irq, 0);
206 else if (d->wake_count > 0)
207 for (i = 0; i < d->wake_count; i++)
208 irq_set_irq_wake(d->irq, 1);
212 mutex_unlock(&d->lock);
215 static void regmap_irq_enable(struct irq_data *data)
217 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
218 struct regmap *map = d->map;
219 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
220 unsigned int mask, type;
222 type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
225 * The type_in_mask flag means that the underlying hardware uses
226 * separate mask bits for rising and falling edge interrupts, but
227 * we want to make them into a single virtual interrupt with
230 * If the interrupt we're enabling defines the falling or rising
231 * masks then instead of using the regular mask bits for this
232 * interrupt, use the value previously written to the type buffer
233 * at the corresponding offset in regmap_irq_set_type().
235 if (d->chip->type_in_mask && type)
236 mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
238 mask = irq_data->mask;
240 if (d->chip->clear_on_unmask)
241 d->clear_status = true;
243 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
246 static void regmap_irq_disable(struct irq_data *data)
248 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
249 struct regmap *map = d->map;
250 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
252 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
255 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
257 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
258 struct regmap *map = d->map;
259 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
261 const struct regmap_irq_type *t = &irq_data->type;
263 if ((t->types_supported & type) != type)
266 reg = t->type_reg_offset / map->reg_stride;
268 if (t->type_reg_mask)
269 d->type_buf[reg] &= ~t->type_reg_mask;
271 d->type_buf[reg] &= ~(t->type_falling_val |
273 t->type_level_low_val |
274 t->type_level_high_val);
276 case IRQ_TYPE_EDGE_FALLING:
277 d->type_buf[reg] |= t->type_falling_val;
280 case IRQ_TYPE_EDGE_RISING:
281 d->type_buf[reg] |= t->type_rising_val;
284 case IRQ_TYPE_EDGE_BOTH:
285 d->type_buf[reg] |= (t->type_falling_val |
289 case IRQ_TYPE_LEVEL_HIGH:
290 d->type_buf[reg] |= t->type_level_high_val;
293 case IRQ_TYPE_LEVEL_LOW:
294 d->type_buf[reg] |= t->type_level_low_val;
302 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
304 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
305 struct regmap *map = d->map;
306 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
310 d->wake_buf[irq_data->reg_offset / map->reg_stride]
315 d->wake_buf[irq_data->reg_offset / map->reg_stride]
323 static const struct irq_chip regmap_irq_chip = {
324 .irq_bus_lock = regmap_irq_lock,
325 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
326 .irq_disable = regmap_irq_disable,
327 .irq_enable = regmap_irq_enable,
328 .irq_set_type = regmap_irq_set_type,
329 .irq_set_wake = regmap_irq_set_wake,
332 static irqreturn_t regmap_irq_thread(int irq, void *d)
334 struct regmap_irq_chip_data *data = d;
335 const struct regmap_irq_chip *chip = data->chip;
336 struct regmap *map = data->map;
338 bool handled = false;
341 if (chip->handle_pre_irq)
342 chip->handle_pre_irq(chip->irq_drv_data);
344 if (chip->runtime_pm) {
345 ret = pm_runtime_get_sync(map->dev);
347 dev_err(map->dev, "IRQ thread failed to resume: %d\n",
349 pm_runtime_put(map->dev);
355 * Read in the statuses, using a single bulk read if possible
356 * in order to reduce the I/O overheads.
358 if (!map->use_single_read && map->reg_stride == 1 &&
359 data->irq_reg_stride == 1) {
360 u8 *buf8 = data->status_reg_buf;
361 u16 *buf16 = data->status_reg_buf;
362 u32 *buf32 = data->status_reg_buf;
364 BUG_ON(!data->status_reg_buf);
366 ret = regmap_bulk_read(map, chip->status_base,
367 data->status_reg_buf,
370 dev_err(map->dev, "Failed to read IRQ status: %d\n",
375 for (i = 0; i < data->chip->num_regs; i++) {
376 switch (map->format.val_bytes) {
378 data->status_buf[i] = buf8[i];
381 data->status_buf[i] = buf16[i];
384 data->status_buf[i] = buf32[i];
393 for (i = 0; i < data->chip->num_regs; i++) {
394 ret = regmap_read(map, chip->status_base +
396 * data->irq_reg_stride),
397 &data->status_buf[i]);
401 "Failed to read IRQ status: %d\n",
403 if (chip->runtime_pm)
404 pm_runtime_put(map->dev);
411 * Ignore masked IRQs and ack if we need to; we ack early so
412 * there is no race between handling and acknowleding the
413 * interrupt. We assume that typically few of the interrupts
414 * will fire simultaneously so don't worry about overhead from
415 * doing a write per register.
417 for (i = 0; i < data->chip->num_regs; i++) {
418 data->status_buf[i] &= ~data->mask_buf[i];
420 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
421 reg = chip->ack_base +
422 (i * map->reg_stride * data->irq_reg_stride);
423 ret = regmap_write(map, reg, data->status_buf[i]);
425 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
430 for (i = 0; i < chip->num_irqs; i++) {
431 if (data->status_buf[chip->irqs[i].reg_offset /
432 map->reg_stride] & chip->irqs[i].mask) {
433 handle_nested_irq(irq_find_mapping(data->domain, i));
438 if (chip->runtime_pm)
439 pm_runtime_put(map->dev);
442 if (chip->handle_post_irq)
443 chip->handle_post_irq(chip->irq_drv_data);
451 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
454 struct regmap_irq_chip_data *data = h->host_data;
456 irq_set_chip_data(virq, data);
457 irq_set_chip(virq, &data->irq_chip);
458 irq_set_nested_thread(virq, 1);
459 irq_set_parent(virq, data->irq);
460 irq_set_noprobe(virq);
465 static const struct irq_domain_ops regmap_domain_ops = {
466 .map = regmap_irq_map,
467 .xlate = irq_domain_xlate_onetwocell,
471 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
473 * @map: The regmap for the device.
474 * @irq: The IRQ the device uses to signal interrupts.
475 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
476 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
477 * @chip: Configuration for the interrupt controller.
478 * @data: Runtime data structure for the controller, allocated on success.
480 * Returns 0 on success or an errno on failure.
482 * In order for this to be efficient the chip really should use a
483 * register cache. The chip driver is responsible for restoring the
484 * register values used by the IRQ controller over suspend and resume.
486 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
487 int irq_base, const struct regmap_irq_chip *chip,
488 struct regmap_irq_chip_data **data)
490 struct regmap_irq_chip_data *d;
497 if (chip->num_regs <= 0)
500 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
503 for (i = 0; i < chip->num_irqs; i++) {
504 if (chip->irqs[i].reg_offset % map->reg_stride)
506 if (chip->irqs[i].reg_offset / map->reg_stride >=
512 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
514 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
520 d = kzalloc(sizeof(*d), GFP_KERNEL);
524 d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
529 d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
534 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
536 if (!d->mask_buf_def)
539 if (chip->wake_base) {
540 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
546 num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
548 d->type_buf_def = kcalloc(num_type_reg,
549 sizeof(unsigned int), GFP_KERNEL);
550 if (!d->type_buf_def)
553 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
559 d->irq_chip = regmap_irq_chip;
560 d->irq_chip.name = chip->name;
564 d->irq_base = irq_base;
566 if (chip->irq_reg_stride)
567 d->irq_reg_stride = chip->irq_reg_stride;
569 d->irq_reg_stride = 1;
571 if (chip->type_reg_stride)
572 d->type_reg_stride = chip->type_reg_stride;
574 d->type_reg_stride = 1;
576 if (!map->use_single_read && map->reg_stride == 1 &&
577 d->irq_reg_stride == 1) {
578 d->status_reg_buf = kmalloc_array(chip->num_regs,
579 map->format.val_bytes,
581 if (!d->status_reg_buf)
585 mutex_init(&d->lock);
587 for (i = 0; i < chip->num_irqs; i++)
588 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
589 |= chip->irqs[i].mask;
591 /* Mask all the interrupts by default */
592 for (i = 0; i < chip->num_regs; i++) {
593 d->mask_buf[i] = d->mask_buf_def[i];
594 if (!chip->mask_base)
597 reg = chip->mask_base +
598 (i * map->reg_stride * d->irq_reg_stride);
599 if (chip->mask_invert)
600 ret = regmap_irq_update_bits(d, reg,
601 d->mask_buf[i], ~d->mask_buf[i]);
602 else if (d->chip->unmask_base) {
603 unmask_offset = d->chip->unmask_base -
605 ret = regmap_irq_update_bits(d,
610 ret = regmap_irq_update_bits(d, reg,
611 d->mask_buf[i], d->mask_buf[i]);
613 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
618 if (!chip->init_ack_masked)
621 /* Ack masked but set interrupts */
622 reg = chip->status_base +
623 (i * map->reg_stride * d->irq_reg_stride);
624 ret = regmap_read(map, reg, &d->status_buf[i]);
626 dev_err(map->dev, "Failed to read IRQ status: %d\n",
631 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
632 reg = chip->ack_base +
633 (i * map->reg_stride * d->irq_reg_stride);
634 if (chip->ack_invert)
635 ret = regmap_write(map, reg,
636 ~(d->status_buf[i] & d->mask_buf[i]));
638 ret = regmap_write(map, reg,
639 d->status_buf[i] & d->mask_buf[i]);
641 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
648 /* Wake is disabled by default */
650 for (i = 0; i < chip->num_regs; i++) {
651 d->wake_buf[i] = d->mask_buf_def[i];
652 reg = chip->wake_base +
653 (i * map->reg_stride * d->irq_reg_stride);
655 if (chip->wake_invert)
656 ret = regmap_irq_update_bits(d, reg,
660 ret = regmap_irq_update_bits(d, reg,
664 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
671 if (chip->num_type_reg && !chip->type_in_mask) {
672 for (i = 0; i < chip->num_type_reg; ++i) {
673 if (!d->type_buf_def[i])
676 reg = chip->type_base +
677 (i * map->reg_stride * d->type_reg_stride);
679 ret = regmap_read(map, reg, &d->type_buf_def[i]);
681 if (d->chip->type_invert)
682 d->type_buf_def[i] = ~d->type_buf_def[i];
685 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
693 d->domain = irq_domain_add_legacy(map->dev->of_node,
694 chip->num_irqs, irq_base, 0,
695 ®map_domain_ops, d);
697 d->domain = irq_domain_add_linear(map->dev->of_node,
699 ®map_domain_ops, d);
701 dev_err(map->dev, "Failed to create IRQ domain\n");
706 ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
707 irq_flags | IRQF_ONESHOT,
710 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
711 irq, chip->name, ret);
720 /* Should really dispose of the domain but... */
723 kfree(d->type_buf_def);
725 kfree(d->mask_buf_def);
727 kfree(d->status_buf);
728 kfree(d->status_reg_buf);
732 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
735 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
737 * @irq: Primary IRQ for the device
738 * @d: ®map_irq_chip_data allocated by regmap_add_irq_chip()
740 * This function also disposes of all mapped IRQs on the chip.
742 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
752 /* Dispose all virtual irq from irq domain before removing it */
753 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
754 /* Ignore hwirq if holes in the IRQ list */
755 if (!d->chip->irqs[hwirq].mask)
759 * Find the virtual irq of hwirq on chip and if it is
760 * there then dispose it
762 virq = irq_find_mapping(d->domain, hwirq);
764 irq_dispose_mapping(virq);
767 irq_domain_remove(d->domain);
769 kfree(d->type_buf_def);
771 kfree(d->mask_buf_def);
773 kfree(d->status_reg_buf);
774 kfree(d->status_buf);
777 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
779 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
781 struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
783 regmap_del_irq_chip(d->irq, d);
786 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
789 struct regmap_irq_chip_data **r = res;
799 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
801 * @dev: The device pointer on which irq_chip belongs to.
802 * @map: The regmap for the device.
803 * @irq: The IRQ the device uses to signal interrupts
804 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
805 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
806 * @chip: Configuration for the interrupt controller.
807 * @data: Runtime data structure for the controller, allocated on success
809 * Returns 0 on success or an errno on failure.
811 * The ®map_irq_chip_data will be automatically released when the device is
814 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
815 int irq_flags, int irq_base,
816 const struct regmap_irq_chip *chip,
817 struct regmap_irq_chip_data **data)
819 struct regmap_irq_chip_data **ptr, *d;
822 ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
827 ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
835 devres_add(dev, ptr);
839 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
842 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
844 * @dev: Device for which which resource was allocated.
845 * @irq: Primary IRQ for the device.
846 * @data: ®map_irq_chip_data allocated by regmap_add_irq_chip().
848 * A resource managed version of regmap_del_irq_chip().
850 void devm_regmap_del_irq_chip(struct device *dev, int irq,
851 struct regmap_irq_chip_data *data)
855 WARN_ON(irq != data->irq);
856 rc = devres_release(dev, devm_regmap_irq_chip_release,
857 devm_regmap_irq_chip_match, data);
862 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
865 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
867 * @data: regmap irq controller to operate on.
869 * Useful for drivers to request their own IRQs.
871 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
873 WARN_ON(!data->irq_base);
874 return data->irq_base;
876 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
879 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
881 * @data: regmap irq controller to operate on.
882 * @irq: index of the interrupt requested in the chip IRQs.
884 * Useful for drivers to request their own IRQs.
886 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
888 /* Handle holes in the IRQ list */
889 if (!data->chip->irqs[irq].mask)
892 return irq_create_mapping(data->domain, irq);
894 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
897 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
899 * @data: regmap_irq controller to operate on.
901 * Useful for drivers to request their own IRQs and for integration
902 * with subsystems. For ease of integration NULL is accepted as a
903 * domain, allowing devices to just call this even if no domain is
906 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
913 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);