1 // SPDX-License-Identifier: GPL-2.0
3 // regmap based irq_chip
5 // Copyright 2011 Wolfson Microelectronics plc
7 // Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 #include <linux/device.h>
10 #include <linux/export.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
20 struct regmap_irq_chip_data {
22 struct irq_chip irq_chip;
25 const struct regmap_irq_chip *chip;
28 struct irq_domain *domain;
34 unsigned int *main_status_buf;
35 unsigned int *status_buf;
36 unsigned int *mask_buf;
37 unsigned int *mask_buf_def;
38 unsigned int *wake_buf;
39 unsigned int *type_buf;
40 unsigned int *type_buf_def;
41 unsigned int **virt_buf;
43 unsigned int irq_reg_stride;
44 unsigned int type_reg_stride;
49 static int sub_irq_reg(struct regmap_irq_chip_data *data,
50 unsigned int base_reg, int i)
52 const struct regmap_irq_chip *chip = data->chip;
53 struct regmap *map = data->map;
54 struct regmap_irq_sub_irq_map *subreg;
58 if (!chip->sub_reg_offsets || !chip->not_fixed_stride) {
59 /* Assume linear mapping */
60 reg = base_reg + (i * map->reg_stride * data->irq_reg_stride);
62 subreg = &chip->sub_reg_offsets[i];
63 offset = subreg->offset[0];
64 reg = base_reg + offset;
71 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
74 return &data->chip->irqs[irq];
77 static void regmap_irq_lock(struct irq_data *data)
79 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
84 static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
85 unsigned int reg, unsigned int mask,
88 if (d->chip->mask_writeonly)
89 return regmap_write_bits(d->map, reg, mask, val);
91 return regmap_update_bits(d->map, reg, mask, val);
94 static void regmap_irq_sync_unlock(struct irq_data *data)
96 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
97 struct regmap *map = d->map;
103 if (d->chip->runtime_pm) {
104 ret = pm_runtime_get_sync(map->dev);
106 dev_err(map->dev, "IRQ sync failed to resume: %d\n",
110 if (d->clear_status) {
111 for (i = 0; i < d->chip->num_regs; i++) {
112 reg = sub_irq_reg(d, d->chip->status_base, i);
114 ret = regmap_read(map, reg, &val);
117 "Failed to clear the interrupt status bits\n");
120 d->clear_status = false;
124 * If there's been a change in the mask write it back to the
125 * hardware. We rely on the use of the regmap core cache to
126 * suppress pointless writes.
128 for (i = 0; i < d->chip->num_regs; i++) {
129 if (!d->chip->mask_base)
132 reg = sub_irq_reg(d, d->chip->mask_base, i);
133 if (d->chip->mask_invert) {
134 ret = regmap_irq_update_bits(d, reg,
135 d->mask_buf_def[i], ~d->mask_buf[i]);
136 } else if (d->chip->unmask_base) {
137 /* set mask with mask_base register */
138 ret = regmap_irq_update_bits(d, reg,
139 d->mask_buf_def[i], ~d->mask_buf[i]);
142 "Failed to sync unmasks in %x\n",
144 unmask_offset = d->chip->unmask_base -
146 /* clear mask with unmask_base register */
147 ret = regmap_irq_update_bits(d,
152 ret = regmap_irq_update_bits(d, reg,
153 d->mask_buf_def[i], d->mask_buf[i]);
156 dev_err(d->map->dev, "Failed to sync masks in %x\n",
159 reg = sub_irq_reg(d, d->chip->wake_base, i);
161 if (d->chip->wake_invert)
162 ret = regmap_irq_update_bits(d, reg,
166 ret = regmap_irq_update_bits(d, reg,
171 "Failed to sync wakes in %x: %d\n",
175 if (!d->chip->init_ack_masked)
178 * Ack all the masked interrupts unconditionally,
179 * OR if there is masked interrupt which hasn't been Acked,
180 * it'll be ignored in irq handler, then may introduce irq storm
182 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
183 reg = sub_irq_reg(d, d->chip->ack_base, i);
185 /* some chips ack by write 0 */
186 if (d->chip->ack_invert)
187 ret = regmap_write(map, reg, ~d->mask_buf[i]);
189 ret = regmap_write(map, reg, d->mask_buf[i]);
190 if (d->chip->clear_ack) {
191 if (d->chip->ack_invert && !ret)
192 ret = regmap_write(map, reg,
195 ret = regmap_write(map, reg,
199 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
204 /* Don't update the type bits if we're using mask bits for irq type. */
205 if (!d->chip->type_in_mask) {
206 for (i = 0; i < d->chip->num_type_reg; i++) {
207 if (!d->type_buf_def[i])
209 reg = sub_irq_reg(d, d->chip->type_base, i);
210 if (d->chip->type_invert)
211 ret = regmap_irq_update_bits(d, reg,
212 d->type_buf_def[i], ~d->type_buf[i]);
214 ret = regmap_irq_update_bits(d, reg,
215 d->type_buf_def[i], d->type_buf[i]);
217 dev_err(d->map->dev, "Failed to sync type in %x\n",
222 if (d->chip->num_virt_regs) {
223 for (i = 0; i < d->chip->num_virt_regs; i++) {
224 for (j = 0; j < d->chip->num_regs; j++) {
225 reg = sub_irq_reg(d, d->chip->virt_reg_base[i],
227 ret = regmap_write(map, reg, d->virt_buf[i][j]);
230 "Failed to write virt 0x%x: %d\n",
236 if (d->chip->runtime_pm)
237 pm_runtime_put(map->dev);
239 /* If we've changed our wakeup count propagate it to the parent */
240 if (d->wake_count < 0)
241 for (i = d->wake_count; i < 0; i++)
242 irq_set_irq_wake(d->irq, 0);
243 else if (d->wake_count > 0)
244 for (i = 0; i < d->wake_count; i++)
245 irq_set_irq_wake(d->irq, 1);
249 mutex_unlock(&d->lock);
252 static void regmap_irq_enable(struct irq_data *data)
254 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
255 struct regmap *map = d->map;
256 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
257 unsigned int mask, type;
259 type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
262 * The type_in_mask flag means that the underlying hardware uses
263 * separate mask bits for rising and falling edge interrupts, but
264 * we want to make them into a single virtual interrupt with
267 * If the interrupt we're enabling defines the falling or rising
268 * masks then instead of using the regular mask bits for this
269 * interrupt, use the value previously written to the type buffer
270 * at the corresponding offset in regmap_irq_set_type().
272 if (d->chip->type_in_mask && type)
273 mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
275 mask = irq_data->mask;
277 if (d->chip->clear_on_unmask)
278 d->clear_status = true;
280 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
283 static void regmap_irq_disable(struct irq_data *data)
285 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
286 struct regmap *map = d->map;
287 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
289 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
292 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
294 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
295 struct regmap *map = d->map;
296 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
298 const struct regmap_irq_type *t = &irq_data->type;
300 if ((t->types_supported & type) != type)
303 reg = t->type_reg_offset / map->reg_stride;
305 if (t->type_reg_mask)
306 d->type_buf[reg] &= ~t->type_reg_mask;
308 d->type_buf[reg] &= ~(t->type_falling_val |
310 t->type_level_low_val |
311 t->type_level_high_val);
313 case IRQ_TYPE_EDGE_FALLING:
314 d->type_buf[reg] |= t->type_falling_val;
317 case IRQ_TYPE_EDGE_RISING:
318 d->type_buf[reg] |= t->type_rising_val;
321 case IRQ_TYPE_EDGE_BOTH:
322 d->type_buf[reg] |= (t->type_falling_val |
326 case IRQ_TYPE_LEVEL_HIGH:
327 d->type_buf[reg] |= t->type_level_high_val;
330 case IRQ_TYPE_LEVEL_LOW:
331 d->type_buf[reg] |= t->type_level_low_val;
337 if (d->chip->set_type_virt)
338 return d->chip->set_type_virt(d->virt_buf, type, data->hwirq,
344 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
346 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
347 struct regmap *map = d->map;
348 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
352 d->wake_buf[irq_data->reg_offset / map->reg_stride]
357 d->wake_buf[irq_data->reg_offset / map->reg_stride]
365 static const struct irq_chip regmap_irq_chip = {
366 .irq_bus_lock = regmap_irq_lock,
367 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
368 .irq_disable = regmap_irq_disable,
369 .irq_enable = regmap_irq_enable,
370 .irq_set_type = regmap_irq_set_type,
371 .irq_set_wake = regmap_irq_set_wake,
374 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
377 const struct regmap_irq_chip *chip = data->chip;
378 struct regmap *map = data->map;
379 struct regmap_irq_sub_irq_map *subreg;
382 if (!chip->sub_reg_offsets) {
383 /* Assume linear mapping */
384 ret = regmap_read(map, chip->status_base +
385 (b * map->reg_stride * data->irq_reg_stride),
386 &data->status_buf[b]);
388 subreg = &chip->sub_reg_offsets[b];
389 for (i = 0; i < subreg->num_regs; i++) {
390 unsigned int offset = subreg->offset[i];
392 if (chip->not_fixed_stride)
393 ret = regmap_read(map,
394 chip->status_base + offset,
395 &data->status_buf[b]);
397 ret = regmap_read(map,
398 chip->status_base + offset,
399 &data->status_buf[offset]);
408 static irqreturn_t regmap_irq_thread(int irq, void *d)
410 struct regmap_irq_chip_data *data = d;
411 const struct regmap_irq_chip *chip = data->chip;
412 struct regmap *map = data->map;
414 bool handled = false;
417 if (chip->handle_pre_irq)
418 chip->handle_pre_irq(chip->irq_drv_data);
420 if (chip->runtime_pm) {
421 ret = pm_runtime_get_sync(map->dev);
423 dev_err(map->dev, "IRQ thread failed to resume: %d\n",
430 * Read only registers with active IRQs if the chip has 'main status
431 * register'. Else read in the statuses, using a single bulk read if
432 * possible in order to reduce the I/O overheads.
435 if (chip->num_main_regs) {
436 unsigned int max_main_bits;
439 size = chip->num_regs * sizeof(unsigned int);
441 max_main_bits = (chip->num_main_status_bits) ?
442 chip->num_main_status_bits : chip->num_regs;
443 /* Clear the status buf as we don't read all status regs */
444 memset(data->status_buf, 0, size);
446 /* We could support bulk read for main status registers
447 * but I don't expect to see devices with really many main
448 * status registers so let's only support single reads for the
449 * sake of simplicity. and add bulk reads only if needed
451 for (i = 0; i < chip->num_main_regs; i++) {
452 ret = regmap_read(map, chip->main_status +
454 * data->irq_reg_stride),
455 &data->main_status_buf[i]);
458 "Failed to read IRQ status %d\n",
464 /* Read sub registers with active IRQs */
465 for (i = 0; i < chip->num_main_regs; i++) {
467 const unsigned long mreg = data->main_status_buf[i];
469 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
470 if (i * map->format.val_bytes * 8 + b >
473 ret = read_sub_irq_data(data, b);
477 "Failed to read IRQ status %d\n",
484 } else if (!map->use_single_read && map->reg_stride == 1 &&
485 data->irq_reg_stride == 1) {
487 u8 *buf8 = data->status_reg_buf;
488 u16 *buf16 = data->status_reg_buf;
489 u32 *buf32 = data->status_reg_buf;
491 BUG_ON(!data->status_reg_buf);
493 ret = regmap_bulk_read(map, chip->status_base,
494 data->status_reg_buf,
497 dev_err(map->dev, "Failed to read IRQ status: %d\n",
502 for (i = 0; i < data->chip->num_regs; i++) {
503 switch (map->format.val_bytes) {
505 data->status_buf[i] = buf8[i];
508 data->status_buf[i] = buf16[i];
511 data->status_buf[i] = buf32[i];
520 for (i = 0; i < data->chip->num_regs; i++) {
521 unsigned int reg = sub_irq_reg(data,
522 data->chip->status_base, i);
523 ret = regmap_read(map, reg, &data->status_buf[i]);
527 "Failed to read IRQ status: %d\n",
534 if (chip->status_invert)
535 for (i = 0; i < data->chip->num_regs; i++)
536 data->status_buf[i] = ~data->status_buf[i];
539 * Ignore masked IRQs and ack if we need to; we ack early so
540 * there is no race between handling and acknowleding the
541 * interrupt. We assume that typically few of the interrupts
542 * will fire simultaneously so don't worry about overhead from
543 * doing a write per register.
545 for (i = 0; i < data->chip->num_regs; i++) {
546 data->status_buf[i] &= ~data->mask_buf[i];
548 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
549 reg = sub_irq_reg(data, data->chip->ack_base, i);
551 if (chip->ack_invert)
552 ret = regmap_write(map, reg,
553 ~data->status_buf[i]);
555 ret = regmap_write(map, reg,
556 data->status_buf[i]);
557 if (chip->clear_ack) {
558 if (chip->ack_invert && !ret)
559 ret = regmap_write(map, reg,
560 data->status_buf[i]);
562 ret = regmap_write(map, reg,
563 ~data->status_buf[i]);
566 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
571 for (i = 0; i < chip->num_irqs; i++) {
572 if (data->status_buf[chip->irqs[i].reg_offset /
573 map->reg_stride] & chip->irqs[i].mask) {
574 handle_nested_irq(irq_find_mapping(data->domain, i));
580 if (chip->runtime_pm)
581 pm_runtime_put(map->dev);
583 if (chip->handle_post_irq)
584 chip->handle_post_irq(chip->irq_drv_data);
592 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
595 struct regmap_irq_chip_data *data = h->host_data;
597 irq_set_chip_data(virq, data);
598 irq_set_chip(virq, &data->irq_chip);
599 irq_set_nested_thread(virq, 1);
600 irq_set_parent(virq, data->irq);
601 irq_set_noprobe(virq);
606 static const struct irq_domain_ops regmap_domain_ops = {
607 .map = regmap_irq_map,
608 .xlate = irq_domain_xlate_onetwocell,
612 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
614 * @fwnode: The firmware node where the IRQ domain should be added to.
615 * @map: The regmap for the device.
616 * @irq: The IRQ the device uses to signal interrupts.
617 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
618 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
619 * @chip: Configuration for the interrupt controller.
620 * @data: Runtime data structure for the controller, allocated on success.
622 * Returns 0 on success or an errno on failure.
624 * In order for this to be efficient the chip really should use a
625 * register cache. The chip driver is responsible for restoring the
626 * register values used by the IRQ controller over suspend and resume.
628 int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode,
629 struct regmap *map, int irq,
630 int irq_flags, int irq_base,
631 const struct regmap_irq_chip *chip,
632 struct regmap_irq_chip_data **data)
634 struct regmap_irq_chip_data *d;
641 if (chip->num_regs <= 0)
644 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
647 for (i = 0; i < chip->num_irqs; i++) {
648 if (chip->irqs[i].reg_offset % map->reg_stride)
650 if (chip->irqs[i].reg_offset / map->reg_stride >=
655 if (chip->not_fixed_stride) {
656 for (i = 0; i < chip->num_regs; i++)
657 if (chip->sub_reg_offsets[i].num_regs != 1)
662 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
664 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
670 d = kzalloc(sizeof(*d), GFP_KERNEL);
674 if (chip->num_main_regs) {
675 d->main_status_buf = kcalloc(chip->num_main_regs,
676 sizeof(unsigned int),
679 if (!d->main_status_buf)
683 d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
688 d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
693 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
695 if (!d->mask_buf_def)
698 if (chip->wake_base) {
699 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
705 num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
707 d->type_buf_def = kcalloc(num_type_reg,
708 sizeof(unsigned int), GFP_KERNEL);
709 if (!d->type_buf_def)
712 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
718 if (chip->num_virt_regs) {
720 * Create virt_buf[chip->num_extra_config_regs][chip->num_regs]
722 d->virt_buf = kcalloc(chip->num_virt_regs, sizeof(*d->virt_buf),
727 for (i = 0; i < chip->num_virt_regs; i++) {
728 d->virt_buf[i] = kcalloc(chip->num_regs,
729 sizeof(unsigned int),
736 d->irq_chip = regmap_irq_chip;
737 d->irq_chip.name = chip->name;
741 d->irq_base = irq_base;
743 if (chip->irq_reg_stride)
744 d->irq_reg_stride = chip->irq_reg_stride;
746 d->irq_reg_stride = 1;
748 if (chip->type_reg_stride)
749 d->type_reg_stride = chip->type_reg_stride;
751 d->type_reg_stride = 1;
753 if (!map->use_single_read && map->reg_stride == 1 &&
754 d->irq_reg_stride == 1) {
755 d->status_reg_buf = kmalloc_array(chip->num_regs,
756 map->format.val_bytes,
758 if (!d->status_reg_buf)
762 mutex_init(&d->lock);
764 for (i = 0; i < chip->num_irqs; i++)
765 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
766 |= chip->irqs[i].mask;
768 /* Mask all the interrupts by default */
769 for (i = 0; i < chip->num_regs; i++) {
770 d->mask_buf[i] = d->mask_buf_def[i];
771 if (!chip->mask_base)
774 reg = sub_irq_reg(d, d->chip->mask_base, i);
776 if (chip->mask_invert)
777 ret = regmap_irq_update_bits(d, reg,
778 d->mask_buf[i], ~d->mask_buf[i]);
779 else if (d->chip->unmask_base) {
780 unmask_offset = d->chip->unmask_base -
782 ret = regmap_irq_update_bits(d,
787 ret = regmap_irq_update_bits(d, reg,
788 d->mask_buf[i], d->mask_buf[i]);
790 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
795 if (!chip->init_ack_masked)
798 /* Ack masked but set interrupts */
799 reg = sub_irq_reg(d, d->chip->status_base, i);
800 ret = regmap_read(map, reg, &d->status_buf[i]);
802 dev_err(map->dev, "Failed to read IRQ status: %d\n",
807 if (chip->status_invert)
808 d->status_buf[i] = ~d->status_buf[i];
810 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
811 reg = sub_irq_reg(d, d->chip->ack_base, i);
812 if (chip->ack_invert)
813 ret = regmap_write(map, reg,
814 ~(d->status_buf[i] & d->mask_buf[i]));
816 ret = regmap_write(map, reg,
817 d->status_buf[i] & d->mask_buf[i]);
818 if (chip->clear_ack) {
819 if (chip->ack_invert && !ret)
820 ret = regmap_write(map, reg,
824 ret = regmap_write(map, reg,
829 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
836 /* Wake is disabled by default */
838 for (i = 0; i < chip->num_regs; i++) {
839 d->wake_buf[i] = d->mask_buf_def[i];
840 reg = sub_irq_reg(d, d->chip->wake_base, i);
842 if (chip->wake_invert)
843 ret = regmap_irq_update_bits(d, reg,
847 ret = regmap_irq_update_bits(d, reg,
851 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
858 if (chip->num_type_reg && !chip->type_in_mask) {
859 for (i = 0; i < chip->num_type_reg; ++i) {
860 reg = sub_irq_reg(d, d->chip->type_base, i);
862 ret = regmap_read(map, reg, &d->type_buf_def[i]);
864 if (d->chip->type_invert)
865 d->type_buf_def[i] = ~d->type_buf_def[i];
868 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
876 d->domain = irq_domain_create_legacy(fwnode, chip->num_irqs,
878 ®map_domain_ops, d);
880 d->domain = irq_domain_create_linear(fwnode, chip->num_irqs,
881 ®map_domain_ops, d);
883 dev_err(map->dev, "Failed to create IRQ domain\n");
888 ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
889 irq_flags | IRQF_ONESHOT,
892 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
893 irq, chip->name, ret);
902 /* Should really dispose of the domain but... */
905 kfree(d->type_buf_def);
907 kfree(d->mask_buf_def);
909 kfree(d->status_buf);
910 kfree(d->status_reg_buf);
912 for (i = 0; i < chip->num_virt_regs; i++)
913 kfree(d->virt_buf[i]);
919 EXPORT_SYMBOL_GPL(regmap_add_irq_chip_fwnode);
922 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
924 * @map: The regmap for the device.
925 * @irq: The IRQ the device uses to signal interrupts.
926 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
927 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
928 * @chip: Configuration for the interrupt controller.
929 * @data: Runtime data structure for the controller, allocated on success.
931 * Returns 0 on success or an errno on failure.
933 * This is the same as regmap_add_irq_chip_fwnode, except that the firmware
934 * node of the regmap is used.
936 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
937 int irq_base, const struct regmap_irq_chip *chip,
938 struct regmap_irq_chip_data **data)
940 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq,
941 irq_flags, irq_base, chip, data);
943 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
946 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
948 * @irq: Primary IRQ for the device
949 * @d: ®map_irq_chip_data allocated by regmap_add_irq_chip()
951 * This function also disposes of all mapped IRQs on the chip.
953 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
963 /* Dispose all virtual irq from irq domain before removing it */
964 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
965 /* Ignore hwirq if holes in the IRQ list */
966 if (!d->chip->irqs[hwirq].mask)
970 * Find the virtual irq of hwirq on chip and if it is
971 * there then dispose it
973 virq = irq_find_mapping(d->domain, hwirq);
975 irq_dispose_mapping(virq);
978 irq_domain_remove(d->domain);
980 kfree(d->type_buf_def);
982 kfree(d->mask_buf_def);
984 kfree(d->status_reg_buf);
985 kfree(d->status_buf);
988 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
990 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
992 struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
994 regmap_del_irq_chip(d->irq, d);
997 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
1000 struct regmap_irq_chip_data **r = res;
1010 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1012 * @dev: The device pointer on which irq_chip belongs to.
1013 * @fwnode: The firmware node where the IRQ domain should be added to.
1014 * @map: The regmap for the device.
1015 * @irq: The IRQ the device uses to signal interrupts
1016 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1017 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
1018 * @chip: Configuration for the interrupt controller.
1019 * @data: Runtime data structure for the controller, allocated on success
1021 * Returns 0 on success or an errno on failure.
1023 * The ®map_irq_chip_data will be automatically released when the device is
1026 int devm_regmap_add_irq_chip_fwnode(struct device *dev,
1027 struct fwnode_handle *fwnode,
1028 struct regmap *map, int irq,
1029 int irq_flags, int irq_base,
1030 const struct regmap_irq_chip *chip,
1031 struct regmap_irq_chip_data **data)
1033 struct regmap_irq_chip_data **ptr, *d;
1036 ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
1041 ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base,
1049 devres_add(dev, ptr);
1053 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip_fwnode);
1056 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
1058 * @dev: The device pointer on which irq_chip belongs to.
1059 * @map: The regmap for the device.
1060 * @irq: The IRQ the device uses to signal interrupts
1061 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1062 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
1063 * @chip: Configuration for the interrupt controller.
1064 * @data: Runtime data structure for the controller, allocated on success
1066 * Returns 0 on success or an errno on failure.
1068 * The ®map_irq_chip_data will be automatically released when the device is
1071 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
1072 int irq_flags, int irq_base,
1073 const struct regmap_irq_chip *chip,
1074 struct regmap_irq_chip_data **data)
1076 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map,
1077 irq, irq_flags, irq_base, chip,
1080 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
1083 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1085 * @dev: Device for which which resource was allocated.
1086 * @irq: Primary IRQ for the device.
1087 * @data: ®map_irq_chip_data allocated by regmap_add_irq_chip().
1089 * A resource managed version of regmap_del_irq_chip().
1091 void devm_regmap_del_irq_chip(struct device *dev, int irq,
1092 struct regmap_irq_chip_data *data)
1096 WARN_ON(irq != data->irq);
1097 rc = devres_release(dev, devm_regmap_irq_chip_release,
1098 devm_regmap_irq_chip_match, data);
1103 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
1106 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1108 * @data: regmap irq controller to operate on.
1110 * Useful for drivers to request their own IRQs.
1112 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
1114 WARN_ON(!data->irq_base);
1115 return data->irq_base;
1117 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
1120 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1122 * @data: regmap irq controller to operate on.
1123 * @irq: index of the interrupt requested in the chip IRQs.
1125 * Useful for drivers to request their own IRQs.
1127 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
1129 /* Handle holes in the IRQ list */
1130 if (!data->chip->irqs[irq].mask)
1133 return irq_create_mapping(data->domain, irq);
1135 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
1138 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1140 * @data: regmap_irq controller to operate on.
1142 * Useful for drivers to request their own IRQs and for integration
1143 * with subsystems. For ease of integration NULL is accepted as a
1144 * domain, allowing devices to just call this even if no domain is
1147 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
1150 return data->domain;
1154 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);