1 // SPDX-License-Identifier: GPL-2.0
3 // regmap based irq_chip
5 // Copyright 2011 Wolfson Microelectronics plc
7 // Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 #include <linux/device.h>
10 #include <linux/export.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
20 struct regmap_irq_chip_data {
22 struct irq_chip irq_chip;
25 const struct regmap_irq_chip *chip;
28 struct irq_domain *domain;
34 unsigned int *main_status_buf;
35 unsigned int *status_buf;
36 unsigned int *mask_buf;
37 unsigned int *mask_buf_def;
38 unsigned int *wake_buf;
39 unsigned int *type_buf;
40 unsigned int *type_buf_def;
42 unsigned int irq_reg_stride;
43 unsigned int type_reg_stride;
49 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
52 return &data->chip->irqs[irq];
55 static void regmap_irq_lock(struct irq_data *data)
57 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
62 static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
63 unsigned int reg, unsigned int mask,
66 if (d->chip->mask_writeonly)
67 return regmap_write_bits(d->map, reg, mask, val);
69 return regmap_update_bits(d->map, reg, mask, val);
72 static void regmap_irq_sync_unlock(struct irq_data *data)
74 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
75 struct regmap *map = d->map;
81 if (d->chip->runtime_pm) {
82 ret = pm_runtime_get_sync(map->dev);
84 dev_err(map->dev, "IRQ sync failed to resume: %d\n",
88 if (d->clear_status) {
89 for (i = 0; i < d->chip->num_regs; i++) {
90 reg = d->chip->status_base +
91 (i * map->reg_stride * d->irq_reg_stride);
93 ret = regmap_read(map, reg, &val);
96 "Failed to clear the interrupt status bits\n");
99 d->clear_status = false;
103 * If there's been a change in the mask write it back to the
104 * hardware. We rely on the use of the regmap core cache to
105 * suppress pointless writes.
107 for (i = 0; i < d->chip->num_regs; i++) {
108 if (!d->chip->mask_base)
111 reg = d->chip->mask_base +
112 (i * map->reg_stride * d->irq_reg_stride);
113 if (d->chip->mask_invert) {
114 ret = regmap_irq_update_bits(d, reg,
115 d->mask_buf_def[i], ~d->mask_buf[i]);
116 } else if (d->chip->unmask_base) {
117 /* set mask with mask_base register */
118 ret = regmap_irq_update_bits(d, reg,
119 d->mask_buf_def[i], ~d->mask_buf[i]);
122 "Failed to sync unmasks in %x\n",
124 unmask_offset = d->chip->unmask_base -
126 /* clear mask with unmask_base register */
127 ret = regmap_irq_update_bits(d,
132 ret = regmap_irq_update_bits(d, reg,
133 d->mask_buf_def[i], d->mask_buf[i]);
136 dev_err(d->map->dev, "Failed to sync masks in %x\n",
139 reg = d->chip->wake_base +
140 (i * map->reg_stride * d->irq_reg_stride);
142 if (d->chip->wake_invert)
143 ret = regmap_irq_update_bits(d, reg,
147 ret = regmap_irq_update_bits(d, reg,
152 "Failed to sync wakes in %x: %d\n",
156 if (!d->chip->init_ack_masked)
159 * Ack all the masked interrupts unconditionally,
160 * OR if there is masked interrupt which hasn't been Acked,
161 * it'll be ignored in irq handler, then may introduce irq storm
163 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
164 reg = d->chip->ack_base +
165 (i * map->reg_stride * d->irq_reg_stride);
166 /* some chips ack by write 0 */
167 if (d->chip->ack_invert)
168 ret = regmap_write(map, reg, ~d->mask_buf[i]);
170 ret = regmap_write(map, reg, d->mask_buf[i]);
172 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
177 /* Don't update the type bits if we're using mask bits for irq type. */
178 if (!d->chip->type_in_mask) {
179 for (i = 0; i < d->chip->num_type_reg; i++) {
180 if (!d->type_buf_def[i])
182 reg = d->chip->type_base +
183 (i * map->reg_stride * d->type_reg_stride);
184 if (d->chip->type_invert)
185 ret = regmap_irq_update_bits(d, reg,
186 d->type_buf_def[i], ~d->type_buf[i]);
188 ret = regmap_irq_update_bits(d, reg,
189 d->type_buf_def[i], d->type_buf[i]);
191 dev_err(d->map->dev, "Failed to sync type in %x\n",
196 if (d->chip->runtime_pm)
197 pm_runtime_put(map->dev);
199 /* If we've changed our wakeup count propagate it to the parent */
200 if (d->wake_count < 0)
201 for (i = d->wake_count; i < 0; i++)
202 irq_set_irq_wake(d->irq, 0);
203 else if (d->wake_count > 0)
204 for (i = 0; i < d->wake_count; i++)
205 irq_set_irq_wake(d->irq, 1);
209 mutex_unlock(&d->lock);
212 static void regmap_irq_enable(struct irq_data *data)
214 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
215 struct regmap *map = d->map;
216 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
217 unsigned int mask, type;
219 type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
222 * The type_in_mask flag means that the underlying hardware uses
223 * separate mask bits for rising and falling edge interrupts, but
224 * we want to make them into a single virtual interrupt with
227 * If the interrupt we're enabling defines the falling or rising
228 * masks then instead of using the regular mask bits for this
229 * interrupt, use the value previously written to the type buffer
230 * at the corresponding offset in regmap_irq_set_type().
232 if (d->chip->type_in_mask && type)
233 mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
235 mask = irq_data->mask;
237 if (d->chip->clear_on_unmask)
238 d->clear_status = true;
240 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
243 static void regmap_irq_disable(struct irq_data *data)
245 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
246 struct regmap *map = d->map;
247 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
249 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
252 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
254 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
255 struct regmap *map = d->map;
256 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
258 const struct regmap_irq_type *t = &irq_data->type;
260 if ((t->types_supported & type) != type)
263 reg = t->type_reg_offset / map->reg_stride;
265 if (t->type_reg_mask)
266 d->type_buf[reg] &= ~t->type_reg_mask;
268 d->type_buf[reg] &= ~(t->type_falling_val |
270 t->type_level_low_val |
271 t->type_level_high_val);
273 case IRQ_TYPE_EDGE_FALLING:
274 d->type_buf[reg] |= t->type_falling_val;
277 case IRQ_TYPE_EDGE_RISING:
278 d->type_buf[reg] |= t->type_rising_val;
281 case IRQ_TYPE_EDGE_BOTH:
282 d->type_buf[reg] |= (t->type_falling_val |
286 case IRQ_TYPE_LEVEL_HIGH:
287 d->type_buf[reg] |= t->type_level_high_val;
290 case IRQ_TYPE_LEVEL_LOW:
291 d->type_buf[reg] |= t->type_level_low_val;
299 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
301 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
302 struct regmap *map = d->map;
303 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
307 d->wake_buf[irq_data->reg_offset / map->reg_stride]
312 d->wake_buf[irq_data->reg_offset / map->reg_stride]
320 static const struct irq_chip regmap_irq_chip = {
321 .irq_bus_lock = regmap_irq_lock,
322 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
323 .irq_disable = regmap_irq_disable,
324 .irq_enable = regmap_irq_enable,
325 .irq_set_type = regmap_irq_set_type,
326 .irq_set_wake = regmap_irq_set_wake,
329 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
332 const struct regmap_irq_chip *chip = data->chip;
333 struct regmap *map = data->map;
334 struct regmap_irq_sub_irq_map *subreg;
337 if (!chip->sub_reg_offsets) {
338 /* Assume linear mapping */
339 ret = regmap_read(map, chip->status_base +
340 (b * map->reg_stride * data->irq_reg_stride),
341 &data->status_buf[b]);
343 subreg = &chip->sub_reg_offsets[b];
344 for (i = 0; i < subreg->num_regs; i++) {
345 unsigned int offset = subreg->offset[i];
347 ret = regmap_read(map, chip->status_base + offset,
348 &data->status_buf[offset]);
356 static irqreturn_t regmap_irq_thread(int irq, void *d)
358 struct regmap_irq_chip_data *data = d;
359 const struct regmap_irq_chip *chip = data->chip;
360 struct regmap *map = data->map;
362 bool handled = false;
365 if (chip->handle_pre_irq)
366 chip->handle_pre_irq(chip->irq_drv_data);
368 if (chip->runtime_pm) {
369 ret = pm_runtime_get_sync(map->dev);
371 dev_err(map->dev, "IRQ thread failed to resume: %d\n",
378 * Read only registers with active IRQs if the chip has 'main status
379 * register'. Else read in the statuses, using a single bulk read if
380 * possible in order to reduce the I/O overheads.
383 if (chip->num_main_regs) {
384 unsigned int max_main_bits;
387 size = chip->num_regs * sizeof(unsigned int);
389 max_main_bits = (chip->num_main_status_bits) ?
390 chip->num_main_status_bits : chip->num_regs;
391 /* Clear the status buf as we don't read all status regs */
392 memset(data->status_buf, 0, size);
394 /* We could support bulk read for main status registers
395 * but I don't expect to see devices with really many main
396 * status registers so let's only support single reads for the
397 * sake of simplicity. and add bulk reads only if needed
399 for (i = 0; i < chip->num_main_regs; i++) {
400 ret = regmap_read(map, chip->main_status +
402 * data->irq_reg_stride),
403 &data->main_status_buf[i]);
406 "Failed to read IRQ status %d\n",
412 /* Read sub registers with active IRQs */
413 for (i = 0; i < chip->num_main_regs; i++) {
415 const unsigned long mreg = data->main_status_buf[i];
417 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
418 if (i * map->format.val_bytes * 8 + b >
421 ret = read_sub_irq_data(data, b);
425 "Failed to read IRQ status %d\n",
432 } else if (!map->use_single_read && map->reg_stride == 1 &&
433 data->irq_reg_stride == 1) {
435 u8 *buf8 = data->status_reg_buf;
436 u16 *buf16 = data->status_reg_buf;
437 u32 *buf32 = data->status_reg_buf;
439 BUG_ON(!data->status_reg_buf);
441 ret = regmap_bulk_read(map, chip->status_base,
442 data->status_reg_buf,
445 dev_err(map->dev, "Failed to read IRQ status: %d\n",
450 for (i = 0; i < data->chip->num_regs; i++) {
451 switch (map->format.val_bytes) {
453 data->status_buf[i] = buf8[i];
456 data->status_buf[i] = buf16[i];
459 data->status_buf[i] = buf32[i];
468 for (i = 0; i < data->chip->num_regs; i++) {
469 ret = regmap_read(map, chip->status_base +
471 * data->irq_reg_stride),
472 &data->status_buf[i]);
476 "Failed to read IRQ status: %d\n",
484 * Ignore masked IRQs and ack if we need to; we ack early so
485 * there is no race between handling and acknowleding the
486 * interrupt. We assume that typically few of the interrupts
487 * will fire simultaneously so don't worry about overhead from
488 * doing a write per register.
490 for (i = 0; i < data->chip->num_regs; i++) {
491 data->status_buf[i] &= ~data->mask_buf[i];
493 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
494 reg = chip->ack_base +
495 (i * map->reg_stride * data->irq_reg_stride);
496 ret = regmap_write(map, reg, data->status_buf[i]);
498 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
503 for (i = 0; i < chip->num_irqs; i++) {
504 if (data->status_buf[chip->irqs[i].reg_offset /
505 map->reg_stride] & chip->irqs[i].mask) {
506 handle_nested_irq(irq_find_mapping(data->domain, i));
512 if (chip->runtime_pm)
513 pm_runtime_put(map->dev);
515 if (chip->handle_post_irq)
516 chip->handle_post_irq(chip->irq_drv_data);
524 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
527 struct regmap_irq_chip_data *data = h->host_data;
529 irq_set_chip_data(virq, data);
530 irq_set_chip(virq, &data->irq_chip);
531 irq_set_nested_thread(virq, 1);
532 irq_set_parent(virq, data->irq);
533 irq_set_noprobe(virq);
538 static const struct irq_domain_ops regmap_domain_ops = {
539 .map = regmap_irq_map,
540 .xlate = irq_domain_xlate_onetwocell,
544 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
546 * @map: The regmap for the device.
547 * @irq: The IRQ the device uses to signal interrupts.
548 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
549 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
550 * @chip: Configuration for the interrupt controller.
551 * @data: Runtime data structure for the controller, allocated on success.
553 * Returns 0 on success or an errno on failure.
555 * In order for this to be efficient the chip really should use a
556 * register cache. The chip driver is responsible for restoring the
557 * register values used by the IRQ controller over suspend and resume.
559 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
560 int irq_base, const struct regmap_irq_chip *chip,
561 struct regmap_irq_chip_data **data)
563 struct regmap_irq_chip_data *d;
570 if (chip->num_regs <= 0)
573 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
576 for (i = 0; i < chip->num_irqs; i++) {
577 if (chip->irqs[i].reg_offset % map->reg_stride)
579 if (chip->irqs[i].reg_offset / map->reg_stride >=
585 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
587 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
593 d = kzalloc(sizeof(*d), GFP_KERNEL);
597 if (chip->num_main_regs) {
598 d->main_status_buf = kcalloc(chip->num_main_regs,
599 sizeof(unsigned int),
602 if (!d->main_status_buf)
606 d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
611 d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
616 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
618 if (!d->mask_buf_def)
621 if (chip->wake_base) {
622 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
628 num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
630 d->type_buf_def = kcalloc(num_type_reg,
631 sizeof(unsigned int), GFP_KERNEL);
632 if (!d->type_buf_def)
635 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
641 d->irq_chip = regmap_irq_chip;
642 d->irq_chip.name = chip->name;
646 d->irq_base = irq_base;
648 if (chip->irq_reg_stride)
649 d->irq_reg_stride = chip->irq_reg_stride;
651 d->irq_reg_stride = 1;
653 if (chip->type_reg_stride)
654 d->type_reg_stride = chip->type_reg_stride;
656 d->type_reg_stride = 1;
658 if (!map->use_single_read && map->reg_stride == 1 &&
659 d->irq_reg_stride == 1) {
660 d->status_reg_buf = kmalloc_array(chip->num_regs,
661 map->format.val_bytes,
663 if (!d->status_reg_buf)
667 mutex_init(&d->lock);
669 for (i = 0; i < chip->num_irqs; i++)
670 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
671 |= chip->irqs[i].mask;
673 /* Mask all the interrupts by default */
674 for (i = 0; i < chip->num_regs; i++) {
675 d->mask_buf[i] = d->mask_buf_def[i];
676 if (!chip->mask_base)
679 reg = chip->mask_base +
680 (i * map->reg_stride * d->irq_reg_stride);
681 if (chip->mask_invert)
682 ret = regmap_irq_update_bits(d, reg,
683 d->mask_buf[i], ~d->mask_buf[i]);
684 else if (d->chip->unmask_base) {
685 unmask_offset = d->chip->unmask_base -
687 ret = regmap_irq_update_bits(d,
692 ret = regmap_irq_update_bits(d, reg,
693 d->mask_buf[i], d->mask_buf[i]);
695 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
700 if (!chip->init_ack_masked)
703 /* Ack masked but set interrupts */
704 reg = chip->status_base +
705 (i * map->reg_stride * d->irq_reg_stride);
706 ret = regmap_read(map, reg, &d->status_buf[i]);
708 dev_err(map->dev, "Failed to read IRQ status: %d\n",
713 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
714 reg = chip->ack_base +
715 (i * map->reg_stride * d->irq_reg_stride);
716 if (chip->ack_invert)
717 ret = regmap_write(map, reg,
718 ~(d->status_buf[i] & d->mask_buf[i]));
720 ret = regmap_write(map, reg,
721 d->status_buf[i] & d->mask_buf[i]);
723 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
730 /* Wake is disabled by default */
732 for (i = 0; i < chip->num_regs; i++) {
733 d->wake_buf[i] = d->mask_buf_def[i];
734 reg = chip->wake_base +
735 (i * map->reg_stride * d->irq_reg_stride);
737 if (chip->wake_invert)
738 ret = regmap_irq_update_bits(d, reg,
742 ret = regmap_irq_update_bits(d, reg,
746 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
753 if (chip->num_type_reg && !chip->type_in_mask) {
754 for (i = 0; i < chip->num_type_reg; ++i) {
755 reg = chip->type_base +
756 (i * map->reg_stride * d->type_reg_stride);
758 ret = regmap_read(map, reg, &d->type_buf_def[i]);
760 if (d->chip->type_invert)
761 d->type_buf_def[i] = ~d->type_buf_def[i];
764 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
772 d->domain = irq_domain_add_legacy(map->dev->of_node,
773 chip->num_irqs, irq_base, 0,
774 ®map_domain_ops, d);
776 d->domain = irq_domain_add_linear(map->dev->of_node,
778 ®map_domain_ops, d);
780 dev_err(map->dev, "Failed to create IRQ domain\n");
785 ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
786 irq_flags | IRQF_ONESHOT,
789 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
790 irq, chip->name, ret);
799 /* Should really dispose of the domain but... */
802 kfree(d->type_buf_def);
804 kfree(d->mask_buf_def);
806 kfree(d->status_buf);
807 kfree(d->status_reg_buf);
811 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
814 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
816 * @irq: Primary IRQ for the device
817 * @d: ®map_irq_chip_data allocated by regmap_add_irq_chip()
819 * This function also disposes of all mapped IRQs on the chip.
821 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
831 /* Dispose all virtual irq from irq domain before removing it */
832 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
833 /* Ignore hwirq if holes in the IRQ list */
834 if (!d->chip->irqs[hwirq].mask)
838 * Find the virtual irq of hwirq on chip and if it is
839 * there then dispose it
841 virq = irq_find_mapping(d->domain, hwirq);
843 irq_dispose_mapping(virq);
846 irq_domain_remove(d->domain);
848 kfree(d->type_buf_def);
850 kfree(d->mask_buf_def);
852 kfree(d->status_reg_buf);
853 kfree(d->status_buf);
856 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
858 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
860 struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
862 regmap_del_irq_chip(d->irq, d);
865 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
868 struct regmap_irq_chip_data **r = res;
878 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
880 * @dev: The device pointer on which irq_chip belongs to.
881 * @map: The regmap for the device.
882 * @irq: The IRQ the device uses to signal interrupts
883 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
884 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
885 * @chip: Configuration for the interrupt controller.
886 * @data: Runtime data structure for the controller, allocated on success
888 * Returns 0 on success or an errno on failure.
890 * The ®map_irq_chip_data will be automatically released when the device is
893 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
894 int irq_flags, int irq_base,
895 const struct regmap_irq_chip *chip,
896 struct regmap_irq_chip_data **data)
898 struct regmap_irq_chip_data **ptr, *d;
901 ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
906 ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
914 devres_add(dev, ptr);
918 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
921 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
923 * @dev: Device for which which resource was allocated.
924 * @irq: Primary IRQ for the device.
925 * @data: ®map_irq_chip_data allocated by regmap_add_irq_chip().
927 * A resource managed version of regmap_del_irq_chip().
929 void devm_regmap_del_irq_chip(struct device *dev, int irq,
930 struct regmap_irq_chip_data *data)
934 WARN_ON(irq != data->irq);
935 rc = devres_release(dev, devm_regmap_irq_chip_release,
936 devm_regmap_irq_chip_match, data);
941 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
944 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
946 * @data: regmap irq controller to operate on.
948 * Useful for drivers to request their own IRQs.
950 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
952 WARN_ON(!data->irq_base);
953 return data->irq_base;
955 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
958 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
960 * @data: regmap irq controller to operate on.
961 * @irq: index of the interrupt requested in the chip IRQs.
963 * Useful for drivers to request their own IRQs.
965 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
967 /* Handle holes in the IRQ list */
968 if (!data->chip->irqs[irq].mask)
971 return irq_create_mapping(data->domain, irq);
973 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
976 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
978 * @data: regmap_irq controller to operate on.
980 * Useful for drivers to request their own IRQs and for integration
981 * with subsystems. For ease of integration NULL is accepted as a
982 * domain, allowing devices to just call this even if no domain is
985 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
992 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);