1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Header file for the nicstar device driver.
7 * Author: Rui Prior (rprior@inescn.pt)
8 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
13 #ifndef _LINUX_NICSTAR_H_
14 #define _LINUX_NICSTAR_H_
18 #include <linux/types.h>
19 #include <linux/pci.h>
20 #include <linux/idr.h>
21 #include <linux/uio.h>
22 #include <linux/skbuff.h>
23 #include <linux/atmdev.h>
24 #include <linux/atm_nicstar.h>
28 #define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards
29 controlled by the device driver. Must
32 #undef RCQ_SUPPORT /* Do not define this for now */
34 #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
35 #define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */
37 #define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */
38 #define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */
39 #define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */
40 #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
42 #define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384.
43 Define 4096 only if (all) your card(s)
44 have 32K x 32bit SRAM, in which case
45 setting this to 16384 will just waste a
47 Setting this to 4096 for a card with
48 128K x 32bit SRAM will limit the maximum
51 /*#define NS_PCI_LATENCY 64*//* Must be a multiple of 32 */
53 /* Number of buffers initially allocated */
54 #define NUM_SB 32 /* Must be even */
55 #define NUM_LB 24 /* Must be even */
56 #define NUM_HB 8 /* Pre-allocated huge buffers */
57 #define NUM_IOVB 48 /* Iovec buffers */
59 /* Lower level for count of buffers */
60 #define MIN_SB 8 /* Must be even */
61 #define MIN_LB 8 /* Must be even */
65 /* Upper level for count of buffers */
66 #define MAX_SB 64 /* Must be even, <= 508 */
67 #define MAX_LB 48 /* Must be even, <= 508 */
71 /* These are the absolute maximum allowed for the ioctl() */
72 #define TOP_SB 256 /* Must be even, <= 508 */
73 #define TOP_LB 128 /* Must be even, <= 508 */
77 #define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */
78 #define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */
82 #define SCQFULL_TIMEOUT (5 * HZ)
84 #define NS_POLL_PERIOD (HZ)
86 #define PCR_TOLERANCE (1.0001)
90 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
91 #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
95 #define NS_IOREMAP_SIZE 4096
98 * BUF_XX distinguish the Rx buffers depending on their (small/large) size.
99 * BUG_SM and BUG_LG are both used by the driver and the device.
100 * BUF_NONE is only used by the driver.
102 #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
103 #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
104 #define BUF_NONE 0xffffffff /* Software only: */
106 #define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */
107 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
108 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
109 #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
111 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
112 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
114 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
116 #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
117 #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
119 /* NICStAR structures located in host memory */
122 * RSQ - Receive Status Queue
124 * Written by the NICStAR, read by the device driver.
127 typedef struct ns_rsqe {
130 u32 final_aal5_crc32;
134 #define ns_rsqe_vpi(ns_rsqep) \
135 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
136 #define ns_rsqe_vci(ns_rsqep) \
137 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
139 #define NS_RSQE_VALID 0x80000000
140 #define NS_RSQE_NZGFC 0x00004000
141 #define NS_RSQE_EOPDU 0x00002000
142 #define NS_RSQE_BUFSIZE 0x00001000
143 #define NS_RSQE_CONGESTION 0x00000800
144 #define NS_RSQE_CLP 0x00000400
145 #define NS_RSQE_CRCERR 0x00000200
147 #define NS_RSQE_BUFSIZE_SM 0x00000000
148 #define NS_RSQE_BUFSIZE_LG 0x00001000
150 #define ns_rsqe_valid(ns_rsqep) \
151 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
152 #define ns_rsqe_nzgfc(ns_rsqep) \
153 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
154 #define ns_rsqe_eopdu(ns_rsqep) \
155 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
156 #define ns_rsqe_bufsize(ns_rsqep) \
157 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
158 #define ns_rsqe_congestion(ns_rsqep) \
159 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
160 #define ns_rsqe_clp(ns_rsqep) \
161 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
162 #define ns_rsqe_crcerr(ns_rsqep) \
163 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
165 #define ns_rsqe_cellcount(ns_rsqep) \
166 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
167 #define ns_rsqe_init(ns_rsqep) \
168 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
170 #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
171 #define NS_RSQ_ALIGNMENT NS_RSQSIZE
174 * RCQ - Raw Cell Queue
176 * Written by the NICStAR, read by the device driver.
179 typedef struct cell_payload {
183 typedef struct ns_rcqe {
188 cell_payload payload;
191 #define NS_RCQE_SIZE 64 /* bytes */
193 #define ns_rcqe_islast(ns_rcqep) \
194 (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
195 #define ns_rcqe_cellheader(ns_rcqep) \
196 (le32_to_cpu((ns_rcqep)->word_1))
197 #define ns_rcqe_nextbufhandle(ns_rcqep) \
198 (le32_to_cpu((ns_rcqep)->word_2))
201 * SCQ - Segmentation Channel Queue
203 * Written by the device driver, read by the NICStAR.
206 typedef struct ns_scqe {
213 /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
214 or TSR (Transmit Status Requests) */
216 #define NS_SCQE_TYPE_TBD 0x00000000
217 #define NS_SCQE_TYPE_TSR 0x80000000
219 #define NS_TBD_EOPDU 0x40000000
220 #define NS_TBD_AAL0 0x00000000
221 #define NS_TBD_AAL34 0x04000000
222 #define NS_TBD_AAL5 0x08000000
224 #define NS_TBD_VPI_MASK 0x0FF00000
225 #define NS_TBD_VCI_MASK 0x000FFFF0
226 #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
228 #define NS_TBD_VPI_SHIFT 20
229 #define NS_TBD_VCI_SHIFT 4
231 #define ns_tbd_mkword_1(flags, m, n, buflen) \
232 (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
233 #define ns_tbd_mkword_1_novbr(flags, buflen) \
234 (cpu_to_le32((flags) | (buflen) | 0x00810000))
235 #define ns_tbd_mkword_3(control, pdulen) \
236 (cpu_to_le32((control) << 16 | (pdulen)))
237 #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
238 (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
240 #define NS_TSR_INTENABLE 0x20000000
242 #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */
244 #define ns_tsr_mkword_1(flags) \
245 (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
246 #define ns_tsr_mkword_2(scdi, scqi) \
247 (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
249 #define ns_scqe_is_tsr(ns_scqep) \
250 (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
252 #define VBR_SCQ_NUM_ENTRIES 512
253 #define VBR_SCQSIZE 8192
254 #define CBR_SCQ_NUM_ENTRIES 64
255 #define CBR_SCQSIZE 1024
257 #define NS_SCQE_SIZE 16
260 * TSQ - Transmit Status Queue
262 * Written by the NICStAR, read by the device driver.
265 typedef struct ns_tsi {
270 /* NOTE: The first word can be a status word copied from the TSR which
271 originated the TSI, or a timer overflow indicator. In this last
272 case, the value of the first word is all zeroes. */
274 #define NS_TSI_EMPTY 0x80000000
275 #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
277 #define ns_tsi_isempty(ns_tsip) \
278 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
279 #define ns_tsi_gettimestamp(ns_tsip) \
280 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
282 #define ns_tsi_init(ns_tsip) \
283 ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
285 #define NS_TSQSIZE 8192
286 #define NS_TSQ_NUM_ENTRIES 1024
287 #define NS_TSQ_ALIGNMENT 8192
289 #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
291 #define ns_tsi_tmrof(ns_tsip) \
292 (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
293 #define ns_tsi_getscdindex(ns_tsip) \
294 ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
295 #define ns_tsi_getscqpos(ns_tsip) \
296 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
298 /* NICStAR structures located in local SRAM */
301 * RCT - Receive Connection Table
303 * Written by both the NICStAR and the device driver.
306 typedef struct ns_rcte {
313 #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */
314 #define NS_RCTE_NZGFC 0x00100000
315 #define NS_RCTE_CONNECTOPEN 0x00080000
316 #define NS_RCTE_AALMASK 0x00070000
317 #define NS_RCTE_AAL0 0x00000000
318 #define NS_RCTE_AAL34 0x00010000
319 #define NS_RCTE_AAL5 0x00020000
320 #define NS_RCTE_RCQ 0x00030000
321 #define NS_RCTE_RAWCELLINTEN 0x00008000
322 #define NS_RCTE_RXCONSTCELLADDR 0x00004000
323 #define NS_RCTE_BUFFVALID 0x00002000
324 #define NS_RCTE_FBDSIZE 0x00001000
325 #define NS_RCTE_EFCI 0x00000800
326 #define NS_RCTE_CLP 0x00000400
327 #define NS_RCTE_CRCERROR 0x00000200
328 #define NS_RCTE_CELLCOUNT_MASK 0x000001FF
330 #define NS_RCTE_FBDSIZE_SM 0x00000000
331 #define NS_RCTE_FBDSIZE_LG 0x00001000
333 #define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */
335 /* NOTE: We could make macros to contruct the first word of the RCTE,
336 but that doesn't seem to make much sense... */
339 * FBD - Free Buffer Descriptor
341 * Written by the device driver using via the command register.
344 typedef struct ns_fbd {
350 * TST - Transmit Schedule Table
352 * Written by the device driver.
357 #define NS_TST_OPCODE_MASK 0x60000000
359 #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
360 #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
361 #define NS_TST_OPCODE_VARIABLE 0x40000000
362 #define NS_TST_OPCODE_END 0x60000000 /* Jump */
364 #define ns_tste_make(opcode, sramad) (opcode | sramad)
368 - When the opcode is FIXED, sramad specifies the SRAM address of the
369 SCD for that fixed rate channel.
370 - When the opcode is END, sramad specifies the SRAM address of the
371 location of the next TST entry to read.
375 * SCD - Segmentation Channel Descriptor
377 * Written by both the device driver and the NICStAR
380 typedef struct ns_scd {
383 u32 partial_aal5_crc;
389 #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
390 #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
391 #define NS_SCD_TAIL_MASK_VAR 0x00001FF0
392 #define NS_SCD_TAIL_MASK_FIX 0x000003F0
393 #define NS_SCD_HEAD_MASK_VAR 0x00001FF0
394 #define NS_SCD_HEAD_MASK_FIX 0x000003F0
395 #define NS_SCD_XMITFOREVER 0x02000000
397 /* NOTE: There are other fields in word 2 of the SCD, but as they should
398 not be needed in the device driver they are not defined here. */
400 /* NICStAR local SRAM memory map */
402 #define NS_RCT 0x00000
403 #define NS_RCT_32_END 0x03FFF
404 #define NS_RCT_128_END 0x0FFFF
405 #define NS_UNUSED_32 0x04000
406 #define NS_UNUSED_128 0x10000
407 #define NS_UNUSED_END 0x1BFFF
408 #define NS_TST_FRSCD 0x1C000
409 #define NS_TST_FRSCD_END 0x1E7DB
410 #define NS_VRSCD2 0x1E7DC
411 #define NS_VRSCD2_END 0x1E7E7
412 #define NS_VRSCD1 0x1E7E8
413 #define NS_VRSCD1_END 0x1E7F3
414 #define NS_VRSCD0 0x1E7F4
415 #define NS_VRSCD0_END 0x1E7FF
416 #define NS_RXFIFO 0x1E800
417 #define NS_RXFIFO_END 0x1F7FF
418 #define NS_SMFBQ 0x1F800
419 #define NS_SMFBQ_END 0x1FBFF
420 #define NS_LGFBQ 0x1FC00
421 #define NS_LGFBQ_END 0x1FFFF
423 /* NISCtAR operation registers */
425 /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
428 DR0 = 0x00, /* Data Register 0 R/W */
429 DR1 = 0x04, /* Data Register 1 W */
430 DR2 = 0x08, /* Data Register 2 W */
431 DR3 = 0x0C, /* Data Register 3 W */
432 CMD = 0x10, /* Command W */
433 CFG = 0x14, /* Configuration R/W */
434 STAT = 0x18, /* Status R/W */
435 RSQB = 0x1C, /* Receive Status Queue Base W */
436 RSQT = 0x20, /* Receive Status Queue Tail R */
437 RSQH = 0x24, /* Receive Status Queue Head W */
438 CDC = 0x28, /* Cell Drop Counter R/clear */
439 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
440 ICC = 0x30, /* Invalid Cell Count R/clear */
441 RAWCT = 0x34, /* Raw Cell Tail R */
442 TMR = 0x38, /* Timer R */
443 TSTB = 0x3C, /* Transmit Schedule Table Base R/W */
444 TSQB = 0x40, /* Transmit Status Queue Base W */
445 TSQT = 0x44, /* Transmit Status Queue Tail R */
446 TSQH = 0x48, /* Transmit Status Queue Head W */
447 GP = 0x4C, /* General Purpose R/W */
448 VPM = 0x50 /* VPI/VCI Mask W */
451 /* NICStAR commands issued to the CMD register */
453 /* Top 4 bits are command opcode, lower 28 are parameters. */
455 #define NS_CMD_NO_OPERATION 0x00000000
456 /* params always 0 */
458 #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
459 /* b19{1=open,0=close} b18-2{SRAM addr} */
461 #define NS_CMD_WRITE_SRAM 0x40000000
462 /* b18-2{SRAM addr} b1-0{burst size} */
464 #define NS_CMD_READ_SRAM 0x50000000
465 /* b18-2{SRAM addr} */
467 #define NS_CMD_WRITE_FREEBUFQ 0x60000000
468 /* b0{large buf indicator} */
470 #define NS_CMD_READ_UTILITY 0x80000000
471 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
473 #define NS_CMD_WRITE_UTILITY 0x90000000
474 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
476 #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
477 #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
479 /* NICStAR configuration bits */
481 #define NS_CFG_SWRST 0x80000000 /* Software Reset */
482 #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */
483 #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */
484 #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */
485 #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue
487 #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */
488 #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
489 #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */
490 #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */
491 #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */
492 #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
493 #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt
495 #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
496 #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full
498 #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */
499 #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt
501 #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
502 #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt
504 #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
506 #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
507 #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full
509 #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
511 #define NS_CFG_SMBUFSIZE_48 0x00000000
512 #define NS_CFG_SMBUFSIZE_96 0x08000000
513 #define NS_CFG_SMBUFSIZE_240 0x10000000
514 #define NS_CFG_SMBUFSIZE_2048 0x18000000
516 #define NS_CFG_LGBUFSIZE_2048 0x00000000
517 #define NS_CFG_LGBUFSIZE_4096 0x02000000
518 #define NS_CFG_LGBUFSIZE_8192 0x04000000
519 #define NS_CFG_LGBUFSIZE_16384 0x06000000
521 #define NS_CFG_RSQSIZE_2048 0x00000000
522 #define NS_CFG_RSQSIZE_4096 0x00400000
523 #define NS_CFG_RSQSIZE_8192 0x00800000
525 #define NS_CFG_VPIBITS_0 0x00000000
526 #define NS_CFG_VPIBITS_1 0x00040000
527 #define NS_CFG_VPIBITS_2 0x00080000
528 #define NS_CFG_VPIBITS_8 0x000C0000
530 #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000
531 #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000
532 #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
534 #define NS_CFG_RXINT_NOINT 0x00000000
535 #define NS_CFG_RXINT_NODELAY 0x00001000
536 #define NS_CFG_RXINT_314US 0x00002000
537 #define NS_CFG_RXINT_624US 0x00003000
538 #define NS_CFG_RXINT_899US 0x00004000
540 /* NICStAR STATus bits */
542 #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
543 #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
544 #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */
545 #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */
546 #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */
547 #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */
548 #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */
549 #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */
550 #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */
551 #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */
552 #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */
553 #define NS_STAT_EOPDU 0x00000020 /* End of PDU */
554 #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
555 #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */
556 #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */
557 #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
559 #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
560 #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
562 /* #defines which depend on other #defines */
564 #define NS_TST0 NS_TST_FRSCD
565 #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
567 #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
568 #define NS_FRSCD_SIZE 12 /* 12 dwords */
569 #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
571 #if (NS_SMBUFSIZE == 48)
572 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
573 #elif (NS_SMBUFSIZE == 96)
574 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
575 #elif (NS_SMBUFSIZE == 240)
576 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
577 #elif (NS_SMBUFSIZE == 2048)
578 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
580 #error NS_SMBUFSIZE is incorrect in nicstar.h
581 #endif /* NS_SMBUFSIZE */
583 #if (NS_LGBUFSIZE == 2048)
584 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
585 #elif (NS_LGBUFSIZE == 4096)
586 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
587 #elif (NS_LGBUFSIZE == 8192)
588 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
589 #elif (NS_LGBUFSIZE == 16384)
590 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
592 #error NS_LGBUFSIZE is incorrect in nicstar.h
593 #endif /* NS_LGBUFSIZE */
595 #if (NS_RSQSIZE == 2048)
596 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
597 #elif (NS_RSQSIZE == 4096)
598 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
599 #elif (NS_RSQSIZE == 8192)
600 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
602 #error NS_RSQSIZE is incorrect in nicstar.h
603 #endif /* NS_RSQSIZE */
605 #if (NS_VPIBITS == 0)
606 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
607 #elif (NS_VPIBITS == 1)
608 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
609 #elif (NS_VPIBITS == 2)
610 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
611 #elif (NS_VPIBITS == 8)
612 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
614 #error NS_VPIBITS is incorrect in nicstar.h
615 #endif /* NS_VPIBITS */
618 #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
620 #define NS_CFG_RAWIE_OPT 0x00000000
621 #endif /* RCQ_SUPPORT */
624 #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
626 #define NS_CFG_TSQFIE_OPT 0x00000000
627 #endif /* ENABLE_TSQFIE */
631 #ifndef PCI_VENDOR_ID_IDT
632 #define PCI_VENDOR_ID_IDT 0x111D
633 #endif /* PCI_VENDOR_ID_IDT */
635 #ifndef PCI_DEVICE_ID_IDT_IDT77201
636 #define PCI_DEVICE_ID_IDT_IDT77201 0x0001
637 #endif /* PCI_DEVICE_ID_IDT_IDT77201 */
639 /* Device driver structures */
642 u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */
647 #define NS_PRV_BUFTYPE(skb) \
648 (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->buf_type)
649 #define NS_PRV_DMA(skb) \
650 (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->dma)
651 #define NS_PRV_IOVCNT(skb) \
652 (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->iovcnt)
654 typedef struct tsq_info {
662 typedef struct scq_info {
668 volatile ns_scqe *tail; /* Not related to the nicstar register */
669 unsigned num_entries;
670 struct sk_buff **skb; /* Pointer to an array of pointers
671 to the sk_buffs used for tx */
672 u32 scd; /* SRAM address of the corresponding
674 int tbd_count; /* Only meaningful on variable rate */
675 wait_queue_head_t scqfull_waitq;
676 volatile char full; /* SCQ full indicator */
677 spinlock_t lock; /* SCQ spinlock */
680 typedef struct rsq_info {
688 typedef struct skb_pool {
689 volatile int count; /* number of buffers in the queue */
690 struct sk_buff_head queue;
693 /* NOTE: for small and large buffer pools, the count is not used, as the
694 actual value used for buffer management is the one read from the
697 typedef struct vc_map {
698 volatile unsigned int tx:1; /* TX vc? */
699 volatile unsigned int rx:1; /* RX vc? */
700 struct atm_vcc *tx_vcc, *rx_vcc;
701 struct sk_buff *rx_iov; /* RX iovector skb */
702 scq_info *scq; /* To keep track of the SCQ */
703 u32 cbr_scd; /* SRAM address of the corresponding
704 SCD. 0x00000000 for UBR/VBR/ABR */
708 typedef struct ns_dev {
709 int index; /* Card ID to the device driver */
710 int sram_size; /* In k x 32bit words. 32 or 128 */
711 void __iomem *membase; /* Card's memory base address */
712 unsigned long max_pcr;
713 int rct_size; /* Number of entries */
716 struct pci_dev *pcidev;
718 struct atm_dev *atmdev;
721 scq_info *scq0, *scq1, *scq2; /* VBR SCQs */
722 skb_pool sbpool; /* Small buffers */
723 skb_pool lbpool; /* Large buffers */
724 skb_pool hbpool; /* Pre-allocated huge buffers */
725 skb_pool iovpool; /* iovector buffers */
726 volatile int efbie; /* Empty free buf. queue int. enabled */
727 volatile u32 tst_addr; /* SRAM address of the TST in use */
728 volatile int tst_free_entries;
729 vc_map vcmap[NS_MAX_RCTSIZE];
730 vc_map *tste2vc[NS_TST_NUM_ENTRIES];
731 vc_map *scd2vc[NS_FRSCD_NUM];
738 struct sk_buff *sm_handle;
740 struct sk_buff *lg_handle;
742 struct sk_buff *rcbuf; /* Current raw cell buffer */
743 struct ns_rcqe *rawcell;
744 u32 rawch; /* Raw cell queue head */
745 unsigned intcnt; /* Interrupt counter */
746 spinlock_t int_lock; /* Interrupt lock */
747 spinlock_t res_lock; /* Card resource lock */
750 /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
751 CBR vc. If the entry is not allocated, it must be NULL.
753 There are two TSTs so the driver can modify them on the fly
754 without stopping the transmission.
756 scd2vc allows us to find out unused fixed rate SCDs, because
757 they must have a NULL pointer here. */
759 #endif /* _LINUX_NICSTAR_H_ */