1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/ata/sata_dwc_460ex.c
5 * Synopsys DesignWare Cores (DWC) SATA host driver
7 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
9 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
10 * Copyright 2008 DENX Software Engineering
12 * Based on versions provided by AMCC and Synopsys which are:
13 * Copyright 2006 Applied Micro Circuits Corporation
14 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
17 #ifdef CONFIG_SATA_DWC_DEBUG
21 #ifdef CONFIG_SATA_DWC_VDEBUG
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/dmaengine.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/phy/phy.h>
34 #include <linux/libata.h>
35 #include <linux/slab.h>
36 #include <trace/events/libata.h>
40 #include <scsi/scsi_host.h>
41 #include <scsi/scsi_cmnd.h>
43 /* These two are defined in "libata.h" */
47 #define DRV_NAME "sata-dwc"
48 #define DRV_VERSION "1.3"
50 #define sata_dwc_writel(a, v) writel_relaxed(v, a)
51 #define sata_dwc_readl(a) readl_relaxed(a)
57 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
60 SATA_DWC_MAX_PORTS = 1,
62 SATA_DWC_SCR_OFFSET = 0x24,
63 SATA_DWC_REG_OFFSET = 0x64,
66 /* DWC SATA Registers */
67 struct sata_dwc_regs {
68 u32 fptagr; /* 1st party DMA tag */
69 u32 fpbor; /* 1st party DMA buffer offset */
70 u32 fptcr; /* 1st party DMA Xfr count */
71 u32 dmacr; /* DMA Control */
72 u32 dbtsr; /* DMA Burst Transac size */
73 u32 intpr; /* Interrupt Pending */
74 u32 intmr; /* Interrupt Mask */
75 u32 errmr; /* Error Mask */
76 u32 llcr; /* Link Layer Control */
77 u32 phycr; /* PHY Control */
78 u32 physr; /* PHY Status */
79 u32 rxbistpd; /* Recvd BIST pattern def register */
80 u32 rxbistpd1; /* Recvd BIST data dword1 */
81 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
82 u32 txbistpd; /* Trans BIST pattern def register */
83 u32 txbistpd1; /* Trans BIST data dword1 */
84 u32 txbistpd2; /* Trans BIST data dword2 */
85 u32 bistcr; /* BIST Control Register */
86 u32 bistfctr; /* BIST FIS Count Register */
87 u32 bistsr; /* BIST Status Register */
88 u32 bistdecr; /* BIST Dword Error count register */
89 u32 res[15]; /* Reserved locations */
90 u32 testr; /* Test Register */
91 u32 versionr; /* Version Register */
92 u32 idr; /* ID Register */
93 u32 unimpl[192]; /* Unimplemented */
94 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
98 SCR_SCONTROL_DET_ENABLE = 0x00000001,
99 SCR_SSTATUS_DET_PRESENT = 0x00000001,
100 SCR_SERROR_DIAG_X = 0x04000000,
101 /* DWC SATA Register Operations */
102 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
103 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
104 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
105 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
106 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
107 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
108 SATA_DWC_INTPR_DMAT = 0x00000001,
109 SATA_DWC_INTPR_NEWFP = 0x00000002,
110 SATA_DWC_INTPR_PMABRT = 0x00000004,
111 SATA_DWC_INTPR_ERR = 0x00000008,
112 SATA_DWC_INTPR_NEWBIST = 0x00000010,
113 SATA_DWC_INTPR_IPF = 0x10000000,
114 SATA_DWC_INTMR_DMATM = 0x00000001,
115 SATA_DWC_INTMR_NEWFPM = 0x00000002,
116 SATA_DWC_INTMR_PMABRTM = 0x00000004,
117 SATA_DWC_INTMR_ERRM = 0x00000008,
118 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
119 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
120 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
121 SATA_DWC_LLCR_RPDEN = 0x00000004,
122 /* This is all error bits, zero's are reserved fields. */
123 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
126 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
127 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
128 SATA_DWC_DMACR_TMOD_TXCHEN)
129 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
130 SATA_DWC_DMACR_TMOD_TXCHEN)
131 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
132 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
134 struct sata_dwc_device {
135 struct device *dev; /* generic device struct */
136 struct ata_probe_ent *pe; /* ptr to probe-ent */
137 struct ata_host *host;
138 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
143 #ifdef CONFIG_SATA_DWC_OLD_DMA
144 struct dw_dma_chip *dma;
148 #define SATA_DWC_QCMD_MAX 32
150 struct sata_dwc_device_port {
151 struct sata_dwc_device *hsdev;
152 int cmd_issued[SATA_DWC_QCMD_MAX];
153 int dma_pending[SATA_DWC_QCMD_MAX];
156 struct dma_chan *chan;
157 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
158 u32 dma_interrupt_count;
162 * Commonly used DWC SATA driver macros
164 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
165 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
166 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
167 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
168 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
171 SATA_DWC_CMD_ISSUED_NOT = 0,
172 SATA_DWC_CMD_ISSUED_PEND = 1,
173 SATA_DWC_CMD_ISSUED_EXEC = 2,
174 SATA_DWC_CMD_ISSUED_NODATA = 3,
176 SATA_DWC_DMA_PENDING_NONE = 0,
177 SATA_DWC_DMA_PENDING_TX = 1,
178 SATA_DWC_DMA_PENDING_RX = 2,
184 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
185 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
187 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
188 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
190 #ifdef CONFIG_SATA_DWC_OLD_DMA
192 #include <linux/platform_data/dma-dw.h>
193 #include <linux/dma/dw.h>
195 static struct dw_dma_slave sata_dwc_dma_dws = {
202 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
204 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
206 if (dws->dma_dev != chan->device->dev)
213 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
215 struct sata_dwc_device *hsdev = hsdevp->hsdev;
216 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
217 struct device *dev = hsdev->dev;
223 dma_cap_set(DMA_SLAVE, mask);
225 /* Acquire DMA channel */
226 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
228 dev_err(dev, "%s: dma channel unavailable\n", __func__);
235 static int sata_dwc_dma_init_old(struct platform_device *pdev,
236 struct sata_dwc_device *hsdev)
238 struct device *dev = &pdev->dev;
239 struct device_node *np = dev->of_node;
241 hsdev->dma = devm_kzalloc(dev, sizeof(*hsdev->dma), GFP_KERNEL);
245 hsdev->dma->dev = dev;
246 hsdev->dma->id = pdev->id;
248 /* Get SATA DMA interrupt number */
249 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
250 if (hsdev->dma->irq == NO_IRQ) {
251 dev_err(dev, "no SATA DMA irq\n");
255 /* Get physical SATA DMA register base address */
256 hsdev->dma->regs = devm_platform_ioremap_resource(pdev, 1);
257 if (IS_ERR(hsdev->dma->regs))
258 return PTR_ERR(hsdev->dma->regs);
260 /* Initialize AHB DMAC */
261 return dw_dma_probe(hsdev->dma);
264 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
269 dw_dma_remove(hsdev->dma);
274 static const char *get_prot_descript(u8 protocol)
277 case ATA_PROT_NODATA:
278 return "ATA no data";
285 case ATA_PROT_NCQ_NODATA:
286 return "ATA NCQ no data";
287 case ATAPI_PROT_NODATA:
288 return "ATAPI no data";
298 static void dma_dwc_xfer_done(void *hsdev_instance)
301 struct sata_dwc_device *hsdev = hsdev_instance;
302 struct ata_host *host = (struct ata_host *)hsdev->host;
304 struct sata_dwc_device_port *hsdevp;
306 unsigned int port = 0;
308 spin_lock_irqsave(&host->lock, flags);
309 ap = host->ports[port];
310 hsdevp = HSDEVP_FROM_AP(ap);
311 tag = ap->link.active_tag;
314 * Each DMA command produces 2 interrupts. Only
315 * complete the command after both interrupts have been
316 * seen. (See sata_dwc_isr())
318 hsdevp->dma_interrupt_count++;
319 sata_dwc_clear_dmacr(hsdevp, tag);
321 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
322 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
323 tag, hsdevp->dma_pending[tag]);
326 if ((hsdevp->dma_interrupt_count % 2) == 0)
327 sata_dwc_dma_xfer_complete(ap, 1);
329 spin_unlock_irqrestore(&host->lock, flags);
332 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
334 struct ata_port *ap = qc->ap;
335 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
336 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
337 struct dma_slave_config sconf;
338 struct dma_async_tx_descriptor *desc;
340 if (qc->dma_dir == DMA_DEV_TO_MEM) {
341 sconf.src_addr = hsdev->dmadr;
342 sconf.device_fc = false;
343 } else { /* DMA_MEM_TO_DEV */
344 sconf.dst_addr = hsdev->dmadr;
345 sconf.device_fc = false;
348 sconf.direction = qc->dma_dir;
349 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
350 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
351 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
352 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
354 dmaengine_slave_config(hsdevp->chan, &sconf);
356 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
357 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
359 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
364 desc->callback = dma_dwc_xfer_done;
365 desc->callback_param = hsdev;
367 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
368 qc->sg, qc->n_elem, &hsdev->dmadr);
373 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
375 if (scr > SCR_NOTIFICATION) {
376 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
381 *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
382 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
383 link->ap->print_id, scr, *val);
388 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
390 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
391 link->ap->print_id, scr, val);
392 if (scr > SCR_NOTIFICATION) {
393 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
397 sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
402 static void clear_serror(struct ata_port *ap)
405 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
406 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
409 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
411 sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
412 sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
415 static u32 qcmd_tag_to_mask(u8 tag)
417 return 0x00000001 << (tag & 0x1f);
421 static void sata_dwc_error_intr(struct ata_port *ap,
422 struct sata_dwc_device *hsdev, uint intpr)
424 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
425 struct ata_eh_info *ehi = &ap->link.eh_info;
426 unsigned int err_mask = 0, action = 0;
427 struct ata_queued_cmd *qc;
431 ata_ehi_clear_desc(ehi);
433 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
434 status = ap->ops->sff_check_status(ap);
436 tag = ap->link.active_tag;
439 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
440 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
441 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
443 /* Clear error register and interrupt bit */
445 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
447 /* This is the only error happening now. TODO check for exact error */
449 err_mask |= AC_ERR_HOST_BUS;
450 action |= ATA_EH_RESET;
452 /* Pass this on to EH */
453 ehi->serror |= serror;
454 ehi->action |= action;
456 qc = ata_qc_from_tag(ap, tag);
458 qc->err_mask |= err_mask;
460 ehi->err_mask |= err_mask;
466 * Function : sata_dwc_isr
467 * arguments : irq, void *dev_instance, struct pt_regs *regs
468 * Return value : irqreturn_t - status of IRQ
469 * This Interrupt handler called via port ops registered function.
470 * .irq_handler = sata_dwc_isr
472 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
474 struct ata_host *host = (struct ata_host *)dev_instance;
475 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
477 struct ata_queued_cmd *qc;
480 int handled, num_processed, port = 0;
481 uint intpr, sactive, sactive2, tag_mask;
482 struct sata_dwc_device_port *hsdevp;
483 hsdev->sactive_issued = 0;
485 spin_lock_irqsave(&host->lock, flags);
487 /* Read the interrupt register */
488 intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
490 ap = host->ports[port];
491 hsdevp = HSDEVP_FROM_AP(ap);
493 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
494 ap->link.active_tag);
496 /* Check for error interrupt */
497 if (intpr & SATA_DWC_INTPR_ERR) {
498 sata_dwc_error_intr(ap, hsdev, intpr);
503 /* Check for DMA SETUP FIS (FP DMA) interrupt */
504 if (intpr & SATA_DWC_INTPR_NEWFP) {
505 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
507 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
508 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
509 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
510 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
512 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
514 qc = ata_qc_from_tag(ap, tag);
516 dev_err(ap->dev, "failed to get qc");
521 * Start FP DMA for NCQ command. At this point the tag is the
522 * active tag. It is the tag that matches the command about to
525 trace_ata_bmdma_start(ap, &qc->tf, tag);
526 qc->ap->link.active_tag = tag;
527 sata_dwc_bmdma_start_by_tag(qc, tag);
532 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
533 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
535 /* If no sactive issued and tag_mask is zero then this is not NCQ */
536 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
537 if (ap->link.active_tag == ATA_TAG_POISON)
540 tag = ap->link.active_tag;
541 qc = ata_qc_from_tag(ap, tag);
543 /* DEV interrupt w/ no active qc? */
544 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
546 "%s interrupt with no active qc qc=%p\n",
548 ap->ops->sff_check_status(ap);
552 status = ap->ops->sff_check_status(ap);
554 qc->ap->link.active_tag = tag;
555 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
557 if (status & ATA_ERR) {
558 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
559 sata_dwc_qc_complete(ap, qc, 1);
564 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
565 __func__, get_prot_descript(qc->tf.protocol));
567 if (ata_is_dma(qc->tf.protocol)) {
569 * Each DMA transaction produces 2 interrupts. The DMAC
570 * transfer complete interrupt and the SATA controller
571 * operation done interrupt. The command should be
572 * completed only after both interrupts are seen.
574 hsdevp->dma_interrupt_count++;
575 if (hsdevp->dma_pending[tag] == \
576 SATA_DWC_DMA_PENDING_NONE) {
578 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
579 __func__, intpr, status,
580 hsdevp->dma_pending[tag]);
583 if ((hsdevp->dma_interrupt_count % 2) == 0)
584 sata_dwc_dma_xfer_complete(ap, 1);
585 } else if (ata_is_pio(qc->tf.protocol)) {
586 ata_sff_hsm_move(ap, qc, status, 0);
590 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
599 * This is a NCQ command. At this point we need to figure out for which
600 * tags we have gotten a completion interrupt. One interrupt may serve
601 * as completion for more than one operation when commands are queued
602 * (NCQ). We need to process each completed command.
605 /* process completed commands */
606 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
607 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
609 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
611 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
612 __func__, sactive, hsdev->sactive_issued, tag_mask);
615 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
617 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
618 sactive, hsdev->sactive_issued, tag_mask);
621 /* read just to clear ... not bad if currently still busy */
622 status = ap->ops->sff_check_status(ap);
623 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
629 while (!(tag_mask & 0x00000001)) {
634 tag_mask &= (~0x00000001);
635 qc = ata_qc_from_tag(ap, tag);
637 dev_err(ap->dev, "failed to get qc");
642 /* To be picked up by completion functions */
643 qc->ap->link.active_tag = tag;
644 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
646 /* Let libata/scsi layers handle error */
647 if (status & ATA_ERR) {
648 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
650 sata_dwc_qc_complete(ap, qc, 1);
655 /* Process completed command */
656 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
657 get_prot_descript(qc->tf.protocol));
658 if (ata_is_dma(qc->tf.protocol)) {
659 hsdevp->dma_interrupt_count++;
660 if (hsdevp->dma_pending[tag] == \
661 SATA_DWC_DMA_PENDING_NONE)
662 dev_warn(ap->dev, "%s: DMA not pending?\n",
664 if ((hsdevp->dma_interrupt_count % 2) == 0)
665 sata_dwc_dma_xfer_complete(ap, 1);
667 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
673 ap->stats.idle_irq++;
674 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
676 } /* while tag_mask */
679 * Check to see if any commands completed while we were processing our
680 * initial set of completed commands (read status clears interrupts,
681 * so we might miss a completed command interrupt if one came in while
682 * we were processing --we read status as part of processing a completed
685 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
686 if (sactive2 != sactive) {
688 "More completed - sactive=0x%x sactive2=0x%x\n",
694 spin_unlock_irqrestore(&host->lock, flags);
695 return IRQ_RETVAL(handled);
698 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
700 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
701 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
703 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
704 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
705 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
706 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
707 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
708 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
711 * This should not happen, it indicates the driver is out of
712 * sync. If it does happen, clear dmacr anyway.
715 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
716 __func__, tag, hsdevp->dma_pending[tag], dmacr);
717 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
718 SATA_DWC_DMACR_TXRXCH_CLEAR);
722 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
724 struct ata_queued_cmd *qc;
725 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
726 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
729 tag = ap->link.active_tag;
730 qc = ata_qc_from_tag(ap, tag);
732 dev_err(ap->dev, "failed to get qc");
736 if (ata_is_dma(qc->tf.protocol)) {
737 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
739 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
741 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
744 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
745 sata_dwc_qc_complete(ap, qc, check_status);
746 ap->link.active_tag = ATA_TAG_POISON;
748 sata_dwc_qc_complete(ap, qc, check_status);
752 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
758 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
759 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
760 hsdev->sactive_queued = 0;
761 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
763 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
764 dev_err(ap->dev, "TX DMA PENDING\n");
765 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
766 dev_err(ap->dev, "RX DMA PENDING\n");
768 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
769 qc->tf.command, status, ap->print_id, qc->tf.protocol);
771 /* clear active bit */
772 mask = (~(qcmd_tag_to_mask(tag)));
773 hsdev->sactive_queued = hsdev->sactive_queued & mask;
774 hsdev->sactive_issued = hsdev->sactive_issued & mask;
779 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
781 /* Enable selective interrupts by setting the interrupt maskregister*/
782 sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
783 SATA_DWC_INTMR_ERRM |
784 SATA_DWC_INTMR_NEWFPM |
785 SATA_DWC_INTMR_PMABRTM |
786 SATA_DWC_INTMR_DMATM);
788 * Unmask the error bits that should trigger an error interrupt by
789 * setting the error mask register.
791 sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
793 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
794 __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
795 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
798 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
800 port->cmd_addr = base + 0x00;
801 port->data_addr = base + 0x00;
803 port->error_addr = base + 0x04;
804 port->feature_addr = base + 0x04;
806 port->nsect_addr = base + 0x08;
808 port->lbal_addr = base + 0x0c;
809 port->lbam_addr = base + 0x10;
810 port->lbah_addr = base + 0x14;
812 port->device_addr = base + 0x18;
813 port->command_addr = base + 0x1c;
814 port->status_addr = base + 0x1c;
816 port->altstatus_addr = base + 0x20;
817 port->ctl_addr = base + 0x20;
820 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
822 struct sata_dwc_device *hsdev = hsdevp->hsdev;
823 struct device *dev = hsdev->dev;
825 #ifdef CONFIG_SATA_DWC_OLD_DMA
826 if (!of_find_property(dev->of_node, "dmas", NULL))
827 return sata_dwc_dma_get_channel_old(hsdevp);
830 hsdevp->chan = dma_request_chan(dev, "sata-dma");
831 if (IS_ERR(hsdevp->chan)) {
832 dev_err(dev, "failed to allocate dma channel: %ld\n",
833 PTR_ERR(hsdevp->chan));
834 return PTR_ERR(hsdevp->chan);
841 * Function : sata_dwc_port_start
842 * arguments : struct ata_ioports *port
843 * Return value : returns 0 if success, error code otherwise
844 * This function allocates the scatter gather LLI table for AHB DMA
846 static int sata_dwc_port_start(struct ata_port *ap)
849 struct sata_dwc_device *hsdev;
850 struct sata_dwc_device_port *hsdevp = NULL;
854 hsdev = HSDEV_FROM_AP(ap);
856 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
858 hsdev->host = ap->host;
859 pdev = ap->host->dev;
861 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
866 /* Allocate Port Struct */
867 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
872 hsdevp->hsdev = hsdev;
874 err = sata_dwc_dma_get_channel(hsdevp);
878 err = phy_power_on(hsdev->phy);
882 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
883 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
885 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
886 ap->bmdma_prd_dma = 0;
888 if (ap->port_no == 0) {
889 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
891 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
892 SATA_DWC_DMACR_TXRXCH_CLEAR);
894 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
896 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
897 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
898 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
901 /* Clear any error bits before libata starts issuing commands */
903 ap->private_data = hsdevp;
904 dev_dbg(ap->dev, "%s: done\n", __func__);
910 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
914 static void sata_dwc_port_stop(struct ata_port *ap)
916 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
917 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
919 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
921 dmaengine_terminate_sync(hsdevp->chan);
922 dma_release_channel(hsdevp->chan);
923 phy_power_off(hsdev->phy);
926 ap->private_data = NULL;
930 * Function : sata_dwc_exec_command_by_tag
931 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
932 * Return value : None
933 * This function keeps track of individual command tag ids and calls
934 * ata_exec_command in libata
936 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
937 struct ata_taskfile *tf,
938 u8 tag, u32 cmd_issued)
940 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
942 hsdevp->cmd_issued[tag] = cmd_issued;
945 * Clear SError before executing a new command.
946 * sata_dwc_scr_write and read can not be used here. Clearing the PM
947 * managed SError register for the disk needs to be done before the
948 * task file is loaded.
951 ata_sff_exec_command(ap, tf);
954 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
956 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
957 SATA_DWC_CMD_ISSUED_PEND);
960 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
964 if (!ata_is_ncq(qc->tf.protocol))
967 sata_dwc_bmdma_setup_by_tag(qc, tag);
970 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
974 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
975 struct ata_port *ap = qc->ap;
976 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
977 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
978 int dir = qc->dma_dir;
980 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
982 if (dir == DMA_TO_DEVICE)
983 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
985 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
988 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
989 __func__, hsdevp->cmd_issued[tag], tag);
994 sata_dwc_scr_read(&ap->link, SCR_ERROR, ®);
995 if (reg & SATA_DWC_SERROR_ERR_BITS) {
996 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1000 if (dir == DMA_TO_DEVICE)
1001 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1002 SATA_DWC_DMACR_TXCHEN);
1004 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1005 SATA_DWC_DMACR_RXCHEN);
1007 /* Enable AHB DMA transfer on the specified channel */
1008 dmaengine_submit(desc);
1009 dma_async_issue_pending(hsdevp->chan);
1013 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1015 u8 tag = qc->hw_tag;
1017 if (!ata_is_ncq(qc->tf.protocol))
1020 sata_dwc_bmdma_start_by_tag(qc, tag);
1023 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1026 u8 tag = qc->hw_tag;
1027 struct ata_port *ap = qc->ap;
1028 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1030 if (!ata_is_ncq(qc->tf.protocol))
1033 if (ata_is_dma(qc->tf.protocol)) {
1034 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1035 if (!hsdevp->desc[tag])
1036 return AC_ERR_SYSTEM;
1038 hsdevp->desc[tag] = NULL;
1041 if (ata_is_ncq(qc->tf.protocol)) {
1042 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1043 sactive |= (0x00000001 << tag);
1044 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1046 trace_ata_tf_load(ap, &qc->tf);
1047 ap->ops->sff_tf_load(ap, &qc->tf);
1048 trace_ata_exec_command(ap, &qc->tf, tag);
1049 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1050 SATA_DWC_CMD_ISSUED_PEND);
1052 return ata_bmdma_qc_issue(qc);
1057 static void sata_dwc_error_handler(struct ata_port *ap)
1059 ata_sff_error_handler(ap);
1062 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1063 unsigned long deadline)
1065 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1068 ret = sata_sff_hardreset(link, class, deadline);
1070 sata_dwc_enable_interrupts(hsdev);
1072 /* Reconfigure the DMA control register */
1073 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1074 SATA_DWC_DMACR_TXRXCH_CLEAR);
1076 /* Reconfigure the DMA Burst Transaction Size register */
1077 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1078 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1079 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1084 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1086 /* SATA DWC is master only */
1090 * scsi mid-layer and libata interface structures
1092 static struct scsi_host_template sata_dwc_sht = {
1093 ATA_NCQ_SHT(DRV_NAME),
1095 * test-only: Currently this driver doesn't handle NCQ
1096 * correctly. We enable NCQ but set the queue depth to a
1097 * max of 1. This will get fixed in in a future release.
1099 .sg_tablesize = LIBATA_MAX_PRD,
1100 /* .can_queue = ATA_MAX_QUEUE, */
1102 * Make sure a LLI block is not created that will span 8K max FIS
1103 * boundary. If the block spans such a FIS boundary, there is a chance
1104 * that a DMA burst will cross that boundary -- this results in an
1105 * error in the host controller.
1107 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
1110 static struct ata_port_operations sata_dwc_ops = {
1111 .inherits = &ata_sff_port_ops,
1113 .error_handler = sata_dwc_error_handler,
1114 .hardreset = sata_dwc_hardreset,
1116 .qc_issue = sata_dwc_qc_issue,
1118 .scr_read = sata_dwc_scr_read,
1119 .scr_write = sata_dwc_scr_write,
1121 .port_start = sata_dwc_port_start,
1122 .port_stop = sata_dwc_port_stop,
1124 .sff_dev_select = sata_dwc_dev_select,
1126 .bmdma_setup = sata_dwc_bmdma_setup,
1127 .bmdma_start = sata_dwc_bmdma_start,
1130 static const struct ata_port_info sata_dwc_port_info[] = {
1132 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1133 .pio_mask = ATA_PIO4,
1134 .udma_mask = ATA_UDMA6,
1135 .port_ops = &sata_dwc_ops,
1139 static int sata_dwc_probe(struct platform_device *ofdev)
1141 struct device *dev = &ofdev->dev;
1142 struct device_node *np = dev->of_node;
1143 struct sata_dwc_device *hsdev;
1145 char *ver = (char *)&versionr;
1149 struct ata_host *host;
1150 struct ata_port_info pi = sata_dwc_port_info[0];
1151 const struct ata_port_info *ppi[] = { &pi, NULL };
1152 struct resource *res;
1154 /* Allocate DWC SATA device */
1155 host = ata_host_alloc_pinfo(dev, ppi, SATA_DWC_MAX_PORTS);
1156 hsdev = devm_kzalloc(dev, sizeof(*hsdev), GFP_KERNEL);
1157 if (!host || !hsdev)
1160 host->private_data = hsdev;
1162 /* Ioremap SATA registers */
1163 base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);
1165 return PTR_ERR(base);
1166 dev_dbg(dev, "ioremap done for SATA register address\n");
1168 /* Synopsys DWC SATA specific Registers */
1169 hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1170 hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
1173 host->ports[0]->ioaddr.cmd_addr = base;
1174 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1175 sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1177 /* Read the ID and Version Registers */
1178 idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1179 versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1180 dev_notice(dev, "id %d, controller version %c.%c%c\n", idr, ver[0], ver[1], ver[2]);
1182 /* Save dev for later use in dev_xxx() routines */
1185 /* Enable SATA Interrupts */
1186 sata_dwc_enable_interrupts(hsdev);
1188 /* Get SATA interrupt number */
1189 irq = irq_of_parse_and_map(np, 0);
1190 if (irq == NO_IRQ) {
1191 dev_err(dev, "no SATA DMA irq\n");
1195 #ifdef CONFIG_SATA_DWC_OLD_DMA
1196 if (!of_find_property(np, "dmas", NULL)) {
1197 err = sata_dwc_dma_init_old(ofdev, hsdev);
1203 hsdev->phy = devm_phy_optional_get(dev, "sata-phy");
1204 if (IS_ERR(hsdev->phy))
1205 return PTR_ERR(hsdev->phy);
1207 err = phy_init(hsdev->phy);
1212 * Now, register with libATA core, this will also initiate the
1213 * device discovery process, invoking our port_start() handler &
1214 * error_handler() to execute a dummy Softreset EH session
1216 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1218 dev_err(dev, "failed to activate host");
1223 phy_exit(hsdev->phy);
1227 static int sata_dwc_remove(struct platform_device *ofdev)
1229 struct device *dev = &ofdev->dev;
1230 struct ata_host *host = dev_get_drvdata(dev);
1231 struct sata_dwc_device *hsdev = host->private_data;
1233 ata_host_detach(host);
1235 phy_exit(hsdev->phy);
1237 #ifdef CONFIG_SATA_DWC_OLD_DMA
1238 /* Free SATA DMA resources */
1239 sata_dwc_dma_exit_old(hsdev);
1242 dev_dbg(dev, "done\n");
1246 static const struct of_device_id sata_dwc_match[] = {
1247 { .compatible = "amcc,sata-460ex", },
1250 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1252 static struct platform_driver sata_dwc_driver = {
1255 .of_match_table = sata_dwc_match,
1257 .probe = sata_dwc_probe,
1258 .remove = sata_dwc_remove,
1261 module_platform_driver(sata_dwc_driver);
1263 MODULE_LICENSE("GPL");
1264 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1265 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1266 MODULE_VERSION(DRV_VERSION);