1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/ata/sata_dwc_460ex.c
5 * Synopsys DesignWare Cores (DWC) SATA host driver
7 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
9 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
10 * Copyright 2008 DENX Software Engineering
12 * Based on versions provided by AMCC and Synopsys which are:
13 * Copyright 2006 Applied Micro Circuits Corporation
14 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/dmaengine.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy/phy.h>
26 #include <linux/libata.h>
27 #include <linux/slab.h>
28 #include <trace/events/libata.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_cmnd.h>
35 /* These two are defined in "libata.h" */
39 #define DRV_NAME "sata-dwc"
40 #define DRV_VERSION "1.3"
42 #define sata_dwc_writel(a, v) writel_relaxed(v, a)
43 #define sata_dwc_readl(a) readl_relaxed(a)
49 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
52 SATA_DWC_MAX_PORTS = 1,
54 SATA_DWC_SCR_OFFSET = 0x24,
55 SATA_DWC_REG_OFFSET = 0x64,
58 /* DWC SATA Registers */
59 struct sata_dwc_regs {
60 u32 fptagr; /* 1st party DMA tag */
61 u32 fpbor; /* 1st party DMA buffer offset */
62 u32 fptcr; /* 1st party DMA Xfr count */
63 u32 dmacr; /* DMA Control */
64 u32 dbtsr; /* DMA Burst Transac size */
65 u32 intpr; /* Interrupt Pending */
66 u32 intmr; /* Interrupt Mask */
67 u32 errmr; /* Error Mask */
68 u32 llcr; /* Link Layer Control */
69 u32 phycr; /* PHY Control */
70 u32 physr; /* PHY Status */
71 u32 rxbistpd; /* Recvd BIST pattern def register */
72 u32 rxbistpd1; /* Recvd BIST data dword1 */
73 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
74 u32 txbistpd; /* Trans BIST pattern def register */
75 u32 txbistpd1; /* Trans BIST data dword1 */
76 u32 txbistpd2; /* Trans BIST data dword2 */
77 u32 bistcr; /* BIST Control Register */
78 u32 bistfctr; /* BIST FIS Count Register */
79 u32 bistsr; /* BIST Status Register */
80 u32 bistdecr; /* BIST Dword Error count register */
81 u32 res[15]; /* Reserved locations */
82 u32 testr; /* Test Register */
83 u32 versionr; /* Version Register */
84 u32 idr; /* ID Register */
85 u32 unimpl[192]; /* Unimplemented */
86 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
90 SCR_SCONTROL_DET_ENABLE = 0x00000001,
91 SCR_SSTATUS_DET_PRESENT = 0x00000001,
92 SCR_SERROR_DIAG_X = 0x04000000,
93 /* DWC SATA Register Operations */
94 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
95 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
96 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
97 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
98 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
99 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
100 SATA_DWC_INTPR_DMAT = 0x00000001,
101 SATA_DWC_INTPR_NEWFP = 0x00000002,
102 SATA_DWC_INTPR_PMABRT = 0x00000004,
103 SATA_DWC_INTPR_ERR = 0x00000008,
104 SATA_DWC_INTPR_NEWBIST = 0x00000010,
105 SATA_DWC_INTPR_IPF = 0x10000000,
106 SATA_DWC_INTMR_DMATM = 0x00000001,
107 SATA_DWC_INTMR_NEWFPM = 0x00000002,
108 SATA_DWC_INTMR_PMABRTM = 0x00000004,
109 SATA_DWC_INTMR_ERRM = 0x00000008,
110 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
111 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
112 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
113 SATA_DWC_LLCR_RPDEN = 0x00000004,
114 /* This is all error bits, zero's are reserved fields. */
115 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
118 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
119 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
120 SATA_DWC_DMACR_TMOD_TXCHEN)
121 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
122 SATA_DWC_DMACR_TMOD_TXCHEN)
123 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
124 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
126 struct sata_dwc_device {
127 struct device *dev; /* generic device struct */
128 struct ata_probe_ent *pe; /* ptr to probe-ent */
129 struct ata_host *host;
130 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
135 #ifdef CONFIG_SATA_DWC_OLD_DMA
136 struct dw_dma_chip *dma;
140 #define SATA_DWC_QCMD_MAX 32
142 struct sata_dwc_device_port {
143 struct sata_dwc_device *hsdev;
144 int cmd_issued[SATA_DWC_QCMD_MAX];
145 int dma_pending[SATA_DWC_QCMD_MAX];
148 struct dma_chan *chan;
149 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
150 u32 dma_interrupt_count;
154 * Commonly used DWC SATA driver macros
156 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
157 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
158 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
159 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
160 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
163 SATA_DWC_CMD_ISSUED_NOT = 0,
164 SATA_DWC_CMD_ISSUED_PEND = 1,
165 SATA_DWC_CMD_ISSUED_EXEC = 2,
166 SATA_DWC_CMD_ISSUED_NODATA = 3,
168 SATA_DWC_DMA_PENDING_NONE = 0,
169 SATA_DWC_DMA_PENDING_TX = 1,
170 SATA_DWC_DMA_PENDING_RX = 2,
176 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
177 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc);
178 static void sata_dwc_dma_xfer_complete(struct ata_port *ap);
179 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
181 #ifdef CONFIG_SATA_DWC_OLD_DMA
183 #include <linux/platform_data/dma-dw.h>
184 #include <linux/dma/dw.h>
186 static struct dw_dma_slave sata_dwc_dma_dws = {
193 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
195 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
197 if (dws->dma_dev != chan->device->dev)
204 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
206 struct sata_dwc_device *hsdev = hsdevp->hsdev;
207 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
208 struct device *dev = hsdev->dev;
214 dma_cap_set(DMA_SLAVE, mask);
216 /* Acquire DMA channel */
217 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
219 dev_err(dev, "%s: dma channel unavailable\n", __func__);
226 static int sata_dwc_dma_init_old(struct platform_device *pdev,
227 struct sata_dwc_device *hsdev)
229 struct device *dev = &pdev->dev;
230 struct device_node *np = dev->of_node;
232 hsdev->dma = devm_kzalloc(dev, sizeof(*hsdev->dma), GFP_KERNEL);
236 hsdev->dma->dev = dev;
237 hsdev->dma->id = pdev->id;
239 /* Get SATA DMA interrupt number */
240 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
241 if (hsdev->dma->irq == NO_IRQ) {
242 dev_err(dev, "no SATA DMA irq\n");
246 /* Get physical SATA DMA register base address */
247 hsdev->dma->regs = devm_platform_ioremap_resource(pdev, 1);
248 if (IS_ERR(hsdev->dma->regs))
249 return PTR_ERR(hsdev->dma->regs);
251 /* Initialize AHB DMAC */
252 return dw_dma_probe(hsdev->dma);
255 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
260 dw_dma_remove(hsdev->dma);
265 static const char *get_prot_descript(u8 protocol)
268 case ATA_PROT_NODATA:
269 return "ATA no data";
276 case ATA_PROT_NCQ_NODATA:
277 return "ATA NCQ no data";
278 case ATAPI_PROT_NODATA:
279 return "ATAPI no data";
289 static void dma_dwc_xfer_done(void *hsdev_instance)
292 struct sata_dwc_device *hsdev = hsdev_instance;
293 struct ata_host *host = (struct ata_host *)hsdev->host;
295 struct sata_dwc_device_port *hsdevp;
297 unsigned int port = 0;
299 spin_lock_irqsave(&host->lock, flags);
300 ap = host->ports[port];
301 hsdevp = HSDEVP_FROM_AP(ap);
302 tag = ap->link.active_tag;
305 * Each DMA command produces 2 interrupts. Only
306 * complete the command after both interrupts have been
307 * seen. (See sata_dwc_isr())
309 hsdevp->dma_interrupt_count++;
310 sata_dwc_clear_dmacr(hsdevp, tag);
312 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
313 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
314 tag, hsdevp->dma_pending[tag]);
317 if ((hsdevp->dma_interrupt_count % 2) == 0)
318 sata_dwc_dma_xfer_complete(ap);
320 spin_unlock_irqrestore(&host->lock, flags);
323 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
325 struct ata_port *ap = qc->ap;
326 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
327 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
328 struct dma_slave_config sconf;
329 struct dma_async_tx_descriptor *desc;
331 if (qc->dma_dir == DMA_DEV_TO_MEM) {
332 sconf.src_addr = hsdev->dmadr;
333 sconf.device_fc = false;
334 } else { /* DMA_MEM_TO_DEV */
335 sconf.dst_addr = hsdev->dmadr;
336 sconf.device_fc = false;
339 sconf.direction = qc->dma_dir;
340 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
341 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
342 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
343 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
345 dmaengine_slave_config(hsdevp->chan, &sconf);
347 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
348 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
350 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
355 desc->callback = dma_dwc_xfer_done;
356 desc->callback_param = hsdev;
358 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
359 qc->sg, qc->n_elem, &hsdev->dmadr);
364 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
366 if (scr > SCR_NOTIFICATION) {
367 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
372 *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
373 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
374 link->ap->print_id, scr, *val);
379 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
381 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
382 link->ap->print_id, scr, val);
383 if (scr > SCR_NOTIFICATION) {
384 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
388 sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
393 static void clear_serror(struct ata_port *ap)
396 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
397 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
400 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
402 sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
403 sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
406 static u32 qcmd_tag_to_mask(u8 tag)
408 return 0x00000001 << (tag & 0x1f);
412 static void sata_dwc_error_intr(struct ata_port *ap,
413 struct sata_dwc_device *hsdev, uint intpr)
415 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
416 struct ata_eh_info *ehi = &ap->link.eh_info;
417 unsigned int err_mask = 0, action = 0;
418 struct ata_queued_cmd *qc;
422 ata_ehi_clear_desc(ehi);
424 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
425 status = ap->ops->sff_check_status(ap);
427 tag = ap->link.active_tag;
430 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
431 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
432 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
434 /* Clear error register and interrupt bit */
436 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
438 /* This is the only error happening now. TODO check for exact error */
440 err_mask |= AC_ERR_HOST_BUS;
441 action |= ATA_EH_RESET;
443 /* Pass this on to EH */
444 ehi->serror |= serror;
445 ehi->action |= action;
447 qc = ata_qc_from_tag(ap, tag);
449 qc->err_mask |= err_mask;
451 ehi->err_mask |= err_mask;
457 * Function : sata_dwc_isr
458 * arguments : irq, void *dev_instance, struct pt_regs *regs
459 * Return value : irqreturn_t - status of IRQ
460 * This Interrupt handler called via port ops registered function.
461 * .irq_handler = sata_dwc_isr
463 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
465 struct ata_host *host = (struct ata_host *)dev_instance;
466 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
468 struct ata_queued_cmd *qc;
471 int handled, num_processed, port = 0;
472 uint intpr, sactive, sactive2, tag_mask;
473 struct sata_dwc_device_port *hsdevp;
474 hsdev->sactive_issued = 0;
476 spin_lock_irqsave(&host->lock, flags);
478 /* Read the interrupt register */
479 intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
481 ap = host->ports[port];
482 hsdevp = HSDEVP_FROM_AP(ap);
484 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
485 ap->link.active_tag);
487 /* Check for error interrupt */
488 if (intpr & SATA_DWC_INTPR_ERR) {
489 sata_dwc_error_intr(ap, hsdev, intpr);
494 /* Check for DMA SETUP FIS (FP DMA) interrupt */
495 if (intpr & SATA_DWC_INTPR_NEWFP) {
496 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
498 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
499 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
500 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
501 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
503 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
505 qc = ata_qc_from_tag(ap, tag);
507 dev_err(ap->dev, "failed to get qc");
512 * Start FP DMA for NCQ command. At this point the tag is the
513 * active tag. It is the tag that matches the command about to
516 trace_ata_bmdma_start(ap, &qc->tf, tag);
517 qc->ap->link.active_tag = tag;
518 sata_dwc_bmdma_start_by_tag(qc, tag);
523 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
524 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
526 /* If no sactive issued and tag_mask is zero then this is not NCQ */
527 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
528 if (ap->link.active_tag == ATA_TAG_POISON)
531 tag = ap->link.active_tag;
532 qc = ata_qc_from_tag(ap, tag);
534 /* DEV interrupt w/ no active qc? */
535 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
537 "%s interrupt with no active qc qc=%p\n",
539 ap->ops->sff_check_status(ap);
543 status = ap->ops->sff_check_status(ap);
545 qc->ap->link.active_tag = tag;
546 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
548 if (status & ATA_ERR) {
549 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
550 sata_dwc_qc_complete(ap, qc);
555 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
556 __func__, get_prot_descript(qc->tf.protocol));
558 if (ata_is_dma(qc->tf.protocol)) {
560 * Each DMA transaction produces 2 interrupts. The DMAC
561 * transfer complete interrupt and the SATA controller
562 * operation done interrupt. The command should be
563 * completed only after both interrupts are seen.
565 hsdevp->dma_interrupt_count++;
566 if (hsdevp->dma_pending[tag] == \
567 SATA_DWC_DMA_PENDING_NONE) {
569 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
570 __func__, intpr, status,
571 hsdevp->dma_pending[tag]);
574 if ((hsdevp->dma_interrupt_count % 2) == 0)
575 sata_dwc_dma_xfer_complete(ap);
576 } else if (ata_is_pio(qc->tf.protocol)) {
577 ata_sff_hsm_move(ap, qc, status, 0);
581 if (unlikely(sata_dwc_qc_complete(ap, qc)))
590 * This is a NCQ command. At this point we need to figure out for which
591 * tags we have gotten a completion interrupt. One interrupt may serve
592 * as completion for more than one operation when commands are queued
593 * (NCQ). We need to process each completed command.
596 /* process completed commands */
597 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
598 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
600 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
602 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
603 __func__, sactive, hsdev->sactive_issued, tag_mask);
606 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
608 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
609 sactive, hsdev->sactive_issued, tag_mask);
612 /* read just to clear ... not bad if currently still busy */
613 status = ap->ops->sff_check_status(ap);
614 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
620 while (!(tag_mask & 0x00000001)) {
625 tag_mask &= (~0x00000001);
626 qc = ata_qc_from_tag(ap, tag);
628 dev_err(ap->dev, "failed to get qc");
633 /* To be picked up by completion functions */
634 qc->ap->link.active_tag = tag;
635 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
637 /* Let libata/scsi layers handle error */
638 if (status & ATA_ERR) {
639 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
641 sata_dwc_qc_complete(ap, qc);
646 /* Process completed command */
647 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
648 get_prot_descript(qc->tf.protocol));
649 if (ata_is_dma(qc->tf.protocol)) {
650 hsdevp->dma_interrupt_count++;
651 if (hsdevp->dma_pending[tag] == \
652 SATA_DWC_DMA_PENDING_NONE)
653 dev_warn(ap->dev, "%s: DMA not pending?\n",
655 if ((hsdevp->dma_interrupt_count % 2) == 0)
656 sata_dwc_dma_xfer_complete(ap);
658 if (unlikely(sata_dwc_qc_complete(ap, qc)))
664 ap->stats.idle_irq++;
665 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
667 } /* while tag_mask */
670 * Check to see if any commands completed while we were processing our
671 * initial set of completed commands (read status clears interrupts,
672 * so we might miss a completed command interrupt if one came in while
673 * we were processing --we read status as part of processing a completed
676 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
677 if (sactive2 != sactive) {
679 "More completed - sactive=0x%x sactive2=0x%x\n",
685 spin_unlock_irqrestore(&host->lock, flags);
686 return IRQ_RETVAL(handled);
689 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
691 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
692 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
694 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
695 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
696 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
697 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
698 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
699 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
702 * This should not happen, it indicates the driver is out of
703 * sync. If it does happen, clear dmacr anyway.
706 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
707 __func__, tag, hsdevp->dma_pending[tag], dmacr);
708 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
709 SATA_DWC_DMACR_TXRXCH_CLEAR);
713 static void sata_dwc_dma_xfer_complete(struct ata_port *ap)
715 struct ata_queued_cmd *qc;
716 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
717 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
720 tag = ap->link.active_tag;
721 qc = ata_qc_from_tag(ap, tag);
723 dev_err(ap->dev, "failed to get qc");
727 if (ata_is_dma(qc->tf.protocol)) {
728 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
730 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
732 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
735 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
736 sata_dwc_qc_complete(ap, qc);
737 ap->link.active_tag = ATA_TAG_POISON;
739 sata_dwc_qc_complete(ap, qc);
743 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc)
748 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
749 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
750 hsdev->sactive_queued = 0;
752 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
753 dev_err(ap->dev, "TX DMA PENDING\n");
754 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
755 dev_err(ap->dev, "RX DMA PENDING\n");
757 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
758 qc->tf.command, status, ap->print_id, qc->tf.protocol);
760 /* clear active bit */
761 mask = (~(qcmd_tag_to_mask(tag)));
762 hsdev->sactive_queued = hsdev->sactive_queued & mask;
763 hsdev->sactive_issued = hsdev->sactive_issued & mask;
768 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
770 /* Enable selective interrupts by setting the interrupt maskregister*/
771 sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
772 SATA_DWC_INTMR_ERRM |
773 SATA_DWC_INTMR_NEWFPM |
774 SATA_DWC_INTMR_PMABRTM |
775 SATA_DWC_INTMR_DMATM);
777 * Unmask the error bits that should trigger an error interrupt by
778 * setting the error mask register.
780 sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
782 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
783 __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
784 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
787 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
789 port->cmd_addr = base + 0x00;
790 port->data_addr = base + 0x00;
792 port->error_addr = base + 0x04;
793 port->feature_addr = base + 0x04;
795 port->nsect_addr = base + 0x08;
797 port->lbal_addr = base + 0x0c;
798 port->lbam_addr = base + 0x10;
799 port->lbah_addr = base + 0x14;
801 port->device_addr = base + 0x18;
802 port->command_addr = base + 0x1c;
803 port->status_addr = base + 0x1c;
805 port->altstatus_addr = base + 0x20;
806 port->ctl_addr = base + 0x20;
809 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
811 struct sata_dwc_device *hsdev = hsdevp->hsdev;
812 struct device *dev = hsdev->dev;
814 #ifdef CONFIG_SATA_DWC_OLD_DMA
815 if (!of_find_property(dev->of_node, "dmas", NULL))
816 return sata_dwc_dma_get_channel_old(hsdevp);
819 hsdevp->chan = dma_request_chan(dev, "sata-dma");
820 if (IS_ERR(hsdevp->chan)) {
821 dev_err(dev, "failed to allocate dma channel: %ld\n",
822 PTR_ERR(hsdevp->chan));
823 return PTR_ERR(hsdevp->chan);
830 * Function : sata_dwc_port_start
831 * arguments : struct ata_ioports *port
832 * Return value : returns 0 if success, error code otherwise
833 * This function allocates the scatter gather LLI table for AHB DMA
835 static int sata_dwc_port_start(struct ata_port *ap)
838 struct sata_dwc_device *hsdev;
839 struct sata_dwc_device_port *hsdevp = NULL;
843 hsdev = HSDEV_FROM_AP(ap);
845 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
847 hsdev->host = ap->host;
848 pdev = ap->host->dev;
850 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
855 /* Allocate Port Struct */
856 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
861 hsdevp->hsdev = hsdev;
863 err = sata_dwc_dma_get_channel(hsdevp);
867 err = phy_power_on(hsdev->phy);
871 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
872 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
874 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
875 ap->bmdma_prd_dma = 0;
877 if (ap->port_no == 0) {
878 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
880 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
881 SATA_DWC_DMACR_TXRXCH_CLEAR);
883 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
885 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
886 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
887 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
890 /* Clear any error bits before libata starts issuing commands */
892 ap->private_data = hsdevp;
893 dev_dbg(ap->dev, "%s: done\n", __func__);
899 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
903 static void sata_dwc_port_stop(struct ata_port *ap)
905 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
906 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
908 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
910 dmaengine_terminate_sync(hsdevp->chan);
911 dma_release_channel(hsdevp->chan);
912 phy_power_off(hsdev->phy);
915 ap->private_data = NULL;
919 * Function : sata_dwc_exec_command_by_tag
920 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
921 * Return value : None
922 * This function keeps track of individual command tag ids and calls
923 * ata_exec_command in libata
925 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
926 struct ata_taskfile *tf,
927 u8 tag, u32 cmd_issued)
929 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
931 hsdevp->cmd_issued[tag] = cmd_issued;
934 * Clear SError before executing a new command.
935 * sata_dwc_scr_write and read can not be used here. Clearing the PM
936 * managed SError register for the disk needs to be done before the
937 * task file is loaded.
940 ata_sff_exec_command(ap, tf);
943 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
945 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
946 SATA_DWC_CMD_ISSUED_PEND);
949 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
953 if (!ata_is_ncq(qc->tf.protocol))
956 sata_dwc_bmdma_setup_by_tag(qc, tag);
959 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
963 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
964 struct ata_port *ap = qc->ap;
965 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
966 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
967 int dir = qc->dma_dir;
969 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
971 if (dir == DMA_TO_DEVICE)
972 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
974 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
977 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
978 __func__, hsdevp->cmd_issued[tag], tag);
983 sata_dwc_scr_read(&ap->link, SCR_ERROR, ®);
984 if (reg & SATA_DWC_SERROR_ERR_BITS) {
985 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
989 if (dir == DMA_TO_DEVICE)
990 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
991 SATA_DWC_DMACR_TXCHEN);
993 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
994 SATA_DWC_DMACR_RXCHEN);
996 /* Enable AHB DMA transfer on the specified channel */
997 dmaengine_submit(desc);
998 dma_async_issue_pending(hsdevp->chan);
1002 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1004 u8 tag = qc->hw_tag;
1006 if (!ata_is_ncq(qc->tf.protocol))
1009 sata_dwc_bmdma_start_by_tag(qc, tag);
1012 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1015 u8 tag = qc->hw_tag;
1016 struct ata_port *ap = qc->ap;
1017 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1019 if (!ata_is_ncq(qc->tf.protocol))
1022 if (ata_is_dma(qc->tf.protocol)) {
1023 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1024 if (!hsdevp->desc[tag])
1025 return AC_ERR_SYSTEM;
1027 hsdevp->desc[tag] = NULL;
1030 if (ata_is_ncq(qc->tf.protocol)) {
1031 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1032 sactive |= (0x00000001 << tag);
1033 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1035 trace_ata_tf_load(ap, &qc->tf);
1036 ap->ops->sff_tf_load(ap, &qc->tf);
1037 trace_ata_exec_command(ap, &qc->tf, tag);
1038 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1039 SATA_DWC_CMD_ISSUED_PEND);
1041 return ata_bmdma_qc_issue(qc);
1046 static void sata_dwc_error_handler(struct ata_port *ap)
1048 ata_sff_error_handler(ap);
1051 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1052 unsigned long deadline)
1054 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1057 ret = sata_sff_hardreset(link, class, deadline);
1059 sata_dwc_enable_interrupts(hsdev);
1061 /* Reconfigure the DMA control register */
1062 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1063 SATA_DWC_DMACR_TXRXCH_CLEAR);
1065 /* Reconfigure the DMA Burst Transaction Size register */
1066 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1067 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1068 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1073 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1075 /* SATA DWC is master only */
1079 * scsi mid-layer and libata interface structures
1081 static struct scsi_host_template sata_dwc_sht = {
1082 ATA_NCQ_SHT(DRV_NAME),
1084 * test-only: Currently this driver doesn't handle NCQ
1085 * correctly. We enable NCQ but set the queue depth to a
1086 * max of 1. This will get fixed in in a future release.
1088 .sg_tablesize = LIBATA_MAX_PRD,
1089 /* .can_queue = ATA_MAX_QUEUE, */
1091 * Make sure a LLI block is not created that will span 8K max FIS
1092 * boundary. If the block spans such a FIS boundary, there is a chance
1093 * that a DMA burst will cross that boundary -- this results in an
1094 * error in the host controller.
1096 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
1099 static struct ata_port_operations sata_dwc_ops = {
1100 .inherits = &ata_sff_port_ops,
1102 .error_handler = sata_dwc_error_handler,
1103 .hardreset = sata_dwc_hardreset,
1105 .qc_issue = sata_dwc_qc_issue,
1107 .scr_read = sata_dwc_scr_read,
1108 .scr_write = sata_dwc_scr_write,
1110 .port_start = sata_dwc_port_start,
1111 .port_stop = sata_dwc_port_stop,
1113 .sff_dev_select = sata_dwc_dev_select,
1115 .bmdma_setup = sata_dwc_bmdma_setup,
1116 .bmdma_start = sata_dwc_bmdma_start,
1119 static const struct ata_port_info sata_dwc_port_info[] = {
1121 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1122 .pio_mask = ATA_PIO4,
1123 .udma_mask = ATA_UDMA6,
1124 .port_ops = &sata_dwc_ops,
1128 static int sata_dwc_probe(struct platform_device *ofdev)
1130 struct device *dev = &ofdev->dev;
1131 struct device_node *np = dev->of_node;
1132 struct sata_dwc_device *hsdev;
1134 char *ver = (char *)&versionr;
1138 struct ata_host *host;
1139 struct ata_port_info pi = sata_dwc_port_info[0];
1140 const struct ata_port_info *ppi[] = { &pi, NULL };
1141 struct resource *res;
1143 /* Allocate DWC SATA device */
1144 host = ata_host_alloc_pinfo(dev, ppi, SATA_DWC_MAX_PORTS);
1145 hsdev = devm_kzalloc(dev, sizeof(*hsdev), GFP_KERNEL);
1146 if (!host || !hsdev)
1149 host->private_data = hsdev;
1151 /* Ioremap SATA registers */
1152 base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);
1154 return PTR_ERR(base);
1155 dev_dbg(dev, "ioremap done for SATA register address\n");
1157 /* Synopsys DWC SATA specific Registers */
1158 hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1159 hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
1162 host->ports[0]->ioaddr.cmd_addr = base;
1163 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1164 sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1166 /* Read the ID and Version Registers */
1167 idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1168 versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1169 dev_notice(dev, "id %d, controller version %c.%c%c\n", idr, ver[0], ver[1], ver[2]);
1171 /* Save dev for later use in dev_xxx() routines */
1174 /* Enable SATA Interrupts */
1175 sata_dwc_enable_interrupts(hsdev);
1177 /* Get SATA interrupt number */
1178 irq = irq_of_parse_and_map(np, 0);
1179 if (irq == NO_IRQ) {
1180 dev_err(dev, "no SATA DMA irq\n");
1184 #ifdef CONFIG_SATA_DWC_OLD_DMA
1185 if (!of_find_property(np, "dmas", NULL)) {
1186 err = sata_dwc_dma_init_old(ofdev, hsdev);
1192 hsdev->phy = devm_phy_optional_get(dev, "sata-phy");
1193 if (IS_ERR(hsdev->phy))
1194 return PTR_ERR(hsdev->phy);
1196 err = phy_init(hsdev->phy);
1201 * Now, register with libATA core, this will also initiate the
1202 * device discovery process, invoking our port_start() handler &
1203 * error_handler() to execute a dummy Softreset EH session
1205 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1207 dev_err(dev, "failed to activate host");
1212 phy_exit(hsdev->phy);
1216 static int sata_dwc_remove(struct platform_device *ofdev)
1218 struct device *dev = &ofdev->dev;
1219 struct ata_host *host = dev_get_drvdata(dev);
1220 struct sata_dwc_device *hsdev = host->private_data;
1222 ata_host_detach(host);
1224 phy_exit(hsdev->phy);
1226 #ifdef CONFIG_SATA_DWC_OLD_DMA
1227 /* Free SATA DMA resources */
1228 sata_dwc_dma_exit_old(hsdev);
1231 dev_dbg(dev, "done\n");
1235 static const struct of_device_id sata_dwc_match[] = {
1236 { .compatible = "amcc,sata-460ex", },
1239 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1241 static struct platform_driver sata_dwc_driver = {
1244 .of_match_table = sata_dwc_match,
1246 .probe = sata_dwc_probe,
1247 .remove = sata_dwc_remove,
1250 module_platform_driver(sata_dwc_driver);
1252 MODULE_LICENSE("GPL");
1253 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1254 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1255 MODULE_VERSION(DRV_VERSION);