1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * (c) 1996-1998 Grant R. Guenther <grant@torque.net>
5 * frpw.c is a low-level protocol driver for the Freecom "Power" parallel port
8 * Some applications of this adapter may require a "printer" reset prior to
9 * loading the driver. This can be done by loading and unloading the "lp"
10 * driver, or it can be done by this driver if you define FRPW_HARD_RESET.
11 * The latter is not recommended as it may upset devices on other ports.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/wait.h>
21 #include "pata_parport.h"
23 #define cec4 w2(0xc);w2(0xe);w2(0xe);w2(0xc);w2(4);w2(4);w2(4);
24 #define j44(l,h) (((l>>4)&0x0f)|(h&0xf0))
27 * cont = 0 - access the IDE register file
28 * cont = 1 - access the IDE command set
30 static int cont_map[2] = { 0x08, 0x10 };
32 static int frpw_read_regr(struct pi_adapter *pi, int cont, int regr)
36 r = regr + cont_map[cont];
47 static void frpw_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
49 int r = regr + cont_map[cont];
53 w2(5); w2(7); w2(5); w2(4);
56 static void frpw_read_block_int(struct pi_adapter *pi, char *buf, int count,
63 w2(4); w0(regr); cec4;
64 for (k = 0; k < count; k++) {
74 w2(4); w0(regr + 0xc0); cec4;
76 for (k = 0; k < count; k++) {
81 w2(0xac); w2(0xa4); w2(4);
85 w2(4); w0(regr + 0x80); cec4;
86 for (k = 0; k < count; k++)
93 w2(4); w0(regr + 0x80); cec4;
94 for (k = 0; k < count - 2; k++)
97 buf[count - 2] = r4();
98 buf[count - 1] = r4();
103 w2(4); w0(regr + 0x80); cec4;
104 for (k = 0; k < count / 2 - 1; k++)
105 ((u16 *)buf)[k] = r4w();
107 buf[count - 2] = r4();
108 buf[count - 1] = r4();
113 w2(4); w0(regr + 0x80); cec4;
114 for (k = 0; k < count / 4 - 1; k++)
115 ((u32 *)buf)[k] = r4l();
116 buf[count - 4] = r4();
117 buf[count - 3] = r4();
119 buf[count - 2] = r4();
120 buf[count - 1] = r4();
126 static void frpw_read_block(struct pi_adapter *pi, char *buf, int count)
128 frpw_read_block_int(pi, buf, count, 0x08);
131 static void frpw_write_block(struct pi_adapter *pi, char *buf, int count)
139 w2(4); w0(8); cec4; w2(5);
140 for (k = 0; k < count; k++) {
148 w2(4); w0(0xc8); cec4; w2(5);
149 for (k = 0; k < count; k++)
155 w2(4); w0(0xc8); cec4; w2(5);
156 for (k = 0; k < count / 2; k++)
157 w4w(((u16 *)buf)[k]);
162 w2(4); w0(0xc8); cec4; w2(5);
163 for (k = 0; k < count / 4; k++)
164 w4l(((u32 *)buf)[k]);
170 static void frpw_connect(struct pi_adapter *pi)
177 static void frpw_disconnect(struct pi_adapter *pi)
179 w2(4); w0(0x20); cec4;
185 * Stub logic to see if PNP string is available - used to distinguish
186 * between the Xilinx and ASIC implementations of the Freecom adapter.
187 * returns chip_type: 0 = Xilinx, 1 = ASIC
189 static int frpw_test_pnp(struct pi_adapter *pi)
193 #ifdef FRPW_HARD_RESET
194 w0(0); w2(8); udelay(50); w2(0xc); /* parallel bus reset */
198 olddelay = pi->delay;
204 w2(4); w0(4); w2(6); w2(7);
205 a = r1() & 0xff; w2(4); b = r1() & 0xff;
206 w2(0xc); w2(0xe); w2(4);
208 pi->delay = olddelay;
212 return ((~a & 0x40) && (b & 0x40));
216 * We use the pi->private to remember the result of the PNP test.
217 * To make this work, private = port*2 + chip. Yes, I know it's a hack :-(
219 static int frpw_test_proto(struct pi_adapter *pi)
225 if ((pi->private >> 1) != pi->port)
226 pi->private = frpw_test_pnp(pi) + 2*pi->port;
228 if (((pi->private & 0x1) == 0) && (pi->mode > 2)) {
230 "frpw: Xilinx does not support mode %d\n", pi->mode);
234 if (((pi->private & 0x1) == 1) && (pi->mode == 2)) {
235 dev_dbg(&pi->dev, "frpw: ASIC does not support mode 2\n");
240 for (j = 0; j < 2; j++) {
241 frpw_write_regr(pi, 0, 6, 0xa0 + j * 0x10);
242 for (k = 0; k < 256; k++) {
243 frpw_write_regr(pi, 0, 2, k ^ 0xaa);
244 frpw_write_regr(pi, 0, 3, k ^ 0x55);
245 if (frpw_read_regr(pi, 0, 2) != (k ^ 0xaa))
252 frpw_read_block_int(pi, scratch, 512, 0x10);
254 for (k = 0; k < 128; k++) {
261 "frpw: port 0x%x, chip %ld, mode %d, test=(%d,%d,%d)\n",
262 pi->port, (pi->private%2), pi->mode, e[0], e[1], r);
264 return r || (e[0] && e[1]);
267 static void frpw_log_adapter(struct pi_adapter *pi)
270 char *mode[6] = { "4-bit", "8-bit", "EPP", "EPP-8", "EPP-16", "EPP-32"};
273 "Freecom (%s) adapter at 0x%x, mode %d (%s), delay %d\n",
274 ((pi->private & 0x1) == 0) ? "Xilinx" : "ASIC",
275 pi->port, pi->mode, mode[pi->mode], pi->delay);
278 static struct pi_protocol frpw = {
279 .owner = THIS_MODULE,
285 .write_regr = frpw_write_regr,
286 .read_regr = frpw_read_regr,
287 .write_block = frpw_write_block,
288 .read_block = frpw_read_block,
289 .connect = frpw_connect,
290 .disconnect = frpw_disconnect,
291 .test_proto = frpw_test_proto,
292 .log_adapter = frpw_log_adapter,
295 MODULE_LICENSE("GPL");
296 MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
297 MODULE_DESCRIPTION("Freecom Power parallel port IDE adapter protocol driver");
298 module_pata_parport_driver(frpw);