2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 * An ATA driver for the legacy ATA ports.
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
34 * on PC class systems. There are three hybrid devices that are exceptions
35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
39 * opti82c465mv/promise 20230c/20630
41 * Use the autospeed and pio_mask options with:
42 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
45 * Winbond W83759A, Promise PDC20230-B
47 * For now use autospeed and pio_mask as above with the W83759A. This may
51 * Merge existing pata_qdi driver
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <scsi/scsi_host.h>
62 #include <linux/ata.h>
63 #include <linux/libata.h>
64 #include <linux/platform_device.h>
66 #define DRV_NAME "pata_legacy"
67 #define DRV_VERSION "0.5.5"
71 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
72 static int legacy_irq[NR_HOST] = { 14, 15, 11, 10, 8, 12 };
79 struct platform_device *platform_dev;
83 static struct legacy_data legacy_data[NR_HOST];
84 static struct ata_host *legacy_host[NR_HOST];
85 static int nr_legacy_host;
88 static int probe_all; /* Set to check all ISA port ranges */
89 static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */
90 static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */
91 static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */
92 static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */
93 static int autospeed; /* Chip present which snoops speed changes */
94 static int pio_mask = 0x1F; /* PIO range for autospeed devices */
95 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
98 * legacy_set_mode - mode setting
100 * @unused: Device that failed when error is returned
102 * Use a non standard set_mode function. We don't want to be tuned.
104 * The BIOS configured everything. Our job is not to fiddle. Just use
105 * whatever PIO the hardware is using and leave it at that. When we
106 * get some kind of nice user driven API for control then we can
107 * expand on this as per hdparm in the base kernel.
110 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
112 struct ata_device *dev;
114 ata_link_for_each_dev(dev, link) {
115 if (ata_dev_enabled(dev)) {
116 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n");
117 dev->pio_mode = XFER_PIO_0;
118 dev->xfer_mode = XFER_PIO_0;
119 dev->xfer_shift = ATA_SHIFT_PIO;
120 dev->flags |= ATA_DFLAG_PIO;
126 static struct scsi_host_template legacy_sht = {
127 .module = THIS_MODULE,
129 .ioctl = ata_scsi_ioctl,
130 .queuecommand = ata_scsi_queuecmd,
131 .can_queue = ATA_DEF_QUEUE,
132 .this_id = ATA_SHT_THIS_ID,
133 .sg_tablesize = LIBATA_MAX_PRD,
134 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
135 .emulated = ATA_SHT_EMULATED,
136 .use_clustering = ATA_SHT_USE_CLUSTERING,
137 .proc_name = DRV_NAME,
138 .dma_boundary = ATA_DMA_BOUNDARY,
139 .slave_configure = ata_scsi_slave_config,
140 .slave_destroy = ata_scsi_slave_destroy,
141 .bios_param = ata_std_bios_param,
145 * These ops are used if the user indicates the hardware
146 * snoops the commands to decide on the mode and handles the
147 * mode selection "magically" itself. Several legacy controllers
148 * do this. The mode range can be set if it is not 0x1F by setting
152 static struct ata_port_operations simple_port_ops = {
153 .port_disable = ata_port_disable,
154 .tf_load = ata_tf_load,
155 .tf_read = ata_tf_read,
156 .check_status = ata_check_status,
157 .exec_command = ata_exec_command,
158 .dev_select = ata_std_dev_select,
160 .freeze = ata_bmdma_freeze,
161 .thaw = ata_bmdma_thaw,
162 .error_handler = ata_bmdma_error_handler,
163 .post_internal_cmd = ata_bmdma_post_internal_cmd,
164 .cable_detect = ata_cable_40wire,
166 .qc_prep = ata_qc_prep,
167 .qc_issue = ata_qc_issue_prot,
169 .data_xfer = ata_data_xfer_noirq,
171 .irq_handler = ata_interrupt,
172 .irq_clear = ata_bmdma_irq_clear,
173 .irq_on = ata_irq_on,
175 .port_start = ata_port_start,
178 static struct ata_port_operations legacy_port_ops = {
179 .set_mode = legacy_set_mode,
181 .port_disable = ata_port_disable,
182 .tf_load = ata_tf_load,
183 .tf_read = ata_tf_read,
184 .check_status = ata_check_status,
185 .exec_command = ata_exec_command,
186 .dev_select = ata_std_dev_select,
187 .cable_detect = ata_cable_40wire,
189 .freeze = ata_bmdma_freeze,
190 .thaw = ata_bmdma_thaw,
191 .error_handler = ata_bmdma_error_handler,
192 .post_internal_cmd = ata_bmdma_post_internal_cmd,
194 .qc_prep = ata_qc_prep,
195 .qc_issue = ata_qc_issue_prot,
197 .data_xfer = ata_data_xfer_noirq,
199 .irq_handler = ata_interrupt,
200 .irq_clear = ata_bmdma_irq_clear,
201 .irq_on = ata_irq_on,
203 .port_start = ata_port_start,
207 * Promise 20230C and 20620 support
209 * This controller supports PIO0 to PIO2. We set PIO timings conservatively to
210 * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
211 * controller and PIO'd to the host and not supported.
214 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
217 int pio = adev->pio_mode - XFER_PIO_0;
221 /* Safe as UP only. Force I/Os to occur together */
223 local_irq_save(flags);
225 /* Unlock the control interface */
229 outb(inb(0x1F2) | 0x80, 0x1F2);
236 while((inb(0x1F2) & 0x80) && --tries);
238 local_irq_restore(flags);
240 outb(inb(0x1F4) & 0x07, 0x1F4);
243 rt &= 0x07 << (3 * adev->devno);
245 rt |= (1 + 3 * pio) << (3 * adev->devno);
248 outb(inb(0x1F2) | 0x01, 0x1F2);
254 static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
256 struct ata_port *ap = adev->link->ap;
257 int slop = buflen & 3;
260 if (ata_id_has_dword_io(adev->id)) {
261 local_irq_save(flags);
263 /* Perform the 32bit I/O synchronization sequence */
264 ioread8(ap->ioaddr.nsect_addr);
265 ioread8(ap->ioaddr.nsect_addr);
266 ioread8(ap->ioaddr.nsect_addr);
271 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
273 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
275 if (unlikely(slop)) {
278 memcpy(&pad, buf + buflen - slop, slop);
279 pad = le32_to_cpu(pad);
280 iowrite32(pad, ap->ioaddr.data_addr);
282 pad = ioread32(ap->ioaddr.data_addr);
283 pad = cpu_to_le16(pad);
284 memcpy(buf + buflen - slop, &pad, slop);
287 local_irq_restore(flags);
290 ata_data_xfer_noirq(adev, buf, buflen, write_data);
293 static struct ata_port_operations pdc20230_port_ops = {
294 .set_piomode = pdc20230_set_piomode,
296 .port_disable = ata_port_disable,
297 .tf_load = ata_tf_load,
298 .tf_read = ata_tf_read,
299 .check_status = ata_check_status,
300 .exec_command = ata_exec_command,
301 .dev_select = ata_std_dev_select,
303 .freeze = ata_bmdma_freeze,
304 .thaw = ata_bmdma_thaw,
305 .error_handler = ata_bmdma_error_handler,
306 .post_internal_cmd = ata_bmdma_post_internal_cmd,
307 .cable_detect = ata_cable_40wire,
309 .qc_prep = ata_qc_prep,
310 .qc_issue = ata_qc_issue_prot,
312 .data_xfer = pdc_data_xfer_vlb,
314 .irq_handler = ata_interrupt,
315 .irq_clear = ata_bmdma_irq_clear,
316 .irq_on = ata_irq_on,
318 .port_start = ata_port_start,
322 * Holtek 6560A support
324 * This controller supports PIO0 to PIO2 (no IORDY even though higher timings
328 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
333 /* Get the timing data in cycles. For now play safe at 50Mhz */
334 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
336 active = FIT(t.active, 2, 15);
337 recover = FIT(t.recover, 4, 15);
344 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
345 ioread8(ap->ioaddr.status_addr);
348 static struct ata_port_operations ht6560a_port_ops = {
349 .set_piomode = ht6560a_set_piomode,
351 .port_disable = ata_port_disable,
352 .tf_load = ata_tf_load,
353 .tf_read = ata_tf_read,
354 .check_status = ata_check_status,
355 .exec_command = ata_exec_command,
356 .dev_select = ata_std_dev_select,
358 .freeze = ata_bmdma_freeze,
359 .thaw = ata_bmdma_thaw,
360 .error_handler = ata_bmdma_error_handler,
361 .post_internal_cmd = ata_bmdma_post_internal_cmd,
362 .cable_detect = ata_cable_40wire,
364 .qc_prep = ata_qc_prep,
365 .qc_issue = ata_qc_issue_prot,
367 .data_xfer = ata_data_xfer, /* Check vlb/noirq */
369 .irq_handler = ata_interrupt,
370 .irq_clear = ata_bmdma_irq_clear,
371 .irq_on = ata_irq_on,
373 .port_start = ata_port_start,
377 * Holtek 6560B support
379 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
380 * unless we see an ATAPI device in which case we force it off.
382 * FIXME: need to implement 2nd channel support.
385 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
390 /* Get the timing data in cycles. For now play safe at 50Mhz */
391 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
393 active = FIT(t.active, 2, 15);
394 recover = FIT(t.recover, 2, 16);
402 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
404 if (adev->class != ATA_DEV_ATA) {
405 u8 rconf = inb(0x3E6);
411 ioread8(ap->ioaddr.status_addr);
414 static struct ata_port_operations ht6560b_port_ops = {
415 .set_piomode = ht6560b_set_piomode,
417 .port_disable = ata_port_disable,
418 .tf_load = ata_tf_load,
419 .tf_read = ata_tf_read,
420 .check_status = ata_check_status,
421 .exec_command = ata_exec_command,
422 .dev_select = ata_std_dev_select,
424 .freeze = ata_bmdma_freeze,
425 .thaw = ata_bmdma_thaw,
426 .error_handler = ata_bmdma_error_handler,
427 .post_internal_cmd = ata_bmdma_post_internal_cmd,
428 .cable_detect = ata_cable_40wire,
430 .qc_prep = ata_qc_prep,
431 .qc_issue = ata_qc_issue_prot,
433 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */
435 .irq_handler = ata_interrupt,
436 .irq_clear = ata_bmdma_irq_clear,
437 .irq_on = ata_irq_on,
439 .port_start = ata_port_start,
443 * Opti core chipset helpers
447 * opti_syscfg - read OPTI chipset configuration
448 * @reg: Configuration register to read
450 * Returns the value of an OPTI system board configuration register.
453 static u8 opti_syscfg(u8 reg)
458 /* Uniprocessor chipset and must force cycles adjancent */
459 local_irq_save(flags);
462 local_irq_restore(flags);
469 * This controller supports PIO0 to PIO3.
472 static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
474 u8 active, recover, setup;
476 struct ata_device *pair = ata_dev_pair(adev);
478 int khz[4] = { 50000, 40000, 33000, 25000 };
481 /* Enter configuration mode */
482 ioread16(ap->ioaddr.error_addr);
483 ioread16(ap->ioaddr.error_addr);
484 iowrite8(3, ap->ioaddr.nsect_addr);
486 /* Read VLB clock strapping */
487 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
489 /* Get the timing data in cycles */
490 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
492 /* Setup timing is shared */
494 struct ata_timing tp;
495 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
497 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
500 active = FIT(t.active, 2, 17) - 2;
501 recover = FIT(t.recover, 1, 16) - 1;
502 setup = FIT(t.setup, 1, 4) - 1;
504 /* Select the right timing bank for write timing */
505 rc = ioread8(ap->ioaddr.lbal_addr);
507 rc |= (adev->devno << 7);
508 iowrite8(rc, ap->ioaddr.lbal_addr);
510 /* Write the timings */
511 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
513 /* Select the right bank for read timings, also
514 load the shared timings for address */
515 rc = ioread8(ap->ioaddr.device_addr);
517 rc |= adev->devno; /* Index select */
518 rc |= (setup << 4) | 0x04;
519 iowrite8(rc, ap->ioaddr.device_addr);
521 /* Load the read timings */
522 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
524 /* Ensure the timing register mode is right */
525 rc = ioread8(ap->ioaddr.lbal_addr);
528 iowrite8(rc, ap->ioaddr.lbal_addr);
530 /* Exit command mode */
531 iowrite8(0x83, ap->ioaddr.nsect_addr);
535 static struct ata_port_operations opti82c611a_port_ops = {
536 .set_piomode = opti82c611a_set_piomode,
538 .port_disable = ata_port_disable,
539 .tf_load = ata_tf_load,
540 .tf_read = ata_tf_read,
541 .check_status = ata_check_status,
542 .exec_command = ata_exec_command,
543 .dev_select = ata_std_dev_select,
545 .freeze = ata_bmdma_freeze,
546 .thaw = ata_bmdma_thaw,
547 .error_handler = ata_bmdma_error_handler,
548 .post_internal_cmd = ata_bmdma_post_internal_cmd,
549 .cable_detect = ata_cable_40wire,
551 .qc_prep = ata_qc_prep,
552 .qc_issue = ata_qc_issue_prot,
554 .data_xfer = ata_data_xfer,
556 .irq_handler = ata_interrupt,
557 .irq_clear = ata_bmdma_irq_clear,
558 .irq_on = ata_irq_on,
560 .port_start = ata_port_start,
566 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
567 * version is dual channel but doesn't have a lot of unique registers.
570 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
572 u8 active, recover, setup;
574 struct ata_device *pair = ata_dev_pair(adev);
576 int khz[4] = { 50000, 40000, 33000, 25000 };
581 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
583 /* Enter configuration mode */
584 ioread16(ap->ioaddr.error_addr);
585 ioread16(ap->ioaddr.error_addr);
586 iowrite8(3, ap->ioaddr.nsect_addr);
588 /* Read VLB clock strapping */
589 clock = 1000000000 / khz[sysclk];
591 /* Get the timing data in cycles */
592 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
594 /* Setup timing is shared */
596 struct ata_timing tp;
597 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
599 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
602 active = FIT(t.active, 2, 17) - 2;
603 recover = FIT(t.recover, 1, 16) - 1;
604 setup = FIT(t.setup, 1, 4) - 1;
606 /* Select the right timing bank for write timing */
607 rc = ioread8(ap->ioaddr.lbal_addr);
609 rc |= (adev->devno << 7);
610 iowrite8(rc, ap->ioaddr.lbal_addr);
612 /* Write the timings */
613 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
615 /* Select the right bank for read timings, also
616 load the shared timings for address */
617 rc = ioread8(ap->ioaddr.device_addr);
619 rc |= adev->devno; /* Index select */
620 rc |= (setup << 4) | 0x04;
621 iowrite8(rc, ap->ioaddr.device_addr);
623 /* Load the read timings */
624 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
626 /* Ensure the timing register mode is right */
627 rc = ioread8(ap->ioaddr.lbal_addr);
630 iowrite8(rc, ap->ioaddr.lbal_addr);
632 /* Exit command mode */
633 iowrite8(0x83, ap->ioaddr.nsect_addr);
635 /* We need to know this for quad device on the MVB */
636 ap->host->private_data = ap;
640 * opt82c465mv_qc_issue_prot - command issue
641 * @qc: command pending
643 * Called when the libata layer is about to issue a command. We wrap
644 * this interface so that we can load the correct ATA timings. The
645 * MVB has a single set of timing registers and these are shared
646 * across channels. As there are two registers we really ought to
647 * track the last two used values as a sort of register window. For
648 * now we just reload on a channel switch. On the single channel
649 * setup this condition never fires so we do nothing extra.
651 * FIXME: dual channel needs ->serialize support
654 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
656 struct ata_port *ap = qc->ap;
657 struct ata_device *adev = qc->dev;
659 /* If timings are set and for the wrong channel (2nd test is
660 due to a libata shortcoming and will eventually go I hope) */
661 if (ap->host->private_data != ap->host
662 && ap->host->private_data != NULL)
663 opti82c46x_set_piomode(ap, adev);
665 return ata_qc_issue_prot(qc);
668 static struct ata_port_operations opti82c46x_port_ops = {
669 .set_piomode = opti82c46x_set_piomode,
671 .port_disable = ata_port_disable,
672 .tf_load = ata_tf_load,
673 .tf_read = ata_tf_read,
674 .check_status = ata_check_status,
675 .exec_command = ata_exec_command,
676 .dev_select = ata_std_dev_select,
678 .freeze = ata_bmdma_freeze,
679 .thaw = ata_bmdma_thaw,
680 .error_handler = ata_bmdma_error_handler,
681 .post_internal_cmd = ata_bmdma_post_internal_cmd,
682 .cable_detect = ata_cable_40wire,
684 .qc_prep = ata_qc_prep,
685 .qc_issue = opti82c46x_qc_issue_prot,
687 .data_xfer = ata_data_xfer,
689 .irq_handler = ata_interrupt,
690 .irq_clear = ata_bmdma_irq_clear,
691 .irq_on = ata_irq_on,
693 .port_start = ata_port_start,
698 * legacy_init_one - attach a legacy interface
700 * @io: I/O port start
701 * @ctrl: control port
702 * @irq: interrupt line
704 * Register an ISA bus IDE interface. Such interfaces are PIO and we
705 * assume do not support IRQ sharing.
708 static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
710 struct legacy_data *ld = &legacy_data[nr_legacy_host];
711 struct ata_host *host;
713 struct platform_device *pdev;
714 struct ata_port_operations *ops = &legacy_port_ops;
715 void __iomem *io_addr, *ctrl_addr;
716 int pio_modes = pio_mask;
717 u32 mask = (1 << port);
718 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
721 pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
723 return PTR_ERR(pdev);
726 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
727 devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL)
731 io_addr = devm_ioport_map(&pdev->dev, io, 8);
732 ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1);
733 if (!io_addr || !ctrl_addr)
736 if (ht6560a & mask) {
737 ops = &ht6560a_port_ops;
739 iordy = ATA_FLAG_NO_IORDY;
741 if (ht6560b & mask) {
742 ops = &ht6560b_port_ops;
745 if (opti82c611a & mask) {
746 ops = &opti82c611a_port_ops;
749 if (opti82c46x & mask) {
750 ops = &opti82c46x_port_ops;
754 /* Probe for automatically detectable controllers */
756 if (io == 0x1F0 && ops == &legacy_port_ops) {
759 local_irq_save(flags);
763 outb(inb(0x1F2) | 0x80, 0x1F2);
770 if ((inb(0x1F2) & 0x80) == 0) {
771 /* PDC20230c or 20630 ? */
772 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
774 ops = &pdc20230_port_ops;
775 iordy = ATA_FLAG_NO_IORDY;
782 if (inb(0x1F2) == 0x00) {
783 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
786 local_irq_restore(flags);
790 /* Chip does mode setting by command snooping */
791 if (ops == &legacy_port_ops && (autospeed & mask))
792 ops = &simple_port_ops;
795 host = ata_host_alloc(&pdev->dev, 1);
801 ap->pio_mask = pio_modes;
802 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
803 ap->ioaddr.cmd_addr = io_addr;
804 ap->ioaddr.altstatus_addr = ctrl_addr;
805 ap->ioaddr.ctl_addr = ctrl_addr;
806 ata_std_ports(&ap->ioaddr);
807 ap->private_data = ld;
809 ret = ata_host_activate(host, irq, ata_interrupt, 0, &legacy_sht);
813 legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
814 ld->platform_dev = pdev;
818 platform_device_unregister(pdev);
823 * legacy_check_special_cases - ATA special cases
824 * @p: PCI device to check
825 * @master: set this if we find an ATA master
826 * @master: set this if we find an ATA secondary
828 * A small number of vendors implemented early PCI ATA interfaces on bridge logic
829 * without the ATA interface being PCI visible. Where we have a matching PCI driver
830 * we must skip the relevant device here. If we don't know about it then the legacy
831 * driver is the right driver anyway.
834 static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
836 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
837 if (p->vendor == 0x1078 && p->device == 0x0000) {
838 *primary = *secondary = 1;
841 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
842 if (p->vendor == 0x1078 && p->device == 0x0002) {
843 *primary = *secondary = 1;
846 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
847 if (p->vendor == 0x8086 && p->device == 0x1234) {
849 pci_read_config_word(p, 0x6C, &r);
850 if (r & 0x8000) { /* ATA port enabled */
862 * legacy_init - attach legacy interfaces
864 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
865 * Right now we do not scan the ide0 and ide1 address but should do so
866 * for non PCI systems or systems with no PCI IDE legacy mode devices.
867 * If you fix that note there are special cases to consider like VLB
868 * drivers and CS5510/20.
871 static __init int legacy_init(void)
877 int last_port = NR_HOST;
879 struct pci_dev *p = NULL;
881 for_each_pci_dev(p) {
883 /* Check for any overlap of the system ATA mappings. Native mode controllers
884 stuck on these addresses or some devices in 'raid' mode won't be found by
885 the storage class test */
886 for (r = 0; r < 6; r++) {
887 if (pci_resource_start(p, r) == 0x1f0)
889 if (pci_resource_start(p, r) == 0x170)
892 /* Check for special cases */
893 legacy_check_special_cases(p, &primary, &secondary);
895 /* If PCI bus is present then don't probe for tertiary legacy ports */
900 /* If an OPTI 82C46X is present find out where the channels are */
902 static const char *optis[4] = {
907 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
909 opti82c46x = 3; /* Assume master and slave first */
910 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
912 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
913 ctrl = opti_syscfg(0xAC);
914 /* Check enabled and this port is the 465MV port. On the
915 MVB we may have two channels */
918 opti82c46x = 2; /* Slave */
920 opti82c46x = 1; /* Master */
922 opti82c46x = 3; /* Master and Slave */
928 for (i = 0; i < last_port; i++) {
929 /* Skip primary if we have seen a PCI one */
930 if (i == 0 && primary == 1)
932 /* Skip secondary if we have seen a PCI one */
933 if (i == 1 && secondary == 1)
935 if (legacy_init_one(i, legacy_port[i],
936 legacy_port[i] + 0x0206,
945 static __exit void legacy_exit(void)
949 for (i = 0; i < nr_legacy_host; i++) {
950 struct legacy_data *ld = &legacy_data[i];
952 ata_host_detach(legacy_host[i]);
953 platform_device_unregister(ld->platform_dev);
955 release_region(ld->timing, 2);
959 MODULE_AUTHOR("Alan Cox");
960 MODULE_DESCRIPTION("low-level driver for legacy ATA");
961 MODULE_LICENSE("GPL");
962 MODULE_VERSION(DRV_VERSION);
964 module_param(probe_all, int, 0);
965 module_param(autospeed, int, 0);
966 module_param(ht6560a, int, 0);
967 module_param(ht6560b, int, 0);
968 module_param(opti82c611a, int, 0);
969 module_param(opti82c46x, int, 0);
970 module_param(pio_mask, int, 0);
971 module_param(iordy_mask, int, 0);
973 module_init(legacy_init);
974 module_exit(legacy_exit);