1 // SPDX-License-Identifier: GPL-2.0-only
3 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
5 * This driver is heavily based upon:
7 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
10 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
11 * Portions Copyright (C) 2003 Red Hat Inc
12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
15 * Look into engine reset on timeout errors. Should not be required.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/blkdev.h>
21 #include <linux/delay.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
25 #define DRV_NAME "pata_hpt37x"
26 #define DRV_VERSION "0.6.23"
36 struct hpt_clock const *clocks[4];
39 /* key for bus clock timings
41 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
43 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
45 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
47 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
49 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
50 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
51 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
52 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
56 * 30 PIO_MST enable. If set, the chip is in bus master mode during
58 * 31 FIFO enable. Only for PIO.
61 static struct hpt_clock hpt37x_timings_33[] = {
62 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
63 { XFER_UDMA_5, 0x12446231 },
64 { XFER_UDMA_4, 0x12446231 },
65 { XFER_UDMA_3, 0x126c6231 },
66 { XFER_UDMA_2, 0x12486231 },
67 { XFER_UDMA_1, 0x124c6233 },
68 { XFER_UDMA_0, 0x12506297 },
70 { XFER_MW_DMA_2, 0x22406c31 },
71 { XFER_MW_DMA_1, 0x22406c33 },
72 { XFER_MW_DMA_0, 0x22406c97 },
74 { XFER_PIO_4, 0x06414e31 },
75 { XFER_PIO_3, 0x06414e42 },
76 { XFER_PIO_2, 0x06414e53 },
77 { XFER_PIO_1, 0x06814e93 },
78 { XFER_PIO_0, 0x06814ea7 }
81 static struct hpt_clock hpt37x_timings_50[] = {
82 { XFER_UDMA_6, 0x12848242 },
83 { XFER_UDMA_5, 0x12848242 },
84 { XFER_UDMA_4, 0x12ac8242 },
85 { XFER_UDMA_3, 0x128c8242 },
86 { XFER_UDMA_2, 0x120c8242 },
87 { XFER_UDMA_1, 0x12148254 },
88 { XFER_UDMA_0, 0x121882ea },
90 { XFER_MW_DMA_2, 0x22808242 },
91 { XFER_MW_DMA_1, 0x22808254 },
92 { XFER_MW_DMA_0, 0x228082ea },
94 { XFER_PIO_4, 0x0a81f442 },
95 { XFER_PIO_3, 0x0a81f443 },
96 { XFER_PIO_2, 0x0a81f454 },
97 { XFER_PIO_1, 0x0ac1f465 },
98 { XFER_PIO_0, 0x0ac1f48a }
101 static struct hpt_clock hpt37x_timings_66[] = {
102 { XFER_UDMA_6, 0x1c869c62 },
103 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
104 { XFER_UDMA_4, 0x1c8a9c62 },
105 { XFER_UDMA_3, 0x1c8e9c62 },
106 { XFER_UDMA_2, 0x1c929c62 },
107 { XFER_UDMA_1, 0x1c9a9c62 },
108 { XFER_UDMA_0, 0x1c829c62 },
110 { XFER_MW_DMA_2, 0x2c829c62 },
111 { XFER_MW_DMA_1, 0x2c829c66 },
112 { XFER_MW_DMA_0, 0x2c829d2e },
114 { XFER_PIO_4, 0x0c829c62 },
115 { XFER_PIO_3, 0x0c829c84 },
116 { XFER_PIO_2, 0x0c829ca6 },
117 { XFER_PIO_1, 0x0d029d26 },
118 { XFER_PIO_0, 0x0d029d5e }
122 static const struct hpt_chip hpt370 = {
133 static const struct hpt_chip hpt370a = {
144 static const struct hpt_chip hpt372 = {
155 static const struct hpt_chip hpt302 = {
166 static const struct hpt_chip hpt371 = {
177 static const struct hpt_chip hpt372a = {
188 static const struct hpt_chip hpt374 = {
200 * hpt37x_find_mode - reset the hpt37x bus
202 * @speed: transfer mode
204 * Return the 32bit register programming information for this channel
205 * that matches the speed provided.
208 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
210 struct hpt_clock *clocks = ap->host->private_data;
212 while (clocks->xfer_speed) {
213 if (clocks->xfer_speed == speed)
214 return clocks->timing;
218 return 0xffffffffU; /* silence compiler warning */
221 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
222 const char * const list[])
224 unsigned char model_num[ATA_ID_PROD_LEN + 1];
227 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
229 i = match_string(list, -1, model_num);
231 ata_dev_warn(dev, "%s is not supported for %s\n",
238 static const char * const bad_ata33[] = {
239 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
240 "Maxtor 90845U3", "Maxtor 90650U2",
241 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
242 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
243 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
244 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
248 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
249 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
250 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
254 static const char * const bad_ata100_5[] = {
274 * hpt370_filter - mode selection filter
278 * Block UDMA on devices that cause trouble with this controller.
281 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
283 if (adev->class == ATA_DEV_ATA) {
284 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
285 mask &= ~ATA_MASK_UDMA;
286 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
287 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
293 * hpt370a_filter - mode selection filter
297 * Block UDMA on devices that cause trouble with this controller.
300 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
302 if (adev->class == ATA_DEV_ATA) {
303 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
304 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
310 * hpt372_filter - mode selection filter
314 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
315 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
317 static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
319 if (ata_id_is_sata(adev->id))
320 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
326 * hpt37x_cable_detect - Detect the cable type
327 * @ap: ATA port to detect on
329 * Return the cable type attached to this port
332 static int hpt37x_cable_detect(struct ata_port *ap)
334 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
337 pci_read_config_byte(pdev, 0x5B, &scr2);
338 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
340 udelay(10); /* debounce */
342 /* Cable register now active */
343 pci_read_config_byte(pdev, 0x5A, &ata66);
345 pci_write_config_byte(pdev, 0x5B, scr2);
347 if (ata66 & (2 >> ap->port_no))
348 return ATA_CBL_PATA40;
350 return ATA_CBL_PATA80;
354 * hpt374_fn1_cable_detect - Detect the cable type
355 * @ap: ATA port to detect on
357 * Return the cable type attached to this port
360 static int hpt374_fn1_cable_detect(struct ata_port *ap)
362 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
363 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
367 /* Do the extra channel work */
368 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
369 /* Set bit 15 of 0x52 to enable TCBLID as input */
370 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
371 pci_read_config_byte(pdev, 0x5A, &ata66);
372 /* Reset TCBLID/FCBLID to output */
373 pci_write_config_word(pdev, mcrbase + 2, mcr3);
375 if (ata66 & (2 >> ap->port_no))
376 return ATA_CBL_PATA40;
378 return ATA_CBL_PATA80;
382 * hpt37x_pre_reset - reset the hpt37x bus
383 * @link: ATA link to reset
384 * @deadline: deadline jiffies for the operation
386 * Perform the initial reset handling for the HPT37x.
389 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
391 struct ata_port *ap = link->ap;
392 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
393 static const struct pci_bits hpt37x_enable_bits[] = {
394 { 0x50, 1, 0x04, 0x04 },
395 { 0x54, 1, 0x04, 0x04 }
398 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
401 /* Reset the state machine */
402 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
405 return ata_sff_prereset(link, deadline);
408 static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
411 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
413 u32 reg, timing, mask;
416 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
417 addr2 = 0x51 + 4 * ap->port_no;
419 /* Fast interrupt prediction disable, hold off interrupt disable */
420 pci_read_config_byte(pdev, addr2, &fast);
423 pci_write_config_byte(pdev, addr2, fast);
425 /* Determine timing mask and find matching mode entry */
426 if (mode < XFER_MW_DMA_0)
428 else if (mode < XFER_UDMA_0)
433 timing = hpt37x_find_mode(ap, mode);
435 pci_read_config_dword(pdev, addr1, ®);
436 reg = (reg & ~mask) | (timing & mask);
437 pci_write_config_dword(pdev, addr1, reg);
440 * hpt370_set_piomode - PIO setup
442 * @adev: device on the interface
444 * Perform PIO mode setup.
447 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
449 hpt370_set_mode(ap, adev, adev->pio_mode);
453 * hpt370_set_dmamode - DMA timing setup
455 * @adev: Device being configured
457 * Set up the channel for MWDMA or UDMA modes.
460 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
462 hpt370_set_mode(ap, adev, adev->dma_mode);
466 * hpt370_bmdma_stop - DMA engine stop
469 * Work around the HPT370 DMA engine.
472 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
474 struct ata_port *ap = qc->ap;
475 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
476 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
477 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
480 if (dma_stat & ATA_DMA_ACTIVE) {
482 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
484 if (dma_stat & ATA_DMA_ACTIVE) {
485 /* Clear the engine */
486 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
489 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
490 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
492 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
493 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
494 bmdma + ATA_DMA_STATUS);
495 /* Clear the engine */
496 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
502 static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
505 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
507 u32 reg, timing, mask;
510 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
511 addr2 = 0x51 + 4 * ap->port_no;
513 /* Fast interrupt prediction disable, hold off interrupt disable */
514 pci_read_config_byte(pdev, addr2, &fast);
516 pci_write_config_byte(pdev, addr2, fast);
518 /* Determine timing mask and find matching mode entry */
519 if (mode < XFER_MW_DMA_0)
521 else if (mode < XFER_UDMA_0)
526 timing = hpt37x_find_mode(ap, mode);
528 pci_read_config_dword(pdev, addr1, ®);
529 reg = (reg & ~mask) | (timing & mask);
530 pci_write_config_dword(pdev, addr1, reg);
534 * hpt372_set_piomode - PIO setup
536 * @adev: device on the interface
538 * Perform PIO mode setup.
541 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
543 hpt372_set_mode(ap, adev, adev->pio_mode);
547 * hpt372_set_dmamode - DMA timing setup
549 * @adev: Device being configured
551 * Set up the channel for MWDMA or UDMA modes.
554 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
556 hpt372_set_mode(ap, adev, adev->dma_mode);
560 * hpt37x_bmdma_stop - DMA engine stop
563 * Clean up after the HPT372 and later DMA engine
566 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
568 struct ata_port *ap = qc->ap;
569 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
570 int mscreg = 0x50 + 4 * ap->port_no;
571 u8 bwsr_stat, msc_stat;
573 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
574 pci_read_config_byte(pdev, mscreg, &msc_stat);
575 if (bwsr_stat & (1 << ap->port_no))
576 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
581 static struct scsi_host_template hpt37x_sht = {
582 ATA_BMDMA_SHT(DRV_NAME),
586 * Configuration for HPT370
589 static struct ata_port_operations hpt370_port_ops = {
590 .inherits = &ata_bmdma_port_ops,
592 .bmdma_stop = hpt370_bmdma_stop,
594 .mode_filter = hpt370_filter,
595 .cable_detect = hpt37x_cable_detect,
596 .set_piomode = hpt370_set_piomode,
597 .set_dmamode = hpt370_set_dmamode,
598 .prereset = hpt37x_pre_reset,
602 * Configuration for HPT370A. Close to 370 but less filters
605 static struct ata_port_operations hpt370a_port_ops = {
606 .inherits = &hpt370_port_ops,
607 .mode_filter = hpt370a_filter,
611 * Configuration for HPT371 and HPT302. Slightly different PIO and DMA
612 * mode setting functionality.
615 static struct ata_port_operations hpt302_port_ops = {
616 .inherits = &ata_bmdma_port_ops,
618 .bmdma_stop = hpt37x_bmdma_stop,
620 .cable_detect = hpt37x_cable_detect,
621 .set_piomode = hpt372_set_piomode,
622 .set_dmamode = hpt372_set_dmamode,
623 .prereset = hpt37x_pre_reset,
627 * Configuration for HPT372. Mode setting works like 371 and 302
628 * but we have a mode filter.
631 static struct ata_port_operations hpt372_port_ops = {
632 .inherits = &hpt302_port_ops,
633 .mode_filter = hpt372_filter,
637 * Configuration for HPT374. Mode setting and filtering works like 372
638 * but we have a different cable detection procedure for function 1.
641 static struct ata_port_operations hpt374_fn1_port_ops = {
642 .inherits = &hpt372_port_ops,
643 .cable_detect = hpt374_fn1_cable_detect,
647 * hpt37x_clock_slot - Turn timing to PC clock entry
648 * @freq: Reported frequency timing
651 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
655 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
657 unsigned int f = (base * freq) / 192; /* Mhz */
659 return 0; /* 33Mhz slot */
661 return 1; /* 40Mhz slot */
663 return 2; /* 50Mhz slot */
664 return 3; /* 60Mhz slot */
668 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
671 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
675 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
681 for (tries = 0; tries < 0x5000; tries++) {
683 pci_read_config_byte(dev, 0x5b, ®5b);
685 /* See if it stays set */
686 for (tries = 0; tries < 0x1000; tries++) {
687 pci_read_config_byte(dev, 0x5b, ®5b);
689 if ((reg5b & 0x80) == 0)
692 /* Turn off tuning, we have the DPLL set */
693 pci_read_config_dword(dev, 0x5c, ®5c);
694 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
698 /* Never went stable */
702 static u32 hpt374_read_freq(struct pci_dev *pdev)
705 unsigned long io_base = pci_resource_start(pdev, 4);
707 if (PCI_FUNC(pdev->devfn) & 1) {
708 struct pci_dev *pdev_0;
710 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
711 /* Someone hot plugged the controller on us ? */
714 io_base = pci_resource_start(pdev_0, 4);
715 freq = inl(io_base + 0x90);
718 freq = inl(io_base + 0x90);
723 * hpt37x_init_one - Initialise an HPT37X/302
725 * @id: Entry in match table
727 * Initialise an HPT37x device. There are some interesting complications
728 * here. Firstly the chip may report 366 and be one of several variants.
729 * Secondly all the timings depend on the clock for the chip which we must
732 * This is the known chip mappings. It may be missing a couple of later
735 * Chip version PCI Rev Notes
736 * HPT366 4 (HPT366) 0 Other driver
737 * HPT366 4 (HPT366) 1 Other driver
738 * HPT368 4 (HPT366) 2 Other driver
739 * HPT370 4 (HPT366) 3 UDMA100
740 * HPT370A 4 (HPT366) 4 UDMA100
741 * HPT372 4 (HPT366) 5 UDMA133 (1)
742 * HPT372N 4 (HPT366) 6 Other driver
743 * HPT372A 5 (HPT372) 1 UDMA133 (1)
744 * HPT372N 5 (HPT372) 2 Other driver
745 * HPT302 6 (HPT302) 1 UDMA133
746 * HPT302N 6 (HPT302) 2 Other driver
747 * HPT371 7 (HPT371) * UDMA133
748 * HPT374 8 (HPT374) * UDMA133 4 channel
749 * HPT372N 9 (HPT372N) * Other driver
751 * (1) UDMA133 support depends on the bus clock
754 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
756 /* HPT370 - UDMA100 */
757 static const struct ata_port_info info_hpt370 = {
758 .flags = ATA_FLAG_SLAVE_POSS,
759 .pio_mask = ATA_PIO4,
760 .mwdma_mask = ATA_MWDMA2,
761 .udma_mask = ATA_UDMA5,
762 .port_ops = &hpt370_port_ops
764 /* HPT370A - UDMA100 */
765 static const struct ata_port_info info_hpt370a = {
766 .flags = ATA_FLAG_SLAVE_POSS,
767 .pio_mask = ATA_PIO4,
768 .mwdma_mask = ATA_MWDMA2,
769 .udma_mask = ATA_UDMA5,
770 .port_ops = &hpt370a_port_ops
772 /* HPT370 - UDMA66 */
773 static const struct ata_port_info info_hpt370_33 = {
774 .flags = ATA_FLAG_SLAVE_POSS,
775 .pio_mask = ATA_PIO4,
776 .mwdma_mask = ATA_MWDMA2,
777 .udma_mask = ATA_UDMA4,
778 .port_ops = &hpt370_port_ops
780 /* HPT370A - UDMA66 */
781 static const struct ata_port_info info_hpt370a_33 = {
782 .flags = ATA_FLAG_SLAVE_POSS,
783 .pio_mask = ATA_PIO4,
784 .mwdma_mask = ATA_MWDMA2,
785 .udma_mask = ATA_UDMA4,
786 .port_ops = &hpt370a_port_ops
788 /* HPT372 - UDMA133 */
789 static const struct ata_port_info info_hpt372 = {
790 .flags = ATA_FLAG_SLAVE_POSS,
791 .pio_mask = ATA_PIO4,
792 .mwdma_mask = ATA_MWDMA2,
793 .udma_mask = ATA_UDMA6,
794 .port_ops = &hpt372_port_ops
796 /* HPT371, 302 - UDMA133 */
797 static const struct ata_port_info info_hpt302 = {
798 .flags = ATA_FLAG_SLAVE_POSS,
799 .pio_mask = ATA_PIO4,
800 .mwdma_mask = ATA_MWDMA2,
801 .udma_mask = ATA_UDMA6,
802 .port_ops = &hpt302_port_ops
804 /* HPT374 - UDMA100, function 1 uses different cable_detect method */
805 static const struct ata_port_info info_hpt374_fn0 = {
806 .flags = ATA_FLAG_SLAVE_POSS,
807 .pio_mask = ATA_PIO4,
808 .mwdma_mask = ATA_MWDMA2,
809 .udma_mask = ATA_UDMA5,
810 .port_ops = &hpt372_port_ops
812 static const struct ata_port_info info_hpt374_fn1 = {
813 .flags = ATA_FLAG_SLAVE_POSS,
814 .pio_mask = ATA_PIO4,
815 .mwdma_mask = ATA_MWDMA2,
816 .udma_mask = ATA_UDMA5,
817 .port_ops = &hpt374_fn1_port_ops
820 static const int MHz[4] = { 33, 40, 50, 66 };
821 void *private_data = NULL;
822 const struct ata_port_info *ppi[] = { NULL, NULL };
823 u8 rev = dev->revision;
829 unsigned long iobase = pci_resource_start(dev, 4);
831 const struct hpt_chip *chip_table;
835 rc = pcim_enable_device(dev);
839 switch (dev->device) {
840 case PCI_DEVICE_ID_TTI_HPT366:
841 /* May be a later chip in disguise. Check */
842 /* Older chips are in the HPT366 driver. Ignore them */
845 /* N series chips have their own driver. Ignore */
851 ppi[0] = &info_hpt370;
852 chip_table = &hpt370;
856 ppi[0] = &info_hpt370a;
857 chip_table = &hpt370a;
861 ppi[0] = &info_hpt372;
862 chip_table = &hpt372;
866 "Unknown HPT366 subtype, please report (%d)\n",
871 case PCI_DEVICE_ID_TTI_HPT372:
872 /* 372N if rev >= 2 */
875 ppi[0] = &info_hpt372;
876 chip_table = &hpt372a;
878 case PCI_DEVICE_ID_TTI_HPT302:
879 /* 302N if rev > 1 */
882 ppi[0] = &info_hpt302;
884 chip_table = &hpt302;
886 case PCI_DEVICE_ID_TTI_HPT371:
889 ppi[0] = &info_hpt302;
890 chip_table = &hpt371;
892 * Single channel device, master is not present but the BIOS
893 * (or us for non x86) must mark it absent
895 pci_read_config_byte(dev, 0x50, &mcr1);
897 pci_write_config_byte(dev, 0x50, mcr1);
899 case PCI_DEVICE_ID_TTI_HPT374:
900 chip_table = &hpt374;
901 if (!(PCI_FUNC(dev->devfn) & 1))
902 *ppi = &info_hpt374_fn0;
904 *ppi = &info_hpt374_fn1;
907 dev_err(&dev->dev, "PCI table is bogus, please report (%d)\n",
911 /* Ok so this is a chip we support */
913 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
914 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
915 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
916 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
918 pci_read_config_byte(dev, 0x5A, &irqmask);
920 pci_write_config_byte(dev, 0x5a, irqmask);
923 * HPT371 chips physically have only one channel, the secondary one,
924 * but the primary channel registers do exist! Go figure...
925 * So, we manually disable the non-existing channel here
926 * (if the BIOS hasn't done this already).
928 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
931 pci_read_config_byte(dev, 0x50, &mcr1);
933 pci_write_config_byte(dev, 0x50, mcr1);
937 * default to pci clock. make sure MA15/16 are set to output
938 * to prevent drives having problems with 40-pin cables. Needed
939 * for some drives such as IBM-DTLA which will not enter ready
940 * state on reset when PDIAG is a input.
943 pci_write_config_byte(dev, 0x5b, 0x23);
946 * HighPoint does this for HPT372A.
947 * NOTE: This register is only writeable via I/O space.
949 if (chip_table == &hpt372a)
950 outb(0x0e, iobase + 0x9c);
953 * Some devices do not let this value be accessed via PCI space
954 * according to the old driver. In addition we must use the value
955 * from FN 0 on the HPT374.
958 if (chip_table == &hpt374) {
959 freq = hpt374_read_freq(dev);
963 freq = inl(iobase + 0x90);
965 if ((freq >> 12) != 0xABCDE) {
970 dev_warn(&dev->dev, "BIOS has not set timing clocks\n");
972 /* This is the process the HPT371 BIOS is reported to use */
973 for (i = 0; i < 128; i++) {
974 pci_read_config_word(dev, 0x78, &sr);
983 * Turn the frequency check into a band and then find a timing
987 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
988 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
990 * We need to try PLL mode instead
992 * For non UDMA133 capable devices we should
993 * use a 50MHz DPLL by choice
995 unsigned int f_low, f_high;
999 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
1001 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
1006 /* Select the DPLL clock. */
1007 pci_write_config_byte(dev, 0x5b, 0x21);
1008 pci_write_config_dword(dev, 0x5C,
1009 (f_high << 16) | f_low | 0x100);
1011 for (adjust = 0; adjust < 8; adjust++) {
1012 if (hpt37x_calibrate_dpll(dev))
1015 * See if it'll settle at a fractionally
1019 f_low -= adjust >> 1;
1021 f_high += adjust >> 1;
1022 pci_write_config_dword(dev, 0x5C,
1023 (f_high << 16) | f_low | 0x100);
1026 dev_err(&dev->dev, "DPLL did not stabilize!\n");
1030 private_data = (void *)hpt37x_timings_66;
1032 private_data = (void *)hpt37x_timings_50;
1034 dev_info(&dev->dev, "bus clock %dMHz, using %dMHz DPLL\n",
1035 MHz[clock_slot], MHz[dpll]);
1037 private_data = (void *)chip_table->clocks[clock_slot];
1039 * Perform a final fixup. Note that we will have used the
1040 * DPLL on the HPT372 which means we don't have to worry
1041 * about lack of UDMA133 support on lower clocks
1044 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1045 ppi[0] = &info_hpt370_33;
1046 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1047 ppi[0] = &info_hpt370a_33;
1049 dev_info(&dev->dev, "%s using %dMHz bus clock\n",
1050 chip_table->name, MHz[clock_slot]);
1053 /* Now kick off ATA set up */
1054 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
1057 static const struct pci_device_id hpt37x[] = {
1058 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1059 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1060 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1061 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1062 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1067 static struct pci_driver hpt37x_pci_driver = {
1070 .probe = hpt37x_init_one,
1071 .remove = ata_pci_remove_one
1074 module_pci_driver(hpt37x_pci_driver);
1076 MODULE_AUTHOR("Alan Cox");
1077 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1078 MODULE_LICENSE("GPL");
1079 MODULE_DEVICE_TABLE(pci, hpt37x);
1080 MODULE_VERSION(DRV_VERSION);