drivers/ata/ahci_imx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * copyright (c) 2013 Freescale Semiconductor, Inc.
   4  * Freescale IMX AHCI SATA platform driver
   5  *
   6  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/property.h>
  13 #include <linux/regmap.h>
  14 #include <linux/ahci_platform.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/of.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  19 #include <linux/libata.h>
  20 #include <linux/hwmon.h>
  21 #include <linux/hwmon-sysfs.h>
  22 #include <linux/thermal.h>
  23 #include "ahci.h"
  24
  25 #define DRV_NAME "ahci-imx"
  26
  27 enum {
  28         /* Timer 1-ms Register */
  29         IMX_TIMER1MS                            = 0x00e0,
  30         /* Port0 PHY Control Register */
  31         IMX_P0PHYCR                             = 0x0178,
  32         IMX_P0PHYCR_TEST_PDDQ                   = 1 << 20,
  33         IMX_P0PHYCR_CR_READ                     = 1 << 19,
  34         IMX_P0PHYCR_CR_WRITE                    = 1 << 18,
  35         IMX_P0PHYCR_CR_CAP_DATA                 = 1 << 17,
  36         IMX_P0PHYCR_CR_CAP_ADDR                 = 1 << 16,
  37         /* Port0 PHY Status Register */
  38         IMX_P0PHYSR                             = 0x017c,
  39         IMX_P0PHYSR_CR_ACK                      = 1 << 18,
  40         IMX_P0PHYSR_CR_DATA_OUT                 = 0xffff << 0,
  41         /* Lane0 Output Status Register */
  42         IMX_LANE0_OUT_STAT                      = 0x2003,
  43         IMX_LANE0_OUT_STAT_RX_PLL_STATE         = 1 << 1,
  44         /* Clock Reset Register */
  45         IMX_CLOCK_RESET                         = 0x7f3f,
  46         IMX_CLOCK_RESET_RESET                   = 1 << 0,
  47         /* IMX8QM HSIO AHCI definitions */
  48         IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET   = 0x03,
  49         IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET   = 0x09,
  50         IMX8QM_SATA_PHY_IMPED_RATIO_85OHM       = 0x6c,
  51         IMX8QM_LPCG_PHYX2_OFFSET                = 0x00000,
  52         IMX8QM_CSR_PHYX2_OFFSET                 = 0x90000,
  53         IMX8QM_CSR_PHYX1_OFFSET                 = 0xa0000,
  54         IMX8QM_CSR_PHYX_STTS0_OFFSET            = 0x4,
  55         IMX8QM_CSR_PCIEA_OFFSET                 = 0xb0000,
  56         IMX8QM_CSR_PCIEB_OFFSET                 = 0xc0000,
  57         IMX8QM_CSR_SATA_OFFSET                  = 0xd0000,
  58         IMX8QM_CSR_PCIE_CTRL2_OFFSET            = 0x8,
  59         IMX8QM_CSR_MISC_OFFSET                  = 0xe0000,
  60
  61         IMX8QM_LPCG_PHYX2_PCLK0_MASK            = (0x3 << 16),
  62         IMX8QM_LPCG_PHYX2_PCLK1_MASK            = (0x3 << 20),
  63         IMX8QM_PHY_APB_RSTN_0                   = BIT(0),
  64         IMX8QM_PHY_MODE_SATA                    = BIT(19),
  65         IMX8QM_PHY_MODE_MASK                    = (0xf << 17),
  66         IMX8QM_PHY_PIPE_RSTN_0                  = BIT(24),
  67         IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0         = BIT(25),
  68         IMX8QM_PHY_PIPE_RSTN_1                  = BIT(26),
  69         IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1         = BIT(27),
  70         IMX8QM_STTS0_LANE0_TX_PLL_LOCK          = BIT(4),
  71         IMX8QM_MISC_IOB_RXENA                   = BIT(0),
  72         IMX8QM_MISC_IOB_TXENA                   = BIT(1),
  73         IMX8QM_MISC_PHYX1_EPCS_SEL              = BIT(12),
  74         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1      = BIT(24),
  75         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0      = BIT(25),
  76         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1       = BIT(28),
  77         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0       = BIT(29),
  78         IMX8QM_SATA_CTRL_RESET_N                = BIT(12),
  79         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N        = BIT(7),
  80         IMX8QM_CTRL_BUTTON_RST_N                = BIT(21),
  81         IMX8QM_CTRL_POWER_UP_RST_N              = BIT(23),
  82         IMX8QM_CTRL_LTSSM_ENABLE                = BIT(4),
  83 };
  84
  85 enum ahci_imx_type {
  86         AHCI_IMX53,
  87         AHCI_IMX6Q,
  88         AHCI_IMX6QP,
  89         AHCI_IMX8QM,
  90 };
  91
  92 struct imx_ahci_priv {
  93         struct platform_device *ahci_pdev;
  94         enum ahci_imx_type type;
  95         struct clk *sata_clk;
  96         struct clk *sata_ref_clk;
  97         struct clk *ahb_clk;
  98         struct clk *epcs_tx_clk;
  99         struct clk *epcs_rx_clk;
 100         struct clk *phy_apbclk;
 101         struct clk *phy_pclk0;
 102         struct clk *phy_pclk1;
 103         void __iomem *phy_base;
 104         struct gpio_desc *clkreq_gpiod;
 105         struct regmap *gpr;
 106         bool no_device;
 107         bool first_time;
 108         u32 phy_params;
 109         u32 imped_ratio;
 110 };
 111
 112 static int ahci_imx_hotplug;
 113 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
 114 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
 115
 116 static void ahci_imx_host_stop(struct ata_host *host);
 117
 118 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
 119 {
 120         int timeout = 10;
 121         u32 crval;
 122         u32 srval;
 123
 124         /* Assert or deassert the bit */
 125         crval = readl(mmio + IMX_P0PHYCR);
 126         if (assert)
 127                 crval |= bit;
 128         else
 129                 crval &= ~bit;
 130         writel(crval, mmio + IMX_P0PHYCR);
 131
 132         /* Wait for the cr_ack signal */
 133         do {
 134                 srval = readl(mmio + IMX_P0PHYSR);
 135                 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
 136                         break;
 137                 usleep_range(100, 200);
 138         } while (--timeout);
 139
 140         return timeout ? 0 : -ETIMEDOUT;
 141 }
 142
 143 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
 144 {
 145         u32 crval = addr;
 146         int ret;
 147
 148         /* Supply the address on cr_data_in */
 149         writel(crval, mmio + IMX_P0PHYCR);
 150
 151         /* Assert the cr_cap_addr signal */
 152         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
 153         if (ret)
 154                 return ret;
 155
 156         /* Deassert cr_cap_addr */
 157         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
 158         if (ret)
 159                 return ret;
 160
 161         return 0;
 162 }
 163
 164 static int imx_phy_reg_write(u16 val, void __iomem *mmio)
 165 {
 166         u32 crval = val;
 167         int ret;
 168
 169         /* Supply the data on cr_data_in */
 170         writel(crval, mmio + IMX_P0PHYCR);
 171
 172         /* Assert the cr_cap_data signal */
 173         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
 174         if (ret)
 175                 return ret;
 176
 177         /* Deassert cr_cap_data */
 178         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
 179         if (ret)
 180                 return ret;
 181
 182         if (val & IMX_CLOCK_RESET_RESET) {
 183                 /*
 184                  * In case we're resetting the phy, it's unable to acknowledge,
 185                  * so we return immediately here.
 186                  */
 187                 crval |= IMX_P0PHYCR_CR_WRITE;
 188                 writel(crval, mmio + IMX_P0PHYCR);
 189                 goto out;
 190         }
 191
 192         /* Assert the cr_write signal */
 193         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
 194         if (ret)
 195                 return ret;
 196
 197         /* Deassert cr_write */
 198         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
 199         if (ret)
 200                 return ret;
 201
 202 out:
 203         return 0;
 204 }
 205
 206 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
 207 {
 208         int ret;
 209
 210         /* Assert the cr_read signal */
 211         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
 212         if (ret)
 213                 return ret;
 214
 215         /* Capture the data from cr_data_out[] */
 216         *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
 217
 218         /* Deassert cr_read */
 219         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
 220         if (ret)
 221                 return ret;
 222
 223         return 0;
 224 }
 225
 226 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
 227 {
 228         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 229         void __iomem *mmio = hpriv->mmio;
 230         int timeout = 10;
 231         u16 val;
 232         int ret;
 233
 234         if (imxpriv->type == AHCI_IMX6QP) {
 235                 /* 6qp adds the sata reset mechanism, use it for 6qp sata */
 236                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 237                                    IMX6Q_GPR5_SATA_SW_PD, 0);
 238
 239                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 240                                    IMX6Q_GPR5_SATA_SW_RST, 0);
 241                 udelay(50);
 242                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 243                                    IMX6Q_GPR5_SATA_SW_RST,
 244                                    IMX6Q_GPR5_SATA_SW_RST);
 245                 return 0;
 246         }
 247
 248         /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
 249         ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
 250         if (ret)
 251                 return ret;
 252         ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
 253         if (ret)
 254                 return ret;
 255
 256         /* Wait for PHY RX_PLL to be stable */
 257         do {
 258                 usleep_range(100, 200);
 259                 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
 260                 if (ret)
 261                         return ret;
 262                 ret = imx_phy_reg_read(&val, mmio);
 263                 if (ret)
 264                         return ret;
 265                 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
 266                         break;
 267         } while (--timeout);
 268
 269         return timeout ? 0 : -ETIMEDOUT;
 270 }
 271
 272 enum {
 273         /* SATA PHY Register */
 274         SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
 275         SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
 276         SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
 277         SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
 278         SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
 279 };
 280
 281 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
 282 {
 283         u16 adc_out_reg, read_sum;
 284         u32 index, read_attempt;
 285         const u32 attempt_limit = 200;
 286
 287         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
 288         imx_phy_reg_write(rtune_ctl_reg, mmio);
 289
 290         /* two dummy read */
 291         index = 0;
 292         read_attempt = 0;
 293         adc_out_reg = 0;
 294         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
 295         while (index < 2) {
 296                 imx_phy_reg_read(&adc_out_reg, mmio);
 297                 /* check if valid */
 298                 if (adc_out_reg & 0x400)
 299                         index++;
 300
 301                 read_attempt++;
 302                 if (read_attempt > attempt_limit) {
 303                         dev_err(dev, "Read REG more than %d times!\n",
 304                                 attempt_limit);
 305                         break;
 306                 }
 307         }
 308
 309         index = 0;
 310         read_attempt = 0;
 311         read_sum = 0;
 312         while (index < 80) {
 313                 imx_phy_reg_read(&adc_out_reg, mmio);
 314                 if (adc_out_reg & 0x400) {
 315                         read_sum = read_sum + (adc_out_reg & 0x3FF);
 316                         index++;
 317                 }
 318                 read_attempt++;
 319                 if (read_attempt > attempt_limit) {
 320                         dev_err(dev, "Read REG more than %d times!\n",
 321                                 attempt_limit);
 322                         break;
 323                 }
 324         }
 325
 326         /* Use the U32 to make 1000 precision */
 327         return (read_sum * 1000) / 80;
 328 }
 329
 330 /* SATA AHCI temperature monitor */
 331 static int __sata_ahci_read_temperature(void *dev, int *temp)
 332 {
 333         u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
 334         u32 str1, str2, str3, str4;
 335         int m1, m2, a;
 336         struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
 337         void __iomem *mmio = hpriv->mmio;
 338
 339         /* check rd-wr to reg */
 340         read_sum = 0;
 341         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
 342         imx_phy_reg_write(read_sum, mmio);
 343         imx_phy_reg_read(&read_sum, mmio);
 344         if ((read_sum & 0xffff) != 0)
 345                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
 346
 347         imx_phy_reg_write(0x5A5A, mmio);
 348         imx_phy_reg_read(&read_sum, mmio);
 349         if ((read_sum & 0xffff) != 0x5A5A)
 350                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
 351
 352         imx_phy_reg_write(0x1234, mmio);
 353         imx_phy_reg_read(&read_sum, mmio);
 354         if ((read_sum & 0xffff) != 0x1234)
 355                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
 356
 357         /* start temperature test */
 358         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
 359         imx_phy_reg_read(&mpll_test_reg, mmio);
 360         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
 361         imx_phy_reg_read(&rtune_ctl_reg, mmio);
 362         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
 363         imx_phy_reg_read(&dac_ctl_reg, mmio);
 364
 365         /* mpll_tst.meas_iv   ([12:2]) */
 366         str1 = (mpll_test_reg >> 2) & 0x7FF;
 367         /* rtune_ctl.mode     ([1:0]) */
 368         str2 = (rtune_ctl_reg) & 0x3;
 369         /* dac_ctl.dac_mode   ([14:12]) */
 370         str3 = (dac_ctl_reg >> 12)  & 0x7;
 371         /* rtune_ctl.sel_atbp ([4]) */
 372         str4 = (rtune_ctl_reg >> 4);
 373
 374         /* Calculate the m1 */
 375         /* mpll_tst.meas_iv */
 376         mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
 377         /* rtune_ctl.mode */
 378         rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
 379         /* dac_ctl.dac_mode */
 380         dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
 381         /* rtune_ctl.sel_atbp */
 382         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
 383         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
 384         imx_phy_reg_write(mpll_test_reg, mmio);
 385         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
 386         imx_phy_reg_write(dac_ctl_reg, mmio);
 387         m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
 388
 389         /* Calculate the m2 */
 390         /* rtune_ctl.sel_atbp */
 391         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
 392         m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
 393
 394         /* restore the status  */
 395         /* mpll_tst.meas_iv */
 396         mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
 397         /* rtune_ctl.mode */
 398         rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
 399         /* dac_ctl.dac_mode */
 400         dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
 401         /* rtune_ctl.sel_atbp */
 402         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
 403
 404         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
 405         imx_phy_reg_write(mpll_test_reg, mmio);
 406         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
 407         imx_phy_reg_write(dac_ctl_reg, mmio);
 408         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
 409         imx_phy_reg_write(rtune_ctl_reg, mmio);
 410
 411         /* Compute temperature */
 412         if (!(m2 / 1000))
 413                 m2 = 1000;
 414         a = (m2 - m1) / (m2/1000);
 415         *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
 416
 417         return 0;
 418 }
 419
 420 static int sata_ahci_read_temperature(struct thermal_zone_device *tz, int *temp)
 421 {
 422         return __sata_ahci_read_temperature(thermal_zone_device_priv(tz), temp);
 423 }
 424
 425 static ssize_t sata_ahci_show_temp(struct device *dev,
 426                                    struct device_attribute *da,
 427                                    char *buf)
 428 {
 429         unsigned int temp = 0;
 430         int err;
 431
 432         err = __sata_ahci_read_temperature(dev, &temp);
 433         if (err < 0)
 434                 return err;
 435
 436         return sprintf(buf, "%u\n", temp);
 437 }
 438
 439 static const struct thermal_zone_device_ops fsl_sata_ahci_of_thermal_ops = {
 440         .get_temp = sata_ahci_read_temperature,
 441 };
 442
 443 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
 444
 445 static struct attribute *fsl_sata_ahci_attrs[] = {
 446         &sensor_dev_attr_temp1_input.dev_attr.attr,
 447         NULL
 448 };
 449 ATTRIBUTE_GROUPS(fsl_sata_ahci);
 450
 451 static int imx8_sata_enable(struct ahci_host_priv *hpriv)
 452 {
 453         u32 val, reg;
 454         int i, ret;
 455         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 456         struct device *dev = &imxpriv->ahci_pdev->dev;
 457
 458         /* configure the hsio for sata */
 459         ret = clk_prepare_enable(imxpriv->phy_pclk0);
 460         if (ret < 0) {
 461                 dev_err(dev, "can't enable phy_pclk0.\n");
 462                 return ret;
 463         }
 464         ret = clk_prepare_enable(imxpriv->phy_pclk1);
 465         if (ret < 0) {
 466                 dev_err(dev, "can't enable phy_pclk1.\n");
 467                 goto disable_phy_pclk0;
 468         }
 469         ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
 470         if (ret < 0) {
 471                 dev_err(dev, "can't enable epcs_tx_clk.\n");
 472                 goto disable_phy_pclk1;
 473         }
 474         ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
 475         if (ret < 0) {
 476                 dev_err(dev, "can't enable epcs_rx_clk.\n");
 477                 goto disable_epcs_tx_clk;
 478         }
 479         ret = clk_prepare_enable(imxpriv->phy_apbclk);
 480         if (ret < 0) {
 481                 dev_err(dev, "can't enable phy_apbclk.\n");
 482                 goto disable_epcs_rx_clk;
 483         }
 484         /* Configure PHYx2 PIPE_RSTN */
 485         regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
 486                         IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
 487         if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
 488                 /* The link of the PCIEA of HSIO is down */
 489                 regmap_update_bits(imxpriv->gpr,
 490                                 IMX8QM_CSR_PHYX2_OFFSET,
 491                                 IMX8QM_PHY_PIPE_RSTN_0 |
 492                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
 493                                 IMX8QM_PHY_PIPE_RSTN_0 |
 494                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
 495         }
 496         regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
 497                         IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
 498         if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
 499                 /* The link of the PCIEB of HSIO is down */
 500                 regmap_update_bits(imxpriv->gpr,
 501                                 IMX8QM_CSR_PHYX2_OFFSET,
 502                                 IMX8QM_PHY_PIPE_RSTN_1 |
 503                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
 504                                 IMX8QM_PHY_PIPE_RSTN_1 |
 505                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
 506         }
 507         if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
 508                 /* The links of both PCIA and PCIEB of HSIO are down */
 509                 regmap_update_bits(imxpriv->gpr,
 510                                 IMX8QM_LPCG_PHYX2_OFFSET,
 511                                 IMX8QM_LPCG_PHYX2_PCLK0_MASK |
 512                                 IMX8QM_LPCG_PHYX2_PCLK1_MASK,
 513                                 0);
 514         }
 515
 516         /* set PWR_RST and BT_RST of csr_pciea */
 517         val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
 518         regmap_update_bits(imxpriv->gpr,
 519                         val,
 520                         IMX8QM_CTRL_BUTTON_RST_N,
 521                         IMX8QM_CTRL_BUTTON_RST_N);
 522         regmap_update_bits(imxpriv->gpr,
 523                         val,
 524                         IMX8QM_CTRL_POWER_UP_RST_N,
 525                         IMX8QM_CTRL_POWER_UP_RST_N);
 526
 527         /* PHYX1_MODE to SATA */
 528         regmap_update_bits(imxpriv->gpr,
 529                         IMX8QM_CSR_PHYX1_OFFSET,
 530                         IMX8QM_PHY_MODE_MASK,
 531                         IMX8QM_PHY_MODE_SATA);
 532
 533         /*
 534          * BIT0 RXENA 1, BIT1 TXENA 0
 535          * BIT12 PHY_X1_EPCS_SEL 1.
 536          */
 537         regmap_update_bits(imxpriv->gpr,
 538                         IMX8QM_CSR_MISC_OFFSET,
 539                         IMX8QM_MISC_IOB_RXENA,
 540                         IMX8QM_MISC_IOB_RXENA);
 541         regmap_update_bits(imxpriv->gpr,
 542                         IMX8QM_CSR_MISC_OFFSET,
 543                         IMX8QM_MISC_IOB_TXENA,
 544                         0);
 545         regmap_update_bits(imxpriv->gpr,
 546                         IMX8QM_CSR_MISC_OFFSET,
 547                         IMX8QM_MISC_PHYX1_EPCS_SEL,
 548                         IMX8QM_MISC_PHYX1_EPCS_SEL);
 549         /*
 550          * It is possible, for PCIe and SATA are sharing
 551          * the same clock source, HPLL or external oscillator.
 552          * When PCIe is in low power modes (L1.X or L2 etc),
 553          * the clock source can be turned off. In this case,
 554          * if this clock source is required to be toggling by
 555          * SATA, then SATA functions will be abnormal.
 556          * Set the override here to avoid it.
 557          */
 558         regmap_update_bits(imxpriv->gpr,
 559                         IMX8QM_CSR_MISC_OFFSET,
 560                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
 561                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
 562                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
 563                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
 564                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
 565                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
 566                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
 567                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
 568
 569         /* clear PHY RST, then set it */
 570         regmap_update_bits(imxpriv->gpr,
 571                         IMX8QM_CSR_SATA_OFFSET,
 572                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
 573                         0);
 574
 575         regmap_update_bits(imxpriv->gpr,
 576                         IMX8QM_CSR_SATA_OFFSET,
 577                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
 578                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
 579
 580         /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
 581         regmap_update_bits(imxpriv->gpr,
 582                         IMX8QM_CSR_SATA_OFFSET,
 583                         IMX8QM_SATA_CTRL_RESET_N,
 584                         IMX8QM_SATA_CTRL_RESET_N);
 585         udelay(1);
 586         regmap_update_bits(imxpriv->gpr,
 587                         IMX8QM_CSR_SATA_OFFSET,
 588                         IMX8QM_SATA_CTRL_RESET_N,
 589                         0);
 590         regmap_update_bits(imxpriv->gpr,
 591                         IMX8QM_CSR_SATA_OFFSET,
 592                         IMX8QM_SATA_CTRL_RESET_N,
 593                         IMX8QM_SATA_CTRL_RESET_N);
 594
 595         /* APB reset */
 596         regmap_update_bits(imxpriv->gpr,
 597                         IMX8QM_CSR_PHYX1_OFFSET,
 598                         IMX8QM_PHY_APB_RSTN_0,
 599                         IMX8QM_PHY_APB_RSTN_0);
 600
 601         for (i = 0; i < 100; i++) {
 602                 reg = IMX8QM_CSR_PHYX1_OFFSET +
 603                         IMX8QM_CSR_PHYX_STTS0_OFFSET;
 604                 regmap_read(imxpriv->gpr, reg, &val);
 605                 val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
 606                 if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
 607                         break;
 608                 udelay(1);
 609         }
 610
 611         if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
 612                 dev_err(dev, "TX PLL of the PHY is not locked\n");
 613                 ret = -ENODEV;
 614         } else {
 615                 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
 616                                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
 617                 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
 618                                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
 619                 reg = readb(imxpriv->phy_base +
 620                                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
 621                 if (unlikely(reg != imxpriv->imped_ratio))
 622                         dev_info(dev, "Can't set PHY RX impedance ratio.\n");
 623                 reg = readb(imxpriv->phy_base +
 624                                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
 625                 if (unlikely(reg != imxpriv->imped_ratio))
 626                         dev_info(dev, "Can't set PHY TX impedance ratio.\n");
 627                 usleep_range(50, 100);
 628
 629                 /*
 630                  * To reduce the power consumption, gate off
 631                  * the PHY clks
 632                  */
 633                 clk_disable_unprepare(imxpriv->phy_apbclk);
 634                 clk_disable_unprepare(imxpriv->phy_pclk1);
 635                 clk_disable_unprepare(imxpriv->phy_pclk0);
 636                 return ret;
 637         }
 638
 639         clk_disable_unprepare(imxpriv->phy_apbclk);
 640 disable_epcs_rx_clk:
 641         clk_disable_unprepare(imxpriv->epcs_rx_clk);
 642 disable_epcs_tx_clk:
 643         clk_disable_unprepare(imxpriv->epcs_tx_clk);
 644 disable_phy_pclk1:
 645         clk_disable_unprepare(imxpriv->phy_pclk1);
 646 disable_phy_pclk0:
 647         clk_disable_unprepare(imxpriv->phy_pclk0);
 648
 649         return ret;
 650 }
 651
 652 static int imx_sata_enable(struct ahci_host_priv *hpriv)
 653 {
 654         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 655         struct device *dev = &imxpriv->ahci_pdev->dev;
 656         int ret;
 657
 658         if (imxpriv->no_device)
 659                 return 0;
 660
 661         ret = ahci_platform_enable_regulators(hpriv);
 662         if (ret)
 663                 return ret;
 664
 665         ret = clk_prepare_enable(imxpriv->sata_ref_clk);
 666         if (ret < 0)
 667                 goto disable_regulator;
 668
 669         if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
 670                 /*
 671                  * set PHY Paremeters, two steps to configure the GPR13,
 672                  * one write for rest of parameters, mask of first write
 673                  * is 0x07ffffff, and the other one write for setting
 674                  * the mpll_clk_en.
 675                  */
 676                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 677                                    IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
 678                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
 679                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
 680                                    IMX6Q_GPR13_SATA_SPD_MODE_MASK |
 681                                    IMX6Q_GPR13_SATA_MPLL_SS_EN |
 682                                    IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
 683                                    IMX6Q_GPR13_SATA_TX_BOOST_MASK |
 684                                    IMX6Q_GPR13_SATA_TX_LVL_MASK |
 685                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN |
 686                                    IMX6Q_GPR13_SATA_TX_EDGE_RATE,
 687                                    imxpriv->phy_params);
 688                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 689                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 690                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 691
 692                 usleep_range(100, 200);
 693
 694                 ret = imx_sata_phy_reset(hpriv);
 695                 if (ret) {
 696                         dev_err(dev, "failed to reset phy: %d\n", ret);
 697                         goto disable_clk;
 698                 }
 699         } else if (imxpriv->type == AHCI_IMX8QM) {
 700                 ret = imx8_sata_enable(hpriv);
 701         }
 702
 703         usleep_range(1000, 2000);
 704
 705         return 0;
 706
 707 disable_clk:
 708         clk_disable_unprepare(imxpriv->sata_ref_clk);
 709 disable_regulator:
 710         ahci_platform_disable_regulators(hpriv);
 711
 712         return ret;
 713 }
 714
 715 static void imx_sata_disable(struct ahci_host_priv *hpriv)
 716 {
 717         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 718
 719         if (imxpriv->no_device)
 720                 return;
 721
 722         switch (imxpriv->type) {
 723         case AHCI_IMX6QP:
 724                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 725                                    IMX6Q_GPR5_SATA_SW_PD,
 726                                    IMX6Q_GPR5_SATA_SW_PD);
 727                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 728                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 729                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 730                 break;
 731
 732         case AHCI_IMX6Q:
 733                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 734                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 735                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 736                 break;
 737
 738         case AHCI_IMX8QM:
 739                 clk_disable_unprepare(imxpriv->epcs_rx_clk);
 740                 clk_disable_unprepare(imxpriv->epcs_tx_clk);
 741                 break;
 742
 743         default:
 744                 break;
 745         }
 746
 747         clk_disable_unprepare(imxpriv->sata_ref_clk);
 748
 749         ahci_platform_disable_regulators(hpriv);
 750 }
 751
 752 static void ahci_imx_error_handler(struct ata_port *ap)
 753 {
 754         u32 reg_val;
 755         struct ata_device *dev;
 756         struct ata_host *host = dev_get_drvdata(ap->dev);
 757         struct ahci_host_priv *hpriv = host->private_data;
 758         void __iomem *mmio = hpriv->mmio;
 759         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 760
 761         ahci_error_handler(ap);
 762
 763         if (!(imxpriv->first_time) || ahci_imx_hotplug)
 764                 return;
 765
 766         imxpriv->first_time = false;
 767
 768         ata_for_each_dev(dev, &ap->link, ENABLED)
 769                 return;
 770         /*
 771          * Disable link to save power.  An imx ahci port can't be recovered
 772          * without full reset once the pddq mode is enabled making it
 773          * impossible to use as part of libata LPM.
 774          */
 775         reg_val = readl(mmio + IMX_P0PHYCR);
 776         writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
 777         imx_sata_disable(hpriv);
 778         imxpriv->no_device = true;
 779
 780         dev_info(ap->dev, "no device found, disabling link.\n");
 781         dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
 782 }
 783
 784 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
 785                        unsigned long deadline)
 786 {
 787         struct ata_port *ap = link->ap;
 788         struct ata_host *host = dev_get_drvdata(ap->dev);
 789         struct ahci_host_priv *hpriv = host->private_data;
 790         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 791         int ret;
 792
 793         if (imxpriv->type == AHCI_IMX53)
 794                 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
 795         else
 796                 ret = ahci_ops.softreset(link, class, deadline);
 797
 798         return ret;
 799 }
 800
 801 static struct ata_port_operations ahci_imx_ops = {
 802         .inherits       = &ahci_ops,
 803         .host_stop      = ahci_imx_host_stop,
 804         .error_handler  = ahci_imx_error_handler,
 805         .softreset      = ahci_imx_softreset,
 806 };
 807
 808 static const struct ata_port_info ahci_imx_port_info = {
 809         .flags          = AHCI_FLAG_COMMON,
 810         .pio_mask       = ATA_PIO4,
 811         .udma_mask      = ATA_UDMA6,
 812         .port_ops       = &ahci_imx_ops,
 813 };
 814
 815 static const struct of_device_id imx_ahci_of_match[] = {
 816         { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
 817         { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
 818         { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
 819         { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
 820         { /* sentinel */ }
 821 };
 822 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
 823
 824 struct reg_value {
 825         u32 of_value;
 826         u32 reg_value;
 827 };
 828
 829 struct reg_property {
 830         const char *name;
 831         const struct reg_value *values;
 832         size_t num_values;
 833         u32 def_value;
 834         u32 set_value;
 835 };
 836
 837 static const struct reg_value gpr13_tx_level[] = {
 838         {  937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
 839         {  947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
 840         {  957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
 841         {  966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
 842         {  976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
 843         {  986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
 844         {  996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
 845         { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
 846         { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
 847         { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
 848         { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
 849         { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
 850         { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
 851         { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
 852         { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
 853         { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
 854         { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
 855         { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
 856         { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
 857         { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
 858         { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
 859         { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
 860         { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
 861         { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
 862         { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
 863         { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
 864         { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
 865         { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
 866         { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
 867         { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
 868         { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
 869         { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
 870 };
 871
 872 static const struct reg_value gpr13_tx_boost[] = {
 873         {    0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
 874         {  370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
 875         {  740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
 876         { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
 877         { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
 878         { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
 879         { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
 880         { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
 881         { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
 882         { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
 883         { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
 884         { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
 885         { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
 886         { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
 887         { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
 888         { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
 889 };
 890
 891 static const struct reg_value gpr13_tx_atten[] = {
 892         {  8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
 893         {  9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
 894         { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
 895         { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
 896         { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
 897         { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
 898 };
 899
 900 static const struct reg_value gpr13_rx_eq[] = {
 901         {  500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
 902         { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
 903         { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
 904         { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
 905         { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
 906         { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
 907         { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
 908         { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
 909 };
 910
 911 static const struct reg_property gpr13_props[] = {
 912         {
 913                 .name = "fsl,transmit-level-mV",
 914                 .values = gpr13_tx_level,
 915                 .num_values = ARRAY_SIZE(gpr13_tx_level),
 916                 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
 917         }, {
 918                 .name = "fsl,transmit-boost-mdB",
 919                 .values = gpr13_tx_boost,
 920                 .num_values = ARRAY_SIZE(gpr13_tx_boost),
 921                 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
 922         }, {
 923                 .name = "fsl,transmit-atten-16ths",
 924                 .values = gpr13_tx_atten,
 925                 .num_values = ARRAY_SIZE(gpr13_tx_atten),
 926                 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
 927         }, {
 928                 .name = "fsl,receive-eq-mdB",
 929                 .values = gpr13_rx_eq,
 930                 .num_values = ARRAY_SIZE(gpr13_rx_eq),
 931                 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
 932         }, {
 933                 .name = "fsl,no-spread-spectrum",
 934                 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
 935                 .set_value = 0,
 936         },
 937 };
 938
 939 static u32 imx_ahci_parse_props(struct device *dev,
 940                                 const struct reg_property *prop, size_t num)
 941 {
 942         struct device_node *np = dev->of_node;
 943         u32 reg_value = 0;
 944         int i, j;
 945
 946         for (i = 0; i < num; i++, prop++) {
 947                 u32 of_val;
 948
 949                 if (prop->num_values == 0) {
 950                         if (of_property_read_bool(np, prop->name))
 951                                 reg_value |= prop->set_value;
 952                         else
 953                                 reg_value |= prop->def_value;
 954                         continue;
 955                 }
 956
 957                 if (of_property_read_u32(np, prop->name, &of_val)) {
 958                         dev_info(dev, "%s not specified, using %08x\n",
 959                                 prop->name, prop->def_value);
 960                         reg_value |= prop->def_value;
 961                         continue;
 962                 }
 963
 964                 for (j = 0; j < prop->num_values; j++) {
 965                         if (prop->values[j].of_value == of_val) {
 966                                 dev_info(dev, "%s value %u, using %08x\n",
 967                                         prop->name, of_val, prop->values[j].reg_value);
 968                                 reg_value |= prop->values[j].reg_value;
 969                                 break;
 970                         }
 971                 }
 972
 973                 if (j == prop->num_values) {
 974                         dev_err(dev, "DT property %s is not a valid value\n",
 975                                 prop->name);
 976                         reg_value |= prop->def_value;
 977                 }
 978         }
 979
 980         return reg_value;
 981 }
 982
 983 static const struct scsi_host_template ahci_platform_sht = {
 984         AHCI_SHT(DRV_NAME),
 985 };
 986
 987 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
 988 {
 989         struct resource *phy_res;
 990         struct platform_device *pdev = imxpriv->ahci_pdev;
 991         struct device_node *np = dev->of_node;
 992
 993         if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
 994                 imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
 995         phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
 996         if (phy_res) {
 997                 imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
 998                                         resource_size(phy_res));
 999                 if (!imxpriv->phy_base) {
1000                         dev_err(dev, "error with ioremap\n");
1001                         return -ENOMEM;
1002                 }
1003         } else {
1004                 dev_err(dev, "missing *phy* reg region.\n");
1005                 return -ENOMEM;
1006         }
1007         imxpriv->gpr =
1008                  syscon_regmap_lookup_by_phandle(np, "hsio");
1009         if (IS_ERR(imxpriv->gpr)) {
1010                 dev_err(dev, "unable to find gpr registers\n");
1011                 return PTR_ERR(imxpriv->gpr);
1012         }
1013
1014         imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
1015         if (IS_ERR(imxpriv->epcs_tx_clk)) {
1016                 dev_err(dev, "can't get epcs_tx_clk clock.\n");
1017                 return PTR_ERR(imxpriv->epcs_tx_clk);
1018         }
1019         imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
1020         if (IS_ERR(imxpriv->epcs_rx_clk)) {
1021                 dev_err(dev, "can't get epcs_rx_clk clock.\n");
1022                 return PTR_ERR(imxpriv->epcs_rx_clk);
1023         }
1024         imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
1025         if (IS_ERR(imxpriv->phy_pclk0)) {
1026                 dev_err(dev, "can't get phy_pclk0 clock.\n");
1027                 return PTR_ERR(imxpriv->phy_pclk0);
1028         }
1029         imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
1030         if (IS_ERR(imxpriv->phy_pclk1)) {
1031                 dev_err(dev, "can't get phy_pclk1 clock.\n");
1032                 return PTR_ERR(imxpriv->phy_pclk1);
1033         }
1034         imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
1035         if (IS_ERR(imxpriv->phy_apbclk)) {
1036                 dev_err(dev, "can't get phy_apbclk clock.\n");
1037                 return PTR_ERR(imxpriv->phy_apbclk);
1038         }
1039
1040         /* Fetch GPIO, then enable the external OSC */
1041         imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
1042                                 GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1043         if (IS_ERR(imxpriv->clkreq_gpiod))
1044                 return PTR_ERR(imxpriv->clkreq_gpiod);
1045         if (imxpriv->clkreq_gpiod)
1046                 gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
1047
1048         return 0;
1049 }
1050
1051 static int imx_ahci_probe(struct platform_device *pdev)
1052 {
1053         struct device *dev = &pdev->dev;
1054         struct ahci_host_priv *hpriv;
1055         struct imx_ahci_priv *imxpriv;
1056         unsigned int reg_val;
1057         int ret;
1058
1059         imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
1060         if (!imxpriv)
1061                 return -ENOMEM;
1062
1063         imxpriv->ahci_pdev = pdev;
1064         imxpriv->no_device = false;
1065         imxpriv->first_time = true;
1066         imxpriv->type = (enum ahci_imx_type)device_get_match_data(dev);
1067
1068         imxpriv->sata_clk = devm_clk_get(dev, "sata");
1069         if (IS_ERR(imxpriv->sata_clk)) {
1070                 dev_err(dev, "can't get sata clock.\n");
1071                 return PTR_ERR(imxpriv->sata_clk);
1072         }
1073
1074         imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
1075         if (IS_ERR(imxpriv->sata_ref_clk)) {
1076                 dev_err(dev, "can't get sata_ref clock.\n");
1077                 return PTR_ERR(imxpriv->sata_ref_clk);
1078         }
1079
1080         imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
1081         if (IS_ERR(imxpriv->ahb_clk)) {
1082                 dev_err(dev, "can't get ahb clock.\n");
1083                 return PTR_ERR(imxpriv->ahb_clk);
1084         }
1085
1086         if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
1087                 u32 reg_value;
1088
1089                 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
1090                                                         "fsl,imx6q-iomuxc-gpr");
1091                 if (IS_ERR(imxpriv->gpr)) {
1092                         dev_err(dev,
1093                                 "failed to find fsl,imx6q-iomux-gpr regmap\n");
1094                         return PTR_ERR(imxpriv->gpr);
1095                 }
1096
1097                 reg_value = imx_ahci_parse_props(dev, gpr13_props,
1098                                                  ARRAY_SIZE(gpr13_props));
1099
1100                 imxpriv->phy_params =
1101                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
1102                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
1103                                    IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
1104                                    reg_value;
1105         } else if (imxpriv->type == AHCI_IMX8QM) {
1106                 ret =  imx8_sata_probe(dev, imxpriv);
1107                 if (ret)
1108                         return ret;
1109         }
1110
1111         hpriv = ahci_platform_get_resources(pdev, 0);
1112         if (IS_ERR(hpriv))
1113                 return PTR_ERR(hpriv);
1114
1115         hpriv->plat_data = imxpriv;
1116
1117         ret = clk_prepare_enable(imxpriv->sata_clk);
1118         if (ret)
1119                 return ret;
1120
1121         if (imxpriv->type == AHCI_IMX53 &&
1122             IS_ENABLED(CONFIG_HWMON)) {
1123                 /* Add the temperature monitor */
1124                 struct device *hwmon_dev;
1125
1126                 hwmon_dev =
1127                         devm_hwmon_device_register_with_groups(dev,
1128                                                         "sata_ahci",
1129                                                         hpriv,
1130                                                         fsl_sata_ahci_groups);
1131                 if (IS_ERR(hwmon_dev)) {
1132                         ret = PTR_ERR(hwmon_dev);
1133                         goto disable_clk;
1134                 }
1135                 devm_thermal_of_zone_register(hwmon_dev, 0, hwmon_dev,
1136                                               &fsl_sata_ahci_of_thermal_ops);
1137                 dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
1138         }
1139
1140         ret = imx_sata_enable(hpriv);
1141         if (ret)
1142                 goto disable_clk;
1143
1144         /*
1145          * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
1146          * and IP vendor specific register IMX_TIMER1MS.
1147          * Configure CAP_SSS (support stagered spin up).
1148          * Implement the port0.
1149          * Get the ahb clock rate, and configure the TIMER1MS register.
1150          */
1151         reg_val = readl(hpriv->mmio + HOST_CAP);
1152         if (!(reg_val & HOST_CAP_SSS)) {
1153                 reg_val |= HOST_CAP_SSS;
1154                 writel(reg_val, hpriv->mmio + HOST_CAP);
1155         }
1156         reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
1157         if (!(reg_val & 0x1)) {
1158                 reg_val |= 0x1;
1159                 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
1160         }
1161
1162         reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
1163         writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
1164
1165         ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
1166                                       &ahci_platform_sht);
1167         if (ret)
1168                 goto disable_sata;
1169
1170         return 0;
1171
1172 disable_sata:
1173         imx_sata_disable(hpriv);
1174 disable_clk:
1175         clk_disable_unprepare(imxpriv->sata_clk);
1176         return ret;
1177 }
1178
1179 static void ahci_imx_host_stop(struct ata_host *host)
1180 {
1181         struct ahci_host_priv *hpriv = host->private_data;
1182         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
1183
1184         imx_sata_disable(hpriv);
1185         clk_disable_unprepare(imxpriv->sata_clk);
1186 }
1187
1188 #ifdef CONFIG_PM_SLEEP
1189 static int imx_ahci_suspend(struct device *dev)
1190 {
1191         struct ata_host *host = dev_get_drvdata(dev);
1192         struct ahci_host_priv *hpriv = host->private_data;
1193         int ret;
1194
1195         ret = ahci_platform_suspend_host(dev);
1196         if (ret)
1197                 return ret;
1198
1199         imx_sata_disable(hpriv);
1200
1201         return 0;
1202 }
1203
1204 static int imx_ahci_resume(struct device *dev)
1205 {
1206         struct ata_host *host = dev_get_drvdata(dev);
1207         struct ahci_host_priv *hpriv = host->private_data;
1208         int ret;
1209
1210         ret = imx_sata_enable(hpriv);
1211         if (ret)
1212                 return ret;
1213
1214         return ahci_platform_resume_host(dev);
1215 }
1216 #endif
1217
1218 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
1219
1220 static struct platform_driver imx_ahci_driver = {
1221         .probe = imx_ahci_probe,
1222         .remove_new = ata_platform_remove_one,
1223         .driver = {
1224                 .name = DRV_NAME,
1225                 .of_match_table = imx_ahci_of_match,
1226                 .pm = &ahci_imx_pm_ops,
1227         },
1228 };
1229 module_platform_driver(imx_ahci_driver);
1230
1231 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
1232 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
1233 MODULE_LICENSE("GPL");
1234 MODULE_ALIAS("platform:" DRV_NAME);