drivers/ata/ahci_imx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * copyright (c) 2013 Freescale Semiconductor, Inc.
   4  * Freescale IMX AHCI SATA platform driver
   5  *
   6  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regmap.h>
  13 #include <linux/ahci_platform.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/of_device.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  18 #include <linux/libata.h>
  19 #include <linux/hwmon.h>
  20 #include <linux/hwmon-sysfs.h>
  21 #include <linux/thermal.h>
  22 #include "ahci.h"
  23
  24 #define DRV_NAME "ahci-imx"
  25
  26 enum {
  27         /* Timer 1-ms Register */
  28         IMX_TIMER1MS                            = 0x00e0,
  29         /* Port0 PHY Control Register */
  30         IMX_P0PHYCR                             = 0x0178,
  31         IMX_P0PHYCR_TEST_PDDQ                   = 1 << 20,
  32         IMX_P0PHYCR_CR_READ                     = 1 << 19,
  33         IMX_P0PHYCR_CR_WRITE                    = 1 << 18,
  34         IMX_P0PHYCR_CR_CAP_DATA                 = 1 << 17,
  35         IMX_P0PHYCR_CR_CAP_ADDR                 = 1 << 16,
  36         /* Port0 PHY Status Register */
  37         IMX_P0PHYSR                             = 0x017c,
  38         IMX_P0PHYSR_CR_ACK                      = 1 << 18,
  39         IMX_P0PHYSR_CR_DATA_OUT                 = 0xffff << 0,
  40         /* Lane0 Output Status Register */
  41         IMX_LANE0_OUT_STAT                      = 0x2003,
  42         IMX_LANE0_OUT_STAT_RX_PLL_STATE         = 1 << 1,
  43         /* Clock Reset Register */
  44         IMX_CLOCK_RESET                         = 0x7f3f,
  45         IMX_CLOCK_RESET_RESET                   = 1 << 0,
  46         /* IMX8QM HSIO AHCI definitions */
  47         IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET   = 0x03,
  48         IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET   = 0x09,
  49         IMX8QM_SATA_PHY_IMPED_RATIO_85OHM       = 0x6c,
  50         IMX8QM_LPCG_PHYX2_OFFSET                = 0x00000,
  51         IMX8QM_CSR_PHYX2_OFFSET                 = 0x90000,
  52         IMX8QM_CSR_PHYX1_OFFSET                 = 0xa0000,
  53         IMX8QM_CSR_PHYX_STTS0_OFFSET            = 0x4,
  54         IMX8QM_CSR_PCIEA_OFFSET                 = 0xb0000,
  55         IMX8QM_CSR_PCIEB_OFFSET                 = 0xc0000,
  56         IMX8QM_CSR_SATA_OFFSET                  = 0xd0000,
  57         IMX8QM_CSR_PCIE_CTRL2_OFFSET            = 0x8,
  58         IMX8QM_CSR_MISC_OFFSET                  = 0xe0000,
  59
  60         IMX8QM_LPCG_PHYX2_PCLK0_MASK            = (0x3 << 16),
  61         IMX8QM_LPCG_PHYX2_PCLK1_MASK            = (0x3 << 20),
  62         IMX8QM_PHY_APB_RSTN_0                   = BIT(0),
  63         IMX8QM_PHY_MODE_SATA                    = BIT(19),
  64         IMX8QM_PHY_MODE_MASK                    = (0xf << 17),
  65         IMX8QM_PHY_PIPE_RSTN_0                  = BIT(24),
  66         IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0         = BIT(25),
  67         IMX8QM_PHY_PIPE_RSTN_1                  = BIT(26),
  68         IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1         = BIT(27),
  69         IMX8QM_STTS0_LANE0_TX_PLL_LOCK          = BIT(4),
  70         IMX8QM_MISC_IOB_RXENA                   = BIT(0),
  71         IMX8QM_MISC_IOB_TXENA                   = BIT(1),
  72         IMX8QM_MISC_PHYX1_EPCS_SEL              = BIT(12),
  73         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1      = BIT(24),
  74         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0      = BIT(25),
  75         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1       = BIT(28),
  76         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0       = BIT(29),
  77         IMX8QM_SATA_CTRL_RESET_N                = BIT(12),
  78         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N        = BIT(7),
  79         IMX8QM_CTRL_BUTTON_RST_N                = BIT(21),
  80         IMX8QM_CTRL_POWER_UP_RST_N              = BIT(23),
  81         IMX8QM_CTRL_LTSSM_ENABLE                = BIT(4),
  82 };
  83
  84 enum ahci_imx_type {
  85         AHCI_IMX53,
  86         AHCI_IMX6Q,
  87         AHCI_IMX6QP,
  88         AHCI_IMX8QM,
  89 };
  90
  91 struct imx_ahci_priv {
  92         struct platform_device *ahci_pdev;
  93         enum ahci_imx_type type;
  94         struct clk *sata_clk;
  95         struct clk *sata_ref_clk;
  96         struct clk *ahb_clk;
  97         struct clk *epcs_tx_clk;
  98         struct clk *epcs_rx_clk;
  99         struct clk *phy_apbclk;
 100         struct clk *phy_pclk0;
 101         struct clk *phy_pclk1;
 102         void __iomem *phy_base;
 103         struct gpio_desc *clkreq_gpiod;
 104         struct regmap *gpr;
 105         bool no_device;
 106         bool first_time;
 107         u32 phy_params;
 108         u32 imped_ratio;
 109 };
 110
 111 static int ahci_imx_hotplug;
 112 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
 113 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
 114
 115 static void ahci_imx_host_stop(struct ata_host *host);
 116
 117 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
 118 {
 119         int timeout = 10;
 120         u32 crval;
 121         u32 srval;
 122
 123         /* Assert or deassert the bit */
 124         crval = readl(mmio + IMX_P0PHYCR);
 125         if (assert)
 126                 crval |= bit;
 127         else
 128                 crval &= ~bit;
 129         writel(crval, mmio + IMX_P0PHYCR);
 130
 131         /* Wait for the cr_ack signal */
 132         do {
 133                 srval = readl(mmio + IMX_P0PHYSR);
 134                 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
 135                         break;
 136                 usleep_range(100, 200);
 137         } while (--timeout);
 138
 139         return timeout ? 0 : -ETIMEDOUT;
 140 }
 141
 142 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
 143 {
 144         u32 crval = addr;
 145         int ret;
 146
 147         /* Supply the address on cr_data_in */
 148         writel(crval, mmio + IMX_P0PHYCR);
 149
 150         /* Assert the cr_cap_addr signal */
 151         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
 152         if (ret)
 153                 return ret;
 154
 155         /* Deassert cr_cap_addr */
 156         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
 157         if (ret)
 158                 return ret;
 159
 160         return 0;
 161 }
 162
 163 static int imx_phy_reg_write(u16 val, void __iomem *mmio)
 164 {
 165         u32 crval = val;
 166         int ret;
 167
 168         /* Supply the data on cr_data_in */
 169         writel(crval, mmio + IMX_P0PHYCR);
 170
 171         /* Assert the cr_cap_data signal */
 172         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
 173         if (ret)
 174                 return ret;
 175
 176         /* Deassert cr_cap_data */
 177         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
 178         if (ret)
 179                 return ret;
 180
 181         if (val & IMX_CLOCK_RESET_RESET) {
 182                 /*
 183                  * In case we're resetting the phy, it's unable to acknowledge,
 184                  * so we return immediately here.
 185                  */
 186                 crval |= IMX_P0PHYCR_CR_WRITE;
 187                 writel(crval, mmio + IMX_P0PHYCR);
 188                 goto out;
 189         }
 190
 191         /* Assert the cr_write signal */
 192         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
 193         if (ret)
 194                 return ret;
 195
 196         /* Deassert cr_write */
 197         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
 198         if (ret)
 199                 return ret;
 200
 201 out:
 202         return 0;
 203 }
 204
 205 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
 206 {
 207         int ret;
 208
 209         /* Assert the cr_read signal */
 210         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
 211         if (ret)
 212                 return ret;
 213
 214         /* Capture the data from cr_data_out[] */
 215         *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
 216
 217         /* Deassert cr_read */
 218         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
 219         if (ret)
 220                 return ret;
 221
 222         return 0;
 223 }
 224
 225 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
 226 {
 227         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 228         void __iomem *mmio = hpriv->mmio;
 229         int timeout = 10;
 230         u16 val;
 231         int ret;
 232
 233         if (imxpriv->type == AHCI_IMX6QP) {
 234                 /* 6qp adds the sata reset mechanism, use it for 6qp sata */
 235                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 236                                    IMX6Q_GPR5_SATA_SW_PD, 0);
 237
 238                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 239                                    IMX6Q_GPR5_SATA_SW_RST, 0);
 240                 udelay(50);
 241                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 242                                    IMX6Q_GPR5_SATA_SW_RST,
 243                                    IMX6Q_GPR5_SATA_SW_RST);
 244                 return 0;
 245         }
 246
 247         /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
 248         ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
 249         if (ret)
 250                 return ret;
 251         ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
 252         if (ret)
 253                 return ret;
 254
 255         /* Wait for PHY RX_PLL to be stable */
 256         do {
 257                 usleep_range(100, 200);
 258                 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
 259                 if (ret)
 260                         return ret;
 261                 ret = imx_phy_reg_read(&val, mmio);
 262                 if (ret)
 263                         return ret;
 264                 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
 265                         break;
 266         } while (--timeout);
 267
 268         return timeout ? 0 : -ETIMEDOUT;
 269 }
 270
 271 enum {
 272         /* SATA PHY Register */
 273         SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
 274         SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
 275         SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
 276         SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
 277         SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
 278 };
 279
 280 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
 281 {
 282         u16 adc_out_reg, read_sum;
 283         u32 index, read_attempt;
 284         const u32 attempt_limit = 200;
 285
 286         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
 287         imx_phy_reg_write(rtune_ctl_reg, mmio);
 288
 289         /* two dummy read */
 290         index = 0;
 291         read_attempt = 0;
 292         adc_out_reg = 0;
 293         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
 294         while (index < 2) {
 295                 imx_phy_reg_read(&adc_out_reg, mmio);
 296                 /* check if valid */
 297                 if (adc_out_reg & 0x400)
 298                         index++;
 299
 300                 read_attempt++;
 301                 if (read_attempt > attempt_limit) {
 302                         dev_err(dev, "Read REG more than %d times!\n",
 303                                 attempt_limit);
 304                         break;
 305                 }
 306         }
 307
 308         index = 0;
 309         read_attempt = 0;
 310         read_sum = 0;
 311         while (index < 80) {
 312                 imx_phy_reg_read(&adc_out_reg, mmio);
 313                 if (adc_out_reg & 0x400) {
 314                         read_sum = read_sum + (adc_out_reg & 0x3FF);
 315                         index++;
 316                 }
 317                 read_attempt++;
 318                 if (read_attempt > attempt_limit) {
 319                         dev_err(dev, "Read REG more than %d times!\n",
 320                                 attempt_limit);
 321                         break;
 322                 }
 323         }
 324
 325         /* Use the U32 to make 1000 precision */
 326         return (read_sum * 1000) / 80;
 327 }
 328
 329 /* SATA AHCI temperature monitor */
 330 static int sata_ahci_read_temperature(void *dev, int *temp)
 331 {
 332         u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
 333         u32 str1, str2, str3, str4;
 334         int m1, m2, a;
 335         struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
 336         void __iomem *mmio = hpriv->mmio;
 337
 338         /* check rd-wr to reg */
 339         read_sum = 0;
 340         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
 341         imx_phy_reg_write(read_sum, mmio);
 342         imx_phy_reg_read(&read_sum, mmio);
 343         if ((read_sum & 0xffff) != 0)
 344                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
 345
 346         imx_phy_reg_write(0x5A5A, mmio);
 347         imx_phy_reg_read(&read_sum, mmio);
 348         if ((read_sum & 0xffff) != 0x5A5A)
 349                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
 350
 351         imx_phy_reg_write(0x1234, mmio);
 352         imx_phy_reg_read(&read_sum, mmio);
 353         if ((read_sum & 0xffff) != 0x1234)
 354                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
 355
 356         /* start temperature test */
 357         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
 358         imx_phy_reg_read(&mpll_test_reg, mmio);
 359         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
 360         imx_phy_reg_read(&rtune_ctl_reg, mmio);
 361         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
 362         imx_phy_reg_read(&dac_ctl_reg, mmio);
 363
 364         /* mpll_tst.meas_iv   ([12:2]) */
 365         str1 = (mpll_test_reg >> 2) & 0x7FF;
 366         /* rtune_ctl.mode     ([1:0]) */
 367         str2 = (rtune_ctl_reg) & 0x3;
 368         /* dac_ctl.dac_mode   ([14:12]) */
 369         str3 = (dac_ctl_reg >> 12)  & 0x7;
 370         /* rtune_ctl.sel_atbp ([4]) */
 371         str4 = (rtune_ctl_reg >> 4);
 372
 373         /* Calculate the m1 */
 374         /* mpll_tst.meas_iv */
 375         mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
 376         /* rtune_ctl.mode */
 377         rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
 378         /* dac_ctl.dac_mode */
 379         dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
 380         /* rtune_ctl.sel_atbp */
 381         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
 382         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
 383         imx_phy_reg_write(mpll_test_reg, mmio);
 384         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
 385         imx_phy_reg_write(dac_ctl_reg, mmio);
 386         m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
 387
 388         /* Calculate the m2 */
 389         /* rtune_ctl.sel_atbp */
 390         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
 391         m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
 392
 393         /* restore the status  */
 394         /* mpll_tst.meas_iv */
 395         mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
 396         /* rtune_ctl.mode */
 397         rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
 398         /* dac_ctl.dac_mode */
 399         dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
 400         /* rtune_ctl.sel_atbp */
 401         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
 402
 403         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
 404         imx_phy_reg_write(mpll_test_reg, mmio);
 405         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
 406         imx_phy_reg_write(dac_ctl_reg, mmio);
 407         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
 408         imx_phy_reg_write(rtune_ctl_reg, mmio);
 409
 410         /* Compute temperature */
 411         if (!(m2 / 1000))
 412                 m2 = 1000;
 413         a = (m2 - m1) / (m2/1000);
 414         *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
 415
 416         return 0;
 417 }
 418
 419 static ssize_t sata_ahci_show_temp(struct device *dev,
 420                                    struct device_attribute *da,
 421                                    char *buf)
 422 {
 423         unsigned int temp = 0;
 424         int err;
 425
 426         err = sata_ahci_read_temperature(dev, &temp);
 427         if (err < 0)
 428                 return err;
 429
 430         return sprintf(buf, "%u\n", temp);
 431 }
 432
 433 static const struct thermal_zone_of_device_ops fsl_sata_ahci_of_thermal_ops = {
 434         .get_temp = sata_ahci_read_temperature,
 435 };
 436
 437 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
 438
 439 static struct attribute *fsl_sata_ahci_attrs[] = {
 440         &sensor_dev_attr_temp1_input.dev_attr.attr,
 441         NULL
 442 };
 443 ATTRIBUTE_GROUPS(fsl_sata_ahci);
 444
 445 static int imx8_sata_enable(struct ahci_host_priv *hpriv)
 446 {
 447         u32 val, reg;
 448         int i, ret;
 449         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 450         struct device *dev = &imxpriv->ahci_pdev->dev;
 451
 452         /* configure the hsio for sata */
 453         ret = clk_prepare_enable(imxpriv->phy_pclk0);
 454         if (ret < 0) {
 455                 dev_err(dev, "can't enable phy_pclk0.\n");
 456                 return ret;
 457         }
 458         ret = clk_prepare_enable(imxpriv->phy_pclk1);
 459         if (ret < 0) {
 460                 dev_err(dev, "can't enable phy_pclk1.\n");
 461                 goto disable_phy_pclk0;
 462         }
 463         ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
 464         if (ret < 0) {
 465                 dev_err(dev, "can't enable epcs_tx_clk.\n");
 466                 goto disable_phy_pclk1;
 467         }
 468         ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
 469         if (ret < 0) {
 470                 dev_err(dev, "can't enable epcs_rx_clk.\n");
 471                 goto disable_epcs_tx_clk;
 472         }
 473         ret = clk_prepare_enable(imxpriv->phy_apbclk);
 474         if (ret < 0) {
 475                 dev_err(dev, "can't enable phy_apbclk.\n");
 476                 goto disable_epcs_rx_clk;
 477         }
 478         /* Configure PHYx2 PIPE_RSTN */
 479         regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
 480                         IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
 481         if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
 482                 /* The link of the PCIEA of HSIO is down */
 483                 regmap_update_bits(imxpriv->gpr,
 484                                 IMX8QM_CSR_PHYX2_OFFSET,
 485                                 IMX8QM_PHY_PIPE_RSTN_0 |
 486                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
 487                                 IMX8QM_PHY_PIPE_RSTN_0 |
 488                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
 489         }
 490         regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
 491                         IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
 492         if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
 493                 /* The link of the PCIEB of HSIO is down */
 494                 regmap_update_bits(imxpriv->gpr,
 495                                 IMX8QM_CSR_PHYX2_OFFSET,
 496                                 IMX8QM_PHY_PIPE_RSTN_1 |
 497                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
 498                                 IMX8QM_PHY_PIPE_RSTN_1 |
 499                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
 500         }
 501         if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
 502                 /* The links of both PCIA and PCIEB of HSIO are down */
 503                 regmap_update_bits(imxpriv->gpr,
 504                                 IMX8QM_LPCG_PHYX2_OFFSET,
 505                                 IMX8QM_LPCG_PHYX2_PCLK0_MASK |
 506                                 IMX8QM_LPCG_PHYX2_PCLK1_MASK,
 507                                 0);
 508         }
 509
 510         /* set PWR_RST and BT_RST of csr_pciea */
 511         val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
 512         regmap_update_bits(imxpriv->gpr,
 513                         val,
 514                         IMX8QM_CTRL_BUTTON_RST_N,
 515                         IMX8QM_CTRL_BUTTON_RST_N);
 516         regmap_update_bits(imxpriv->gpr,
 517                         val,
 518                         IMX8QM_CTRL_POWER_UP_RST_N,
 519                         IMX8QM_CTRL_POWER_UP_RST_N);
 520
 521         /* PHYX1_MODE to SATA */
 522         regmap_update_bits(imxpriv->gpr,
 523                         IMX8QM_CSR_PHYX1_OFFSET,
 524                         IMX8QM_PHY_MODE_MASK,
 525                         IMX8QM_PHY_MODE_SATA);
 526
 527         /*
 528          * BIT0 RXENA 1, BIT1 TXENA 0
 529          * BIT12 PHY_X1_EPCS_SEL 1.
 530          */
 531         regmap_update_bits(imxpriv->gpr,
 532                         IMX8QM_CSR_MISC_OFFSET,
 533                         IMX8QM_MISC_IOB_RXENA,
 534                         IMX8QM_MISC_IOB_RXENA);
 535         regmap_update_bits(imxpriv->gpr,
 536                         IMX8QM_CSR_MISC_OFFSET,
 537                         IMX8QM_MISC_IOB_TXENA,
 538                         0);
 539         regmap_update_bits(imxpriv->gpr,
 540                         IMX8QM_CSR_MISC_OFFSET,
 541                         IMX8QM_MISC_PHYX1_EPCS_SEL,
 542                         IMX8QM_MISC_PHYX1_EPCS_SEL);
 543         /*
 544          * It is possible, for PCIe and SATA are sharing
 545          * the same clock source, HPLL or external oscillator.
 546          * When PCIe is in low power modes (L1.X or L2 etc),
 547          * the clock source can be turned off. In this case,
 548          * if this clock source is required to be toggling by
 549          * SATA, then SATA functions will be abnormal.
 550          * Set the override here to avoid it.
 551          */
 552         regmap_update_bits(imxpriv->gpr,
 553                         IMX8QM_CSR_MISC_OFFSET,
 554                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
 555                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
 556                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
 557                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
 558                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
 559                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
 560                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
 561                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
 562
 563         /* clear PHY RST, then set it */
 564         regmap_update_bits(imxpriv->gpr,
 565                         IMX8QM_CSR_SATA_OFFSET,
 566                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
 567                         0);
 568
 569         regmap_update_bits(imxpriv->gpr,
 570                         IMX8QM_CSR_SATA_OFFSET,
 571                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
 572                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
 573
 574         /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
 575         regmap_update_bits(imxpriv->gpr,
 576                         IMX8QM_CSR_SATA_OFFSET,
 577                         IMX8QM_SATA_CTRL_RESET_N,
 578                         IMX8QM_SATA_CTRL_RESET_N);
 579         udelay(1);
 580         regmap_update_bits(imxpriv->gpr,
 581                         IMX8QM_CSR_SATA_OFFSET,
 582                         IMX8QM_SATA_CTRL_RESET_N,
 583                         0);
 584         regmap_update_bits(imxpriv->gpr,
 585                         IMX8QM_CSR_SATA_OFFSET,
 586                         IMX8QM_SATA_CTRL_RESET_N,
 587                         IMX8QM_SATA_CTRL_RESET_N);
 588
 589         /* APB reset */
 590         regmap_update_bits(imxpriv->gpr,
 591                         IMX8QM_CSR_PHYX1_OFFSET,
 592                         IMX8QM_PHY_APB_RSTN_0,
 593                         IMX8QM_PHY_APB_RSTN_0);
 594
 595         for (i = 0; i < 100; i++) {
 596                 reg = IMX8QM_CSR_PHYX1_OFFSET +
 597                         IMX8QM_CSR_PHYX_STTS0_OFFSET;
 598                 regmap_read(imxpriv->gpr, reg, &val);
 599                 val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
 600                 if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
 601                         break;
 602                 udelay(1);
 603         }
 604
 605         if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
 606                 dev_err(dev, "TX PLL of the PHY is not locked\n");
 607                 ret = -ENODEV;
 608         } else {
 609                 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
 610                                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
 611                 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
 612                                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
 613                 reg = readb(imxpriv->phy_base +
 614                                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
 615                 if (unlikely(reg != imxpriv->imped_ratio))
 616                         dev_info(dev, "Can't set PHY RX impedance ratio.\n");
 617                 reg = readb(imxpriv->phy_base +
 618                                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
 619                 if (unlikely(reg != imxpriv->imped_ratio))
 620                         dev_info(dev, "Can't set PHY TX impedance ratio.\n");
 621                 usleep_range(50, 100);
 622
 623                 /*
 624                  * To reduce the power consumption, gate off
 625                  * the PHY clks
 626                  */
 627                 clk_disable_unprepare(imxpriv->phy_apbclk);
 628                 clk_disable_unprepare(imxpriv->phy_pclk1);
 629                 clk_disable_unprepare(imxpriv->phy_pclk0);
 630                 return ret;
 631         }
 632
 633         clk_disable_unprepare(imxpriv->phy_apbclk);
 634 disable_epcs_rx_clk:
 635         clk_disable_unprepare(imxpriv->epcs_rx_clk);
 636 disable_epcs_tx_clk:
 637         clk_disable_unprepare(imxpriv->epcs_tx_clk);
 638 disable_phy_pclk1:
 639         clk_disable_unprepare(imxpriv->phy_pclk1);
 640 disable_phy_pclk0:
 641         clk_disable_unprepare(imxpriv->phy_pclk0);
 642
 643         return ret;
 644 }
 645
 646 static int imx_sata_enable(struct ahci_host_priv *hpriv)
 647 {
 648         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 649         struct device *dev = &imxpriv->ahci_pdev->dev;
 650         int ret;
 651
 652         if (imxpriv->no_device)
 653                 return 0;
 654
 655         ret = ahci_platform_enable_regulators(hpriv);
 656         if (ret)
 657                 return ret;
 658
 659         ret = clk_prepare_enable(imxpriv->sata_ref_clk);
 660         if (ret < 0)
 661                 goto disable_regulator;
 662
 663         if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
 664                 /*
 665                  * set PHY Paremeters, two steps to configure the GPR13,
 666                  * one write for rest of parameters, mask of first write
 667                  * is 0x07ffffff, and the other one write for setting
 668                  * the mpll_clk_en.
 669                  */
 670                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 671                                    IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
 672                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
 673                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
 674                                    IMX6Q_GPR13_SATA_SPD_MODE_MASK |
 675                                    IMX6Q_GPR13_SATA_MPLL_SS_EN |
 676                                    IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
 677                                    IMX6Q_GPR13_SATA_TX_BOOST_MASK |
 678                                    IMX6Q_GPR13_SATA_TX_LVL_MASK |
 679                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN |
 680                                    IMX6Q_GPR13_SATA_TX_EDGE_RATE,
 681                                    imxpriv->phy_params);
 682                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 683                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 684                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 685
 686                 usleep_range(100, 200);
 687
 688                 ret = imx_sata_phy_reset(hpriv);
 689                 if (ret) {
 690                         dev_err(dev, "failed to reset phy: %d\n", ret);
 691                         goto disable_clk;
 692                 }
 693         } else if (imxpriv->type == AHCI_IMX8QM) {
 694                 ret = imx8_sata_enable(hpriv);
 695         }
 696
 697         usleep_range(1000, 2000);
 698
 699         return 0;
 700
 701 disable_clk:
 702         clk_disable_unprepare(imxpriv->sata_ref_clk);
 703 disable_regulator:
 704         ahci_platform_disable_regulators(hpriv);
 705
 706         return ret;
 707 }
 708
 709 static void imx_sata_disable(struct ahci_host_priv *hpriv)
 710 {
 711         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 712
 713         if (imxpriv->no_device)
 714                 return;
 715
 716         switch (imxpriv->type) {
 717         case AHCI_IMX6QP:
 718                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
 719                                    IMX6Q_GPR5_SATA_SW_PD,
 720                                    IMX6Q_GPR5_SATA_SW_PD);
 721                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 722                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 723                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 724                 break;
 725
 726         case AHCI_IMX6Q:
 727                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 728                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 729                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 730                 break;
 731
 732         case AHCI_IMX8QM:
 733                 clk_disable_unprepare(imxpriv->epcs_rx_clk);
 734                 clk_disable_unprepare(imxpriv->epcs_tx_clk);
 735                 break;
 736
 737         default:
 738                 break;
 739         }
 740
 741         clk_disable_unprepare(imxpriv->sata_ref_clk);
 742
 743         ahci_platform_disable_regulators(hpriv);
 744 }
 745
 746 static void ahci_imx_error_handler(struct ata_port *ap)
 747 {
 748         u32 reg_val;
 749         struct ata_device *dev;
 750         struct ata_host *host = dev_get_drvdata(ap->dev);
 751         struct ahci_host_priv *hpriv = host->private_data;
 752         void __iomem *mmio = hpriv->mmio;
 753         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 754
 755         ahci_error_handler(ap);
 756
 757         if (!(imxpriv->first_time) || ahci_imx_hotplug)
 758                 return;
 759
 760         imxpriv->first_time = false;
 761
 762         ata_for_each_dev(dev, &ap->link, ENABLED)
 763                 return;
 764         /*
 765          * Disable link to save power.  An imx ahci port can't be recovered
 766          * without full reset once the pddq mode is enabled making it
 767          * impossible to use as part of libata LPM.
 768          */
 769         reg_val = readl(mmio + IMX_P0PHYCR);
 770         writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
 771         imx_sata_disable(hpriv);
 772         imxpriv->no_device = true;
 773
 774         dev_info(ap->dev, "no device found, disabling link.\n");
 775         dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
 776 }
 777
 778 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
 779                        unsigned long deadline)
 780 {
 781         struct ata_port *ap = link->ap;
 782         struct ata_host *host = dev_get_drvdata(ap->dev);
 783         struct ahci_host_priv *hpriv = host->private_data;
 784         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 785         int ret;
 786
 787         if (imxpriv->type == AHCI_IMX53)
 788                 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
 789         else
 790                 ret = ahci_ops.softreset(link, class, deadline);
 791
 792         return ret;
 793 }
 794
 795 static struct ata_port_operations ahci_imx_ops = {
 796         .inherits       = &ahci_ops,
 797         .host_stop      = ahci_imx_host_stop,
 798         .error_handler  = ahci_imx_error_handler,
 799         .softreset      = ahci_imx_softreset,
 800 };
 801
 802 static const struct ata_port_info ahci_imx_port_info = {
 803         .flags          = AHCI_FLAG_COMMON,
 804         .pio_mask       = ATA_PIO4,
 805         .udma_mask      = ATA_UDMA6,
 806         .port_ops       = &ahci_imx_ops,
 807 };
 808
 809 static const struct of_device_id imx_ahci_of_match[] = {
 810         { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
 811         { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
 812         { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
 813         { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
 814         {},
 815 };
 816 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
 817
 818 struct reg_value {
 819         u32 of_value;
 820         u32 reg_value;
 821 };
 822
 823 struct reg_property {
 824         const char *name;
 825         const struct reg_value *values;
 826         size_t num_values;
 827         u32 def_value;
 828         u32 set_value;
 829 };
 830
 831 static const struct reg_value gpr13_tx_level[] = {
 832         {  937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
 833         {  947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
 834         {  957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
 835         {  966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
 836         {  976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
 837         {  986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
 838         {  996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
 839         { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
 840         { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
 841         { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
 842         { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
 843         { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
 844         { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
 845         { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
 846         { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
 847         { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
 848         { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
 849         { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
 850         { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
 851         { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
 852         { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
 853         { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
 854         { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
 855         { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
 856         { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
 857         { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
 858         { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
 859         { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
 860         { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
 861         { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
 862         { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
 863         { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
 864 };
 865
 866 static const struct reg_value gpr13_tx_boost[] = {
 867         {    0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
 868         {  370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
 869         {  740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
 870         { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
 871         { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
 872         { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
 873         { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
 874         { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
 875         { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
 876         { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
 877         { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
 878         { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
 879         { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
 880         { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
 881         { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
 882         { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
 883 };
 884
 885 static const struct reg_value gpr13_tx_atten[] = {
 886         {  8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
 887         {  9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
 888         { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
 889         { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
 890         { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
 891         { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
 892 };
 893
 894 static const struct reg_value gpr13_rx_eq[] = {
 895         {  500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
 896         { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
 897         { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
 898         { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
 899         { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
 900         { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
 901         { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
 902         { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
 903 };
 904
 905 static const struct reg_property gpr13_props[] = {
 906         {
 907                 .name = "fsl,transmit-level-mV",
 908                 .values = gpr13_tx_level,
 909                 .num_values = ARRAY_SIZE(gpr13_tx_level),
 910                 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
 911         }, {
 912                 .name = "fsl,transmit-boost-mdB",
 913                 .values = gpr13_tx_boost,
 914                 .num_values = ARRAY_SIZE(gpr13_tx_boost),
 915                 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
 916         }, {
 917                 .name = "fsl,transmit-atten-16ths",
 918                 .values = gpr13_tx_atten,
 919                 .num_values = ARRAY_SIZE(gpr13_tx_atten),
 920                 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
 921         }, {
 922                 .name = "fsl,receive-eq-mdB",
 923                 .values = gpr13_rx_eq,
 924                 .num_values = ARRAY_SIZE(gpr13_rx_eq),
 925                 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
 926         }, {
 927                 .name = "fsl,no-spread-spectrum",
 928                 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
 929                 .set_value = 0,
 930         },
 931 };
 932
 933 static u32 imx_ahci_parse_props(struct device *dev,
 934                                 const struct reg_property *prop, size_t num)
 935 {
 936         struct device_node *np = dev->of_node;
 937         u32 reg_value = 0;
 938         int i, j;
 939
 940         for (i = 0; i < num; i++, prop++) {
 941                 u32 of_val;
 942
 943                 if (prop->num_values == 0) {
 944                         if (of_property_read_bool(np, prop->name))
 945                                 reg_value |= prop->set_value;
 946                         else
 947                                 reg_value |= prop->def_value;
 948                         continue;
 949                 }
 950
 951                 if (of_property_read_u32(np, prop->name, &of_val)) {
 952                         dev_info(dev, "%s not specified, using %08x\n",
 953                                 prop->name, prop->def_value);
 954                         reg_value |= prop->def_value;
 955                         continue;
 956                 }
 957
 958                 for (j = 0; j < prop->num_values; j++) {
 959                         if (prop->values[j].of_value == of_val) {
 960                                 dev_info(dev, "%s value %u, using %08x\n",
 961                                         prop->name, of_val, prop->values[j].reg_value);
 962                                 reg_value |= prop->values[j].reg_value;
 963                                 break;
 964                         }
 965                 }
 966
 967                 if (j == prop->num_values) {
 968                         dev_err(dev, "DT property %s is not a valid value\n",
 969                                 prop->name);
 970                         reg_value |= prop->def_value;
 971                 }
 972         }
 973
 974         return reg_value;
 975 }
 976
 977 static struct scsi_host_template ahci_platform_sht = {
 978         AHCI_SHT(DRV_NAME),
 979 };
 980
 981 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
 982 {
 983         struct resource *phy_res;
 984         struct platform_device *pdev = imxpriv->ahci_pdev;
 985         struct device_node *np = dev->of_node;
 986
 987         if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
 988                 imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
 989         phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
 990         if (phy_res) {
 991                 imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
 992                                         resource_size(phy_res));
 993                 if (!imxpriv->phy_base) {
 994                         dev_err(dev, "error with ioremap\n");
 995                         return -ENOMEM;
 996                 }
 997         } else {
 998                 dev_err(dev, "missing *phy* reg region.\n");
 999                 return -ENOMEM;
1000         }
1001         imxpriv->gpr =
1002                  syscon_regmap_lookup_by_phandle(np, "hsio");
1003         if (IS_ERR(imxpriv->gpr)) {
1004                 dev_err(dev, "unable to find gpr registers\n");
1005                 return PTR_ERR(imxpriv->gpr);
1006         }
1007
1008         imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
1009         if (IS_ERR(imxpriv->epcs_tx_clk)) {
1010                 dev_err(dev, "can't get epcs_tx_clk clock.\n");
1011                 return PTR_ERR(imxpriv->epcs_tx_clk);
1012         }
1013         imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
1014         if (IS_ERR(imxpriv->epcs_rx_clk)) {
1015                 dev_err(dev, "can't get epcs_rx_clk clock.\n");
1016                 return PTR_ERR(imxpriv->epcs_rx_clk);
1017         }
1018         imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
1019         if (IS_ERR(imxpriv->phy_pclk0)) {
1020                 dev_err(dev, "can't get phy_pclk0 clock.\n");
1021                 return PTR_ERR(imxpriv->phy_pclk0);
1022         }
1023         imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
1024         if (IS_ERR(imxpriv->phy_pclk1)) {
1025                 dev_err(dev, "can't get phy_pclk1 clock.\n");
1026                 return PTR_ERR(imxpriv->phy_pclk1);
1027         }
1028         imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
1029         if (IS_ERR(imxpriv->phy_apbclk)) {
1030                 dev_err(dev, "can't get phy_apbclk clock.\n");
1031                 return PTR_ERR(imxpriv->phy_apbclk);
1032         }
1033
1034         /* Fetch GPIO, then enable the external OSC */
1035         imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
1036                                 GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1037         if (IS_ERR(imxpriv->clkreq_gpiod))
1038                 return PTR_ERR(imxpriv->clkreq_gpiod);
1039         if (imxpriv->clkreq_gpiod)
1040                 gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
1041
1042         return 0;
1043 }
1044
1045 static int imx_ahci_probe(struct platform_device *pdev)
1046 {
1047         struct device *dev = &pdev->dev;
1048         const struct of_device_id *of_id;
1049         struct ahci_host_priv *hpriv;
1050         struct imx_ahci_priv *imxpriv;
1051         unsigned int reg_val;
1052         int ret;
1053
1054         of_id = of_match_device(imx_ahci_of_match, dev);
1055         if (!of_id)
1056                 return -EINVAL;
1057
1058         imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
1059         if (!imxpriv)
1060                 return -ENOMEM;
1061
1062         imxpriv->ahci_pdev = pdev;
1063         imxpriv->no_device = false;
1064         imxpriv->first_time = true;
1065         imxpriv->type = (enum ahci_imx_type)of_id->data;
1066
1067         imxpriv->sata_clk = devm_clk_get(dev, "sata");
1068         if (IS_ERR(imxpriv->sata_clk)) {
1069                 dev_err(dev, "can't get sata clock.\n");
1070                 return PTR_ERR(imxpriv->sata_clk);
1071         }
1072
1073         imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
1074         if (IS_ERR(imxpriv->sata_ref_clk)) {
1075                 dev_err(dev, "can't get sata_ref clock.\n");
1076                 return PTR_ERR(imxpriv->sata_ref_clk);
1077         }
1078
1079         imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
1080         if (IS_ERR(imxpriv->ahb_clk)) {
1081                 dev_err(dev, "can't get ahb clock.\n");
1082                 return PTR_ERR(imxpriv->ahb_clk);
1083         }
1084
1085         if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
1086                 u32 reg_value;
1087
1088                 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
1089                                                         "fsl,imx6q-iomuxc-gpr");
1090                 if (IS_ERR(imxpriv->gpr)) {
1091                         dev_err(dev,
1092                                 "failed to find fsl,imx6q-iomux-gpr regmap\n");
1093                         return PTR_ERR(imxpriv->gpr);
1094                 }
1095
1096                 reg_value = imx_ahci_parse_props(dev, gpr13_props,
1097                                                  ARRAY_SIZE(gpr13_props));
1098
1099                 imxpriv->phy_params =
1100                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
1101                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
1102                                    IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
1103                                    reg_value;
1104         } else if (imxpriv->type == AHCI_IMX8QM) {
1105                 ret =  imx8_sata_probe(dev, imxpriv);
1106                 if (ret)
1107                         return ret;
1108         }
1109
1110         hpriv = ahci_platform_get_resources(pdev, 0);
1111         if (IS_ERR(hpriv))
1112                 return PTR_ERR(hpriv);
1113
1114         hpriv->plat_data = imxpriv;
1115
1116         ret = clk_prepare_enable(imxpriv->sata_clk);
1117         if (ret)
1118                 return ret;
1119
1120         if (imxpriv->type == AHCI_IMX53 &&
1121             IS_ENABLED(CONFIG_HWMON)) {
1122                 /* Add the temperature monitor */
1123                 struct device *hwmon_dev;
1124
1125                 hwmon_dev =
1126                         devm_hwmon_device_register_with_groups(dev,
1127                                                         "sata_ahci",
1128                                                         hpriv,
1129                                                         fsl_sata_ahci_groups);
1130                 if (IS_ERR(hwmon_dev)) {
1131                         ret = PTR_ERR(hwmon_dev);
1132                         goto disable_clk;
1133                 }
1134                 devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev,
1135                                              &fsl_sata_ahci_of_thermal_ops);
1136                 dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
1137         }
1138
1139         ret = imx_sata_enable(hpriv);
1140         if (ret)
1141                 goto disable_clk;
1142
1143         /*
1144          * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
1145          * and IP vendor specific register IMX_TIMER1MS.
1146          * Configure CAP_SSS (support stagered spin up).
1147          * Implement the port0.
1148          * Get the ahb clock rate, and configure the TIMER1MS register.
1149          */
1150         reg_val = readl(hpriv->mmio + HOST_CAP);
1151         if (!(reg_val & HOST_CAP_SSS)) {
1152                 reg_val |= HOST_CAP_SSS;
1153                 writel(reg_val, hpriv->mmio + HOST_CAP);
1154         }
1155         reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
1156         if (!(reg_val & 0x1)) {
1157                 reg_val |= 0x1;
1158                 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
1159         }
1160
1161         reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
1162         writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
1163
1164         ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
1165                                       &ahci_platform_sht);
1166         if (ret)
1167                 goto disable_sata;
1168
1169         return 0;
1170
1171 disable_sata:
1172         imx_sata_disable(hpriv);
1173 disable_clk:
1174         clk_disable_unprepare(imxpriv->sata_clk);
1175         return ret;
1176 }
1177
1178 static void ahci_imx_host_stop(struct ata_host *host)
1179 {
1180         struct ahci_host_priv *hpriv = host->private_data;
1181         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
1182
1183         imx_sata_disable(hpriv);
1184         clk_disable_unprepare(imxpriv->sata_clk);
1185 }
1186
1187 #ifdef CONFIG_PM_SLEEP
1188 static int imx_ahci_suspend(struct device *dev)
1189 {
1190         struct ata_host *host = dev_get_drvdata(dev);
1191         struct ahci_host_priv *hpriv = host->private_data;
1192         int ret;
1193
1194         ret = ahci_platform_suspend_host(dev);
1195         if (ret)
1196                 return ret;
1197
1198         imx_sata_disable(hpriv);
1199
1200         return 0;
1201 }
1202
1203 static int imx_ahci_resume(struct device *dev)
1204 {
1205         struct ata_host *host = dev_get_drvdata(dev);
1206         struct ahci_host_priv *hpriv = host->private_data;
1207         int ret;
1208
1209         ret = imx_sata_enable(hpriv);
1210         if (ret)
1211                 return ret;
1212
1213         return ahci_platform_resume_host(dev);
1214 }
1215 #endif
1216
1217 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
1218
1219 static struct platform_driver imx_ahci_driver = {
1220         .probe = imx_ahci_probe,
1221         .remove = ata_platform_remove_one,
1222         .driver = {
1223                 .name = DRV_NAME,
1224                 .of_match_table = imx_ahci_of_match,
1225                 .pm = &ahci_imx_pm_ops,
1226         },
1227 };
1228 module_platform_driver(imx_ahci_driver);
1229
1230 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
1231 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
1232 MODULE_LICENSE("GPL");
1233 MODULE_ALIAS("ahci:imx");