1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
50 /* board IDs by feature in alphabetical order */
54 board_ahci_no_debounce_delay,
60 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_sb700, /* for SB700 and SB800 */
72 * board IDs for Intel chipsets that support more than 6 ports
73 * *and* end up needing the PCS quirk.
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void ahci_remove_one(struct pci_dev *dev);
86 static void ahci_shutdown_one(struct pci_dev *dev);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
92 static bool is_mcp89_apple(struct pci_dev *pdev);
93 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
96 static int ahci_pci_device_runtime_suspend(struct device *dev);
97 static int ahci_pci_device_runtime_resume(struct device *dev);
98 #ifdef CONFIG_PM_SLEEP
99 static int ahci_pci_device_suspend(struct device *dev);
100 static int ahci_pci_device_resume(struct device *dev);
102 #endif /* CONFIG_PM */
104 static struct scsi_host_template ahci_sht = {
108 static struct ata_port_operations ahci_vt8251_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_vt8251_hardreset,
113 static struct ata_port_operations ahci_p5wdh_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_p5wdh_hardreset,
118 static struct ata_port_operations ahci_avn_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_avn_hardreset,
123 static const struct ata_port_info ahci_port_info[] = {
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
131 [board_ahci_ign_iferr] = {
132 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
138 [board_ahci_low_power] = {
139 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
145 [board_ahci_no_debounce_delay] = {
146 .flags = AHCI_FLAG_COMMON,
147 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
152 [board_ahci_nomsi] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
159 [board_ahci_noncq] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
166 [board_ahci_nosntf] = {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_ops,
173 [board_ahci_yes_fbs] = {
174 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
182 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_avn_ops,
194 [board_ahci_mcp65] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
197 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_ops,
202 [board_ahci_mcp77] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_ops,
209 [board_ahci_mcp89] = {
210 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
218 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
219 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
224 [board_ahci_sb600] = {
225 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
226 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
227 AHCI_HFLAG_32BIT_ONLY),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_pmp_retry_srst_ops,
233 [board_ahci_sb700] = { /* for SB700 and SB800 */
234 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
235 .flags = AHCI_FLAG_COMMON,
236 .pio_mask = ATA_PIO4,
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &ahci_pmp_retry_srst_ops,
240 [board_ahci_vt8251] = {
241 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
242 .flags = AHCI_FLAG_COMMON,
243 .pio_mask = ATA_PIO4,
244 .udma_mask = ATA_UDMA6,
245 .port_ops = &ahci_vt8251_ops,
247 [board_ahci_pcs7] = {
248 .flags = AHCI_FLAG_COMMON,
249 .pio_mask = ATA_PIO4,
250 .udma_mask = ATA_UDMA6,
251 .port_ops = &ahci_ops,
255 static const struct pci_device_id ahci_pci_tbl[] = {
257 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
258 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
259 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
260 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
261 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
262 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
263 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
264 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
265 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
266 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
267 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
268 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
269 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
270 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
271 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
272 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
273 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
274 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
275 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
277 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
278 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
279 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
280 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
281 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
282 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
283 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
285 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
286 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
287 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
288 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
289 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
290 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
291 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
292 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
293 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
294 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
295 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
296 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
297 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
319 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
320 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
321 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
322 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
323 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
324 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
325 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
326 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
327 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG/Lewisburg RAID*/
328 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
329 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
330 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
331 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
332 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
333 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
334 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
335 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
336 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
337 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
338 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
339 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
340 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
341 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
342 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
343 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
344 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
345 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
346 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
347 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
352 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
353 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
363 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
369 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
370 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg/Lewisburg RAID*/
371 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
372 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
373 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
374 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
375 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
376 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
377 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
378 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
379 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
380 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
381 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
382 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
383 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
384 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
385 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
386 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
387 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
388 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
389 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
390 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
391 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
392 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
393 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
394 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
395 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
396 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
397 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
398 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
399 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
400 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
401 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
402 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
403 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
404 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
405 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
406 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
410 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
411 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
412 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
413 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
414 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
415 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
416 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
417 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
418 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
419 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
420 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
421 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
422 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
424 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
425 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
426 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
427 /* JMicron 362B and 362C have an AHCI function with IDE class code */
428 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
429 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
430 /* May need to update quirk_jmicron_async_suspend() for additions */
433 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
434 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
437 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
438 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
441 /* Amazon's Annapurna Labs support */
442 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
443 .class = PCI_CLASS_STORAGE_SATA_AHCI,
444 .class_mask = 0xffffff,
447 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
448 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
449 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
450 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
451 /* AMD is using RAID class only for ahci controllers */
452 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
453 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
456 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
457 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
460 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
461 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
464 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
465 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
466 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
467 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
468 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
469 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
470 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
471 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
472 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
479 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
480 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
481 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
482 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
483 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
493 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
495 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
507 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
508 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
509 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
510 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
511 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
519 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
520 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
521 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
522 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
523 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
531 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
532 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
533 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
534 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
535 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
538 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
539 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
540 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
541 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
542 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
543 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
544 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
545 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
546 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
547 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
551 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
552 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
554 /* ST Microelectronics */
555 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
558 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
559 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
561 .class = PCI_CLASS_STORAGE_SATA_AHCI,
562 .class_mask = 0xffffff,
563 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
565 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
566 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
567 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
568 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
570 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
572 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
574 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
576 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
577 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
578 .driver_data = board_ahci_yes_fbs },
579 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
580 .driver_data = board_ahci_yes_fbs },
581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
582 .driver_data = board_ahci_yes_fbs },
583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
584 .driver_data = board_ahci_yes_fbs },
585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
586 .driver_data = board_ahci_no_debounce_delay },
587 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
588 .driver_data = board_ahci_yes_fbs },
589 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
590 .driver_data = board_ahci_yes_fbs },
593 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
594 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
597 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
598 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
599 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
600 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
601 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
602 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
603 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */
606 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
607 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
609 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
610 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
613 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
616 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
618 /* Generic, PCI class code for AHCI */
619 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
620 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
622 { } /* terminate list */
625 static const struct dev_pm_ops ahci_pci_pm_ops = {
626 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
627 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
628 ahci_pci_device_runtime_resume, NULL)
631 static struct pci_driver ahci_pci_driver = {
633 .id_table = ahci_pci_tbl,
634 .probe = ahci_init_one,
635 .remove = ahci_remove_one,
636 .shutdown = ahci_shutdown_one,
638 .pm = &ahci_pci_pm_ops,
642 #if IS_ENABLED(CONFIG_PATA_MARVELL)
643 static int marvell_enable;
645 static int marvell_enable = 1;
647 module_param(marvell_enable, int, 0644);
648 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
650 static int mobile_lpm_policy = -1;
651 module_param(mobile_lpm_policy, int, 0644);
652 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
654 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
655 struct ahci_host_priv *hpriv)
657 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
658 dev_info(&pdev->dev, "JMB361 has only one port\n");
659 hpriv->force_port_map = 1;
663 * Temporary Marvell 6145 hack: PATA port presence
664 * is asserted through the standard AHCI port
665 * presence register, as bit 4 (counting from 0)
667 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
668 if (pdev->device == 0x6121)
669 hpriv->mask_port_map = 0x3;
671 hpriv->mask_port_map = 0xf;
673 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
676 ahci_save_initial_config(&pdev->dev, hpriv);
679 static void ahci_pci_init_controller(struct ata_host *host)
681 struct ahci_host_priv *hpriv = host->private_data;
682 struct pci_dev *pdev = to_pci_dev(host->dev);
683 void __iomem *port_mmio;
687 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
688 if (pdev->device == 0x6121)
692 port_mmio = __ahci_port_base(host, mv);
694 writel(0, port_mmio + PORT_IRQ_MASK);
697 tmp = readl(port_mmio + PORT_IRQ_STAT);
698 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
700 writel(tmp, port_mmio + PORT_IRQ_STAT);
703 ahci_init_controller(host);
706 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
707 unsigned long deadline)
709 struct ata_port *ap = link->ap;
710 struct ahci_host_priv *hpriv = ap->host->private_data;
714 hpriv->stop_engine(ap);
716 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
717 deadline, &online, NULL);
719 hpriv->start_engine(ap);
721 /* vt8251 doesn't clear BSY on signature FIS reception,
722 * request follow-up softreset.
724 return online ? -EAGAIN : rc;
727 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
728 unsigned long deadline)
730 struct ata_port *ap = link->ap;
731 struct ahci_port_priv *pp = ap->private_data;
732 struct ahci_host_priv *hpriv = ap->host->private_data;
733 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
734 struct ata_taskfile tf;
738 hpriv->stop_engine(ap);
740 /* clear D2H reception area to properly wait for D2H FIS */
741 ata_tf_init(link->device, &tf);
742 tf.status = ATA_BUSY;
743 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
745 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
746 deadline, &online, NULL);
748 hpriv->start_engine(ap);
750 /* The pseudo configuration device on SIMG4726 attached to
751 * ASUS P5W-DH Deluxe doesn't send signature FIS after
752 * hardreset if no device is attached to the first downstream
753 * port && the pseudo device locks up on SRST w/ PMP==0. To
754 * work around this, wait for !BSY only briefly. If BSY isn't
755 * cleared, perform CLO and proceed to IDENTIFY (achieved by
756 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
758 * Wait for two seconds. Devices attached to downstream port
759 * which can't process the following IDENTIFY after this will
760 * have to be reset again. For most cases, this should
761 * suffice while making probing snappish enough.
764 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
767 ahci_kick_engine(ap);
773 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
775 * It has been observed with some SSDs that the timing of events in the
776 * link synchronization phase can leave the port in a state that can not
777 * be recovered by a SATA-hard-reset alone. The failing signature is
778 * SStatus.DET stuck at 1 ("Device presence detected but Phy
779 * communication not established"). It was found that unloading and
780 * reloading the driver when this problem occurs allows the drive
781 * connection to be recovered (DET advanced to 0x3). The critical
782 * component of reloading the driver is that the port state machines are
783 * reset by bouncing "port enable" in the AHCI PCS configuration
784 * register. So, reproduce that effect by bouncing a port whenever we
785 * see DET==1 after a reset.
787 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
788 unsigned long deadline)
790 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
791 struct ata_port *ap = link->ap;
792 struct ahci_port_priv *pp = ap->private_data;
793 struct ahci_host_priv *hpriv = ap->host->private_data;
794 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
795 unsigned long tmo = deadline - jiffies;
796 struct ata_taskfile tf;
800 hpriv->stop_engine(ap);
802 for (i = 0; i < 2; i++) {
805 int port = ap->port_no;
806 struct ata_host *host = ap->host;
807 struct pci_dev *pdev = to_pci_dev(host->dev);
809 /* clear D2H reception area to properly wait for D2H FIS */
810 ata_tf_init(link->device, &tf);
811 tf.status = ATA_BUSY;
812 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
814 rc = sata_link_hardreset(link, timing, deadline, &online,
817 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
818 (sstatus & 0xf) != 1)
821 ata_link_info(link, "avn bounce port%d\n", port);
823 pci_read_config_word(pdev, 0x92, &val);
825 pci_write_config_word(pdev, 0x92, val);
826 ata_msleep(ap, 1000);
828 pci_write_config_word(pdev, 0x92, val);
832 hpriv->start_engine(ap);
835 *class = ahci_dev_classify(ap);
842 static void ahci_pci_disable_interrupts(struct ata_host *host)
844 struct ahci_host_priv *hpriv = host->private_data;
845 void __iomem *mmio = hpriv->mmio;
848 /* AHCI spec rev1.1 section 8.3.3:
849 * Software must disable interrupts prior to requesting a
850 * transition of the HBA to D3 state.
852 ctl = readl(mmio + HOST_CTL);
854 writel(ctl, mmio + HOST_CTL);
855 readl(mmio + HOST_CTL); /* flush */
858 static int ahci_pci_device_runtime_suspend(struct device *dev)
860 struct pci_dev *pdev = to_pci_dev(dev);
861 struct ata_host *host = pci_get_drvdata(pdev);
863 ahci_pci_disable_interrupts(host);
867 static int ahci_pci_device_runtime_resume(struct device *dev)
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct ata_host *host = pci_get_drvdata(pdev);
873 rc = ahci_reset_controller(host);
876 ahci_pci_init_controller(host);
880 #ifdef CONFIG_PM_SLEEP
881 static int ahci_pci_device_suspend(struct device *dev)
883 struct pci_dev *pdev = to_pci_dev(dev);
884 struct ata_host *host = pci_get_drvdata(pdev);
885 struct ahci_host_priv *hpriv = host->private_data;
887 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
889 "BIOS update required for suspend/resume\n");
893 ahci_pci_disable_interrupts(host);
894 ata_host_suspend(host, PMSG_SUSPEND);
898 static int ahci_pci_device_resume(struct device *dev)
900 struct pci_dev *pdev = to_pci_dev(dev);
901 struct ata_host *host = pci_get_drvdata(pdev);
904 /* Apple BIOS helpfully mangles the registers on resume */
905 if (is_mcp89_apple(pdev))
906 ahci_mcp89_apple_enable(pdev);
908 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
909 rc = ahci_reset_controller(host);
913 ahci_pci_init_controller(host);
916 ata_host_resume(host);
922 #endif /* CONFIG_PM */
924 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
926 const int dma_bits = using_dac ? 64 : 32;
930 * If the device fixup already set the dma_mask to some non-standard
931 * value, don't extend it here. This happens on STA2X11, for example.
933 * XXX: manipulating the DMA mask from platform code is completely
934 * bogus, platform code should use dev->bus_dma_limit instead..
936 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
939 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
941 dev_err(&pdev->dev, "DMA enable failed\n");
945 static void ahci_pci_print_info(struct ata_host *host)
947 struct pci_dev *pdev = to_pci_dev(host->dev);
951 pci_read_config_word(pdev, 0x0a, &cc);
952 if (cc == PCI_CLASS_STORAGE_IDE)
954 else if (cc == PCI_CLASS_STORAGE_SATA)
956 else if (cc == PCI_CLASS_STORAGE_RAID)
961 ahci_print_info(host, scc_s);
964 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
965 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
966 * support PMP and the 4726 either directly exports the device
967 * attached to the first downstream port or acts as a hardware storage
968 * controller and emulate a single ATA device (can be RAID 0/1 or some
969 * other configuration).
971 * When there's no device attached to the first downstream port of the
972 * 4726, "Config Disk" appears, which is a pseudo ATA device to
973 * configure the 4726. However, ATA emulation of the device is very
974 * lame. It doesn't send signature D2H Reg FIS after the initial
975 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
977 * The following function works around the problem by always using
978 * hardreset on the port and not depending on receiving signature FIS
979 * afterward. If signature FIS isn't received soon, ATA class is
980 * assumed without follow-up softreset.
982 static void ahci_p5wdh_workaround(struct ata_host *host)
984 static const struct dmi_system_id sysids[] = {
986 .ident = "P5W DH Deluxe",
988 DMI_MATCH(DMI_SYS_VENDOR,
989 "ASUSTEK COMPUTER INC"),
990 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
995 struct pci_dev *pdev = to_pci_dev(host->dev);
997 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
998 dmi_check_system(sysids)) {
999 struct ata_port *ap = host->ports[1];
1001 dev_info(&pdev->dev,
1002 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1004 ap->ops = &ahci_p5wdh_ops;
1005 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1010 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1011 * booting in BIOS compatibility mode. We restore the registers but not ID.
1013 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1017 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1019 pci_read_config_dword(pdev, 0xf8, &val);
1021 /* the following changes the device ID, but appears not to affect function */
1022 /* val = (val & ~0xf0000000) | 0x80000000; */
1023 pci_write_config_dword(pdev, 0xf8, val);
1025 pci_read_config_dword(pdev, 0x54c, &val);
1027 pci_write_config_dword(pdev, 0x54c, val);
1029 pci_read_config_dword(pdev, 0x4a4, &val);
1032 pci_write_config_dword(pdev, 0x4a4, val);
1034 pci_read_config_dword(pdev, 0x54c, &val);
1036 pci_write_config_dword(pdev, 0x54c, val);
1038 pci_read_config_dword(pdev, 0xf8, &val);
1039 val &= ~(1 << 0x1b);
1040 pci_write_config_dword(pdev, 0xf8, val);
1043 static bool is_mcp89_apple(struct pci_dev *pdev)
1045 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1046 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1047 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1048 pdev->subsystem_device == 0xcb89;
1051 /* only some SB600 ahci controllers can do 64bit DMA */
1052 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1054 static const struct dmi_system_id sysids[] = {
1056 * The oldest version known to be broken is 0901 and
1057 * working is 1501 which was released on 2007-10-26.
1058 * Enable 64bit DMA on 1501 and anything newer.
1060 * Please read bko#9412 for more info.
1063 .ident = "ASUS M2A-VM",
1065 DMI_MATCH(DMI_BOARD_VENDOR,
1066 "ASUSTeK Computer INC."),
1067 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1069 .driver_data = "20071026", /* yyyymmdd */
1072 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1073 * support 64bit DMA.
1075 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1076 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1077 * This spelling mistake was fixed in BIOS version 1.5, so
1078 * 1.5 and later have the Manufacturer as
1079 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1080 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1082 * BIOS versions earlier than 1.9 had a Board Product Name
1083 * DMI field of "MS-7376". This was changed to be
1084 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1085 * match on DMI_BOARD_NAME of "MS-7376".
1088 .ident = "MSI K9A2 Platinum",
1090 DMI_MATCH(DMI_BOARD_VENDOR,
1091 "MICRO-STAR INTER"),
1092 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1096 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1099 * This board also had the typo mentioned above in the
1100 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1101 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1104 .ident = "MSI K9AGM2",
1106 DMI_MATCH(DMI_BOARD_VENDOR,
1107 "MICRO-STAR INTER"),
1108 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1112 * All BIOS versions for the Asus M3A support 64bit DMA.
1113 * (all release versions from 0301 to 1206 were tested)
1116 .ident = "ASUS M3A",
1118 DMI_MATCH(DMI_BOARD_VENDOR,
1119 "ASUSTeK Computer INC."),
1120 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1125 const struct dmi_system_id *match;
1126 int year, month, date;
1129 match = dmi_first_match(sysids);
1130 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1134 if (!match->driver_data)
1137 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1138 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1140 if (strcmp(buf, match->driver_data) >= 0)
1143 dev_warn(&pdev->dev,
1144 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1150 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1154 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1156 static const struct dmi_system_id broken_systems[] = {
1158 .ident = "HP Compaq nx6310",
1160 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1161 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1163 /* PCI slot number of the controller */
1164 .driver_data = (void *)0x1FUL,
1167 .ident = "HP Compaq 6720s",
1169 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1170 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1172 /* PCI slot number of the controller */
1173 .driver_data = (void *)0x1FUL,
1176 { } /* terminate list */
1178 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1181 unsigned long slot = (unsigned long)dmi->driver_data;
1182 /* apply the quirk only to on-board controllers */
1183 return slot == PCI_SLOT(pdev->devfn);
1189 static bool ahci_broken_suspend(struct pci_dev *pdev)
1191 static const struct dmi_system_id sysids[] = {
1193 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1194 * to the harddisk doesn't become online after
1195 * resuming from STR. Warn and fail suspend.
1197 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1199 * Use dates instead of versions to match as HP is
1200 * apparently recycling both product and version
1203 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1208 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1209 DMI_MATCH(DMI_PRODUCT_NAME,
1210 "HP Pavilion dv4 Notebook PC"),
1212 .driver_data = "20090105", /* F.30 */
1217 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1218 DMI_MATCH(DMI_PRODUCT_NAME,
1219 "HP Pavilion dv5 Notebook PC"),
1221 .driver_data = "20090506", /* F.16 */
1226 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1227 DMI_MATCH(DMI_PRODUCT_NAME,
1228 "HP Pavilion dv6 Notebook PC"),
1230 .driver_data = "20090423", /* F.21 */
1235 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1236 DMI_MATCH(DMI_PRODUCT_NAME,
1237 "HP HDX18 Notebook PC"),
1239 .driver_data = "20090430", /* F.23 */
1242 * Acer eMachines G725 has the same problem. BIOS
1243 * V1.03 is known to be broken. V3.04 is known to
1244 * work. Between, there are V1.06, V2.06 and V3.03
1245 * that we don't have much idea about. For now,
1246 * blacklist anything older than V3.04.
1248 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1253 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1254 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1256 .driver_data = "20091216", /* V3.04 */
1258 { } /* terminate list */
1260 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1261 int year, month, date;
1264 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1267 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1268 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1270 return strcmp(buf, dmi->driver_data) < 0;
1273 static bool ahci_broken_lpm(struct pci_dev *pdev)
1275 static const struct dmi_system_id sysids[] = {
1276 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1279 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1280 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1282 .driver_data = "20180406", /* 1.31 */
1286 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1287 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1289 .driver_data = "20180420", /* 1.28 */
1293 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1294 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1296 .driver_data = "20180315", /* 1.33 */
1300 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1301 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1304 * Note date based on release notes, 2.35 has been
1305 * reported to be good, but I've been unable to get
1306 * a hold of the reporter to get the DMI BIOS date.
1309 .driver_data = "20180310", /* 2.35 */
1311 { } /* terminate list */
1313 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1314 int year, month, date;
1320 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1321 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1323 return strcmp(buf, dmi->driver_data) < 0;
1326 static bool ahci_broken_online(struct pci_dev *pdev)
1328 #define ENCODE_BUSDEVFN(bus, slot, func) \
1329 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1330 static const struct dmi_system_id sysids[] = {
1332 * There are several gigabyte boards which use
1333 * SIMG5723s configured as hardware RAID. Certain
1334 * 5723 firmware revisions shipped there keep the link
1335 * online but fail to answer properly to SRST or
1336 * IDENTIFY when no device is attached downstream
1337 * causing libata to retry quite a few times leading
1338 * to excessive detection delay.
1340 * As these firmwares respond to the second reset try
1341 * with invalid device signature, considering unknown
1342 * sig as offline works around the problem acceptably.
1345 .ident = "EP45-DQ6",
1347 DMI_MATCH(DMI_BOARD_VENDOR,
1348 "Gigabyte Technology Co., Ltd."),
1349 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1351 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1354 .ident = "EP45-DS5",
1356 DMI_MATCH(DMI_BOARD_VENDOR,
1357 "Gigabyte Technology Co., Ltd."),
1358 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1360 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1362 { } /* terminate list */
1364 #undef ENCODE_BUSDEVFN
1365 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1371 val = (unsigned long)dmi->driver_data;
1373 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1376 static bool ahci_broken_devslp(struct pci_dev *pdev)
1378 /* device with broken DEVSLP but still showing SDS capability */
1379 static const struct pci_device_id ids[] = {
1380 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1384 return pci_match_id(ids, pdev);
1387 #ifdef CONFIG_ATA_ACPI
1388 static void ahci_gtf_filter_workaround(struct ata_host *host)
1390 static const struct dmi_system_id sysids[] = {
1392 * Aspire 3810T issues a bunch of SATA enable commands
1393 * via _GTF including an invalid one and one which is
1394 * rejected by the device. Among the successful ones
1395 * is FPDMA non-zero offset enable which when enabled
1396 * only on the drive side leads to NCQ command
1397 * failures. Filter it out.
1400 .ident = "Aspire 3810T",
1402 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1403 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1405 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1409 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1410 unsigned int filter;
1416 filter = (unsigned long)dmi->driver_data;
1417 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1418 filter, dmi->ident);
1420 for (i = 0; i < host->n_ports; i++) {
1421 struct ata_port *ap = host->ports[i];
1422 struct ata_link *link;
1423 struct ata_device *dev;
1425 ata_for_each_link(link, ap, EDGE)
1426 ata_for_each_dev(dev, link, ALL)
1427 dev->gtf_filter |= filter;
1431 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1436 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1437 * as DUMMY, or detected but eventually get a "link down" and never get up
1438 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1439 * port_map may hold a value of 0x00.
1441 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1442 * and can significantly reduce the occurrence of the problem.
1444 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1446 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1447 struct pci_dev *pdev)
1449 static const struct dmi_system_id sysids[] = {
1451 .ident = "Acer Switch Alpha 12",
1453 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1454 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1460 if (dmi_check_system(sysids)) {
1461 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1462 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1463 hpriv->port_map = 0x7;
1464 hpriv->cap = 0xC734FF02;
1471 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1472 * Workaround is to make sure all pending IRQs are served before leaving
1475 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1477 struct ata_host *host = dev_instance;
1478 struct ahci_host_priv *hpriv;
1479 unsigned int rc = 0;
1481 u32 irq_stat, irq_masked;
1482 unsigned int handled = 1;
1484 hpriv = host->private_data;
1486 irq_stat = readl(mmio + HOST_IRQ_STAT);
1491 irq_masked = irq_stat & hpriv->port_map;
1492 spin_lock(&host->lock);
1493 rc = ahci_handle_port_intr(host, irq_masked);
1496 writel(irq_stat, mmio + HOST_IRQ_STAT);
1497 irq_stat = readl(mmio + HOST_IRQ_STAT);
1498 spin_unlock(&host->lock);
1501 return IRQ_RETVAL(handled);
1505 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1506 struct ahci_host_priv *hpriv)
1512 * Check if this device might have remapped nvme devices.
1514 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1515 pci_resource_len(pdev, bar) < SZ_512K ||
1516 bar != AHCI_PCI_BAR_STANDARD ||
1517 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1520 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1521 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1522 if ((cap & (1 << i)) == 0)
1524 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1525 != PCI_CLASS_STORAGE_EXPRESS)
1528 /* We've found a remapped device */
1529 hpriv->remapped_nvme++;
1532 if (!hpriv->remapped_nvme)
1535 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1536 hpriv->remapped_nvme);
1537 dev_warn(&pdev->dev,
1538 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1541 * Don't rely on the msi-x capability in the remap case,
1542 * share the legacy interrupt across ahci and remapped devices.
1544 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1547 static int ahci_get_irq_vector(struct ata_host *host, int port)
1549 return pci_irq_vector(to_pci_dev(host->dev), port);
1552 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1553 struct ahci_host_priv *hpriv)
1557 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1561 * If number of MSIs is less than number of ports then Sharing Last
1562 * Message mode could be enforced. In this case assume that advantage
1563 * of multipe MSIs is negated and use single MSI mode instead.
1566 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1567 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1569 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1570 hpriv->get_irq_vector = ahci_get_irq_vector;
1571 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1576 * Fallback to single MSI mode if the controller
1577 * enforced MRSM mode.
1580 "ahci: MRSM is on, fallback to single MSI\n");
1581 pci_free_irq_vectors(pdev);
1586 * If the host is not capable of supporting per-port vectors, fall
1587 * back to single MSI before finally attempting single MSI-X.
1589 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1592 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1595 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1596 struct ahci_host_priv *hpriv)
1598 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1601 /* Ignore processing for chipsets that don't use policy */
1602 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1605 /* user modified policy via module param */
1606 if (mobile_lpm_policy != -1) {
1607 policy = mobile_lpm_policy;
1612 if (policy > ATA_LPM_MED_POWER &&
1613 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1614 if (hpriv->cap & HOST_CAP_PART)
1615 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1616 else if (hpriv->cap & HOST_CAP_SSC)
1617 policy = ATA_LPM_MIN_POWER;
1622 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1623 ap->target_lpm_policy = policy;
1626 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1628 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1632 * Only apply the 6-port PCS quirk for known legacy platforms.
1634 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1637 /* Skip applying the quirk on Denverton and beyond */
1638 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1642 * port_map is determined from PORTS_IMPL PCI register which is
1643 * implemented as write or write-once register. If the register
1644 * isn't programmed, ahci automatically generates it from number
1645 * of ports, which is good enough for PCS programming. It is
1646 * otherwise expected that platform firmware enables the ports
1647 * before the OS boots.
1649 pci_read_config_word(pdev, PCS_6, &tmp16);
1650 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1651 tmp16 |= hpriv->port_map;
1652 pci_write_config_word(pdev, PCS_6, tmp16);
1656 static ssize_t remapped_nvme_show(struct device *dev,
1657 struct device_attribute *attr,
1660 struct ata_host *host = dev_get_drvdata(dev);
1661 struct ahci_host_priv *hpriv = host->private_data;
1663 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1666 static DEVICE_ATTR_RO(remapped_nvme);
1668 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1670 unsigned int board_id = ent->driver_data;
1671 struct ata_port_info pi = ahci_port_info[board_id];
1672 const struct ata_port_info *ppi[] = { &pi, NULL };
1673 struct device *dev = &pdev->dev;
1674 struct ahci_host_priv *hpriv;
1675 struct ata_host *host;
1677 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1679 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1681 ata_print_version_once(&pdev->dev, DRV_VERSION);
1683 /* The AHCI driver can only drive the SATA ports, the PATA driver
1684 can drive them all so if both drivers are selected make sure
1685 AHCI stays out of the way */
1686 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1689 /* Apple BIOS on MCP89 prevents us using AHCI */
1690 if (is_mcp89_apple(pdev))
1691 ahci_mcp89_apple_enable(pdev);
1693 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1694 * At the moment, we can only use the AHCI mode. Let the users know
1695 * that for SAS drives they're out of luck.
1697 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1698 dev_info(&pdev->dev,
1699 "PDC42819 can only drive SATA devices with this driver\n");
1701 /* Some devices use non-standard BARs */
1702 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1703 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1704 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1705 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1706 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1707 if (pdev->device == 0xa01c)
1708 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1709 if (pdev->device == 0xa084)
1710 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1711 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1712 if (pdev->device == 0x7a08)
1713 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1716 /* acquire resources */
1717 rc = pcim_enable_device(pdev);
1721 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1722 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1725 /* ICH6s share the same PCI ID for both piix and ahci
1726 * modes. Enabling ahci mode while MAP indicates
1727 * combined mode is a bad idea. Yield to ata_piix.
1729 pci_read_config_byte(pdev, ICH_MAP, &map);
1731 dev_info(&pdev->dev,
1732 "controller is in combined mode, can't enable AHCI mode\n");
1737 /* AHCI controllers often implement SFF compatible interface.
1738 * Grab all PCI BARs just in case.
1740 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1742 pcim_pin_device(pdev);
1746 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1749 hpriv->flags |= (unsigned long)pi.private_data;
1751 /* MCP65 revision A1 and A2 can't do MSI */
1752 if (board_id == board_ahci_mcp65 &&
1753 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1754 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1756 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1757 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1758 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1760 /* only some SB600s can do 64bit DMA */
1761 if (ahci_sb600_enable_64bit(pdev))
1762 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1764 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1766 /* detect remapped nvme devices */
1767 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1769 sysfs_add_file_to_group(&pdev->dev.kobj,
1770 &dev_attr_remapped_nvme.attr,
1773 /* must set flag prior to save config in order to take effect */
1774 if (ahci_broken_devslp(pdev))
1775 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1778 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1779 pdev->device == 0xa235 &&
1780 pdev->revision < 0x30)
1781 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1783 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1784 hpriv->irq_handler = ahci_thunderx_irq_handler;
1787 /* save initial config */
1788 ahci_pci_save_initial_config(pdev, hpriv);
1791 * If platform firmware failed to enable ports, try to enable
1794 ahci_intel_pcs_quirk(pdev, hpriv);
1797 if (hpriv->cap & HOST_CAP_NCQ) {
1798 pi.flags |= ATA_FLAG_NCQ;
1800 * Auto-activate optimization is supposed to be
1801 * supported on all AHCI controllers indicating NCQ
1802 * capability, but it seems to be broken on some
1803 * chipsets including NVIDIAs.
1805 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1806 pi.flags |= ATA_FLAG_FPDMA_AA;
1809 * All AHCI controllers should be forward-compatible
1810 * with the new auxiliary field. This code should be
1811 * conditionalized if any buggy AHCI controllers are
1814 pi.flags |= ATA_FLAG_FPDMA_AUX;
1817 if (hpriv->cap & HOST_CAP_PMP)
1818 pi.flags |= ATA_FLAG_PMP;
1820 ahci_set_em_messages(hpriv, &pi);
1822 if (ahci_broken_system_poweroff(pdev)) {
1823 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1824 dev_info(&pdev->dev,
1825 "quirky BIOS, skipping spindown on poweroff\n");
1828 if (ahci_broken_lpm(pdev)) {
1829 pi.flags |= ATA_FLAG_NO_LPM;
1830 dev_warn(&pdev->dev,
1831 "BIOS update required for Link Power Management support\n");
1834 if (ahci_broken_suspend(pdev)) {
1835 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1836 dev_warn(&pdev->dev,
1837 "BIOS update required for suspend/resume\n");
1840 if (ahci_broken_online(pdev)) {
1841 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1842 dev_info(&pdev->dev,
1843 "online status unreliable, applying workaround\n");
1847 /* Acer SA5-271 workaround modifies private_data */
1848 acer_sa5_271_workaround(hpriv, pdev);
1850 /* CAP.NP sometimes indicate the index of the last enabled
1851 * port, at other times, that of the last possible port, so
1852 * determining the maximum port number requires looking at
1853 * both CAP.NP and port_map.
1855 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1857 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1860 host->private_data = hpriv;
1862 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1863 /* legacy intx interrupts */
1866 hpriv->irq = pci_irq_vector(pdev, 0);
1868 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1869 host->flags |= ATA_HOST_PARALLEL_SCAN;
1871 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1873 if (pi.flags & ATA_FLAG_EM)
1874 ahci_reset_em(host);
1876 for (i = 0; i < host->n_ports; i++) {
1877 struct ata_port *ap = host->ports[i];
1879 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1880 ata_port_pbar_desc(ap, ahci_pci_bar,
1881 0x100 + ap->port_no * 0x80, "port");
1883 /* set enclosure management message type */
1884 if (ap->flags & ATA_FLAG_EM)
1885 ap->em_message_type = hpriv->em_msg_type;
1887 ahci_update_initial_lpm_policy(ap, hpriv);
1889 /* disabled/not-implemented port */
1890 if (!(hpriv->port_map & (1 << i)))
1891 ap->ops = &ata_dummy_port_ops;
1894 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1895 ahci_p5wdh_workaround(host);
1897 /* apply gtf filter quirk */
1898 ahci_gtf_filter_workaround(host);
1900 /* initialize adapter */
1901 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1905 rc = ahci_reset_controller(host);
1909 ahci_pci_init_controller(host);
1910 ahci_pci_print_info(host);
1912 pci_set_master(pdev);
1914 rc = ahci_host_activate(host, &ahci_sht);
1918 pm_runtime_put_noidle(&pdev->dev);
1922 static void ahci_shutdown_one(struct pci_dev *pdev)
1924 ata_pci_shutdown_one(pdev);
1927 static void ahci_remove_one(struct pci_dev *pdev)
1929 sysfs_remove_file_from_group(&pdev->dev.kobj,
1930 &dev_attr_remapped_nvme.attr,
1932 pm_runtime_get_noresume(&pdev->dev);
1933 ata_pci_remove_one(pdev);
1936 module_pci_driver(ahci_pci_driver);
1938 MODULE_AUTHOR("Jeff Garzik");
1939 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1940 MODULE_LICENSE("GPL");
1941 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1942 MODULE_VERSION(DRV_VERSION);