2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 static const struct ata_port_info ahci_port_info[] = {
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_ops,
115 [board_ahci_ign_iferr] = {
116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
117 .flags = AHCI_FLAG_COMMON,
118 .pio_mask = ATA_PIO4,
119 .udma_mask = ATA_UDMA6,
120 .port_ops = &ahci_ops,
122 [board_ahci_nosntf] = {
123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
129 [board_ahci_yes_fbs] = {
130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
137 [board_ahci_mcp65] = {
138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
145 [board_ahci_mcp77] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
152 [board_ahci_mcp89] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
167 [board_ahci_sb600] = {
168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_pmp_retry_srst_ops,
176 [board_ahci_sb700] = { /* for SB700 and SB800 */
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_pmp_retry_srst_ops,
183 [board_ahci_vt8251] = {
184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_vt8251_ops,
192 static const struct pci_device_id ahci_pci_tbl[] = {
194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
285 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
286 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
287 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
291 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
295 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
296 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
297 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
298 /* JMicron 362B and 362C have an AHCI function with IDE class code */
299 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
300 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
303 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
304 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
305 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
306 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
307 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
308 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
309 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
312 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
313 /* AMD is using RAID class only for ahci controllers */
314 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
315 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
318 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
319 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
322 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
323 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
324 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
325 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
326 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
327 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
328 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
329 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
330 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
331 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
332 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
333 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
334 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
335 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
336 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
337 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
343 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
344 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
345 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
346 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
347 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
348 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
349 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
359 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
360 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
361 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
362 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
363 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
364 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
365 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
371 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
372 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
373 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
374 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
375 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
376 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
383 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
384 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
385 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
386 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
387 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
388 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
389 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
395 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
396 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
397 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
398 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
399 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
400 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
401 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
409 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
410 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
412 /* ST Microelectronics */
413 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
416 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
417 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
418 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
419 .class = PCI_CLASS_STORAGE_SATA_AHCI,
420 .class_mask = 0xffffff,
421 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
422 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
423 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
424 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
425 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
426 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
427 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
428 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
429 .driver_data = board_ahci_yes_fbs },
432 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
435 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
436 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
437 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
438 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
441 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
443 /* Generic, PCI class code for AHCI */
444 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
445 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
447 { } /* terminate list */
451 static struct pci_driver ahci_pci_driver = {
453 .id_table = ahci_pci_tbl,
454 .probe = ahci_init_one,
455 .remove = ata_pci_remove_one,
457 .suspend = ahci_pci_device_suspend,
458 .resume = ahci_pci_device_resume,
462 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
463 static int marvell_enable;
465 static int marvell_enable = 1;
467 module_param(marvell_enable, int, 0644);
468 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
471 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
472 struct ahci_host_priv *hpriv)
474 unsigned int force_port_map = 0;
475 unsigned int mask_port_map = 0;
477 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
478 dev_info(&pdev->dev, "JMB361 has only one port\n");
483 * Temporary Marvell 6145 hack: PATA port presence
484 * is asserted through the standard AHCI port
485 * presence register, as bit 4 (counting from 0)
487 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
488 if (pdev->device == 0x6121)
493 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
496 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
500 static int ahci_pci_reset_controller(struct ata_host *host)
502 struct pci_dev *pdev = to_pci_dev(host->dev);
504 ahci_reset_controller(host);
506 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
507 struct ahci_host_priv *hpriv = host->private_data;
511 pci_read_config_word(pdev, 0x92, &tmp16);
512 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
513 tmp16 |= hpriv->port_map;
514 pci_write_config_word(pdev, 0x92, tmp16);
521 static void ahci_pci_init_controller(struct ata_host *host)
523 struct ahci_host_priv *hpriv = host->private_data;
524 struct pci_dev *pdev = to_pci_dev(host->dev);
525 void __iomem *port_mmio;
529 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
530 if (pdev->device == 0x6121)
534 port_mmio = __ahci_port_base(host, mv);
536 writel(0, port_mmio + PORT_IRQ_MASK);
539 tmp = readl(port_mmio + PORT_IRQ_STAT);
540 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
542 writel(tmp, port_mmio + PORT_IRQ_STAT);
545 ahci_init_controller(host);
548 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
549 unsigned long deadline)
551 struct ata_port *ap = link->ap;
557 ahci_stop_engine(ap);
559 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
560 deadline, &online, NULL);
562 ahci_start_engine(ap);
564 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
566 /* vt8251 doesn't clear BSY on signature FIS reception,
567 * request follow-up softreset.
569 return online ? -EAGAIN : rc;
572 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline)
575 struct ata_port *ap = link->ap;
576 struct ahci_port_priv *pp = ap->private_data;
577 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
578 struct ata_taskfile tf;
582 ahci_stop_engine(ap);
584 /* clear D2H reception area to properly wait for D2H FIS */
585 ata_tf_init(link->device, &tf);
587 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
589 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
590 deadline, &online, NULL);
592 ahci_start_engine(ap);
594 /* The pseudo configuration device on SIMG4726 attached to
595 * ASUS P5W-DH Deluxe doesn't send signature FIS after
596 * hardreset if no device is attached to the first downstream
597 * port && the pseudo device locks up on SRST w/ PMP==0. To
598 * work around this, wait for !BSY only briefly. If BSY isn't
599 * cleared, perform CLO and proceed to IDENTIFY (achieved by
600 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
602 * Wait for two seconds. Devices attached to downstream port
603 * which can't process the following IDENTIFY after this will
604 * have to be reset again. For most cases, this should
605 * suffice while making probing snappish enough.
608 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
611 ahci_kick_engine(ap);
617 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
619 struct ata_host *host = pci_get_drvdata(pdev);
620 struct ahci_host_priv *hpriv = host->private_data;
621 void __iomem *mmio = hpriv->mmio;
624 if (mesg.event & PM_EVENT_SUSPEND &&
625 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
627 "BIOS update required for suspend/resume\n");
631 if (mesg.event & PM_EVENT_SLEEP) {
632 /* AHCI spec rev1.1 section 8.3.3:
633 * Software must disable interrupts prior to requesting a
634 * transition of the HBA to D3 state.
636 ctl = readl(mmio + HOST_CTL);
638 writel(ctl, mmio + HOST_CTL);
639 readl(mmio + HOST_CTL); /* flush */
642 return ata_pci_device_suspend(pdev, mesg);
645 static int ahci_pci_device_resume(struct pci_dev *pdev)
647 struct ata_host *host = pci_get_drvdata(pdev);
650 rc = ata_pci_device_do_resume(pdev);
654 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
655 rc = ahci_pci_reset_controller(host);
659 ahci_pci_init_controller(host);
662 ata_host_resume(host);
668 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
673 * If the device fixup already set the dma_mask to some non-standard
674 * value, don't extend it here. This happens on STA2X11, for example.
676 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
680 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
681 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
683 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
686 "64-bit DMA enable failed\n");
691 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
693 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
696 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
699 "32-bit consistent DMA enable failed\n");
706 static void ahci_pci_print_info(struct ata_host *host)
708 struct pci_dev *pdev = to_pci_dev(host->dev);
712 pci_read_config_word(pdev, 0x0a, &cc);
713 if (cc == PCI_CLASS_STORAGE_IDE)
715 else if (cc == PCI_CLASS_STORAGE_SATA)
717 else if (cc == PCI_CLASS_STORAGE_RAID)
722 ahci_print_info(host, scc_s);
725 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
726 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
727 * support PMP and the 4726 either directly exports the device
728 * attached to the first downstream port or acts as a hardware storage
729 * controller and emulate a single ATA device (can be RAID 0/1 or some
730 * other configuration).
732 * When there's no device attached to the first downstream port of the
733 * 4726, "Config Disk" appears, which is a pseudo ATA device to
734 * configure the 4726. However, ATA emulation of the device is very
735 * lame. It doesn't send signature D2H Reg FIS after the initial
736 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
738 * The following function works around the problem by always using
739 * hardreset on the port and not depending on receiving signature FIS
740 * afterward. If signature FIS isn't received soon, ATA class is
741 * assumed without follow-up softreset.
743 static void ahci_p5wdh_workaround(struct ata_host *host)
745 static struct dmi_system_id sysids[] = {
747 .ident = "P5W DH Deluxe",
749 DMI_MATCH(DMI_SYS_VENDOR,
750 "ASUSTEK COMPUTER INC"),
751 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
756 struct pci_dev *pdev = to_pci_dev(host->dev);
758 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
759 dmi_check_system(sysids)) {
760 struct ata_port *ap = host->ports[1];
763 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
765 ap->ops = &ahci_p5wdh_ops;
766 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
770 /* only some SB600 ahci controllers can do 64bit DMA */
771 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
773 static const struct dmi_system_id sysids[] = {
775 * The oldest version known to be broken is 0901 and
776 * working is 1501 which was released on 2007-10-26.
777 * Enable 64bit DMA on 1501 and anything newer.
779 * Please read bko#9412 for more info.
782 .ident = "ASUS M2A-VM",
784 DMI_MATCH(DMI_BOARD_VENDOR,
785 "ASUSTeK Computer INC."),
786 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
788 .driver_data = "20071026", /* yyyymmdd */
791 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
794 * BIOS versions earlier than 1.5 had the Manufacturer DMI
795 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
796 * This spelling mistake was fixed in BIOS version 1.5, so
797 * 1.5 and later have the Manufacturer as
798 * "MICRO-STAR INTERNATIONAL CO.,LTD".
799 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
801 * BIOS versions earlier than 1.9 had a Board Product Name
802 * DMI field of "MS-7376". This was changed to be
803 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
804 * match on DMI_BOARD_NAME of "MS-7376".
807 .ident = "MSI K9A2 Platinum",
809 DMI_MATCH(DMI_BOARD_VENDOR,
811 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
815 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
818 * This board also had the typo mentioned above in the
819 * Manufacturer DMI field (fixed in BIOS version 1.5), so
820 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
823 .ident = "MSI K9AGM2",
825 DMI_MATCH(DMI_BOARD_VENDOR,
827 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
831 * All BIOS versions for the Asus M3A support 64bit DMA.
832 * (all release versions from 0301 to 1206 were tested)
837 DMI_MATCH(DMI_BOARD_VENDOR,
838 "ASUSTeK Computer INC."),
839 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
844 const struct dmi_system_id *match;
845 int year, month, date;
848 match = dmi_first_match(sysids);
849 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
853 if (!match->driver_data)
856 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
857 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
859 if (strcmp(buf, match->driver_data) >= 0)
863 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
869 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
873 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
875 static const struct dmi_system_id broken_systems[] = {
877 .ident = "HP Compaq nx6310",
879 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
880 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
882 /* PCI slot number of the controller */
883 .driver_data = (void *)0x1FUL,
886 .ident = "HP Compaq 6720s",
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
891 /* PCI slot number of the controller */
892 .driver_data = (void *)0x1FUL,
895 { } /* terminate list */
897 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
900 unsigned long slot = (unsigned long)dmi->driver_data;
901 /* apply the quirk only to on-board controllers */
902 return slot == PCI_SLOT(pdev->devfn);
908 static bool ahci_broken_suspend(struct pci_dev *pdev)
910 static const struct dmi_system_id sysids[] = {
912 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
913 * to the harddisk doesn't become online after
914 * resuming from STR. Warn and fail suspend.
916 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
918 * Use dates instead of versions to match as HP is
919 * apparently recycling both product and version
922 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
927 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
928 DMI_MATCH(DMI_PRODUCT_NAME,
929 "HP Pavilion dv4 Notebook PC"),
931 .driver_data = "20090105", /* F.30 */
936 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
937 DMI_MATCH(DMI_PRODUCT_NAME,
938 "HP Pavilion dv5 Notebook PC"),
940 .driver_data = "20090506", /* F.16 */
945 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
946 DMI_MATCH(DMI_PRODUCT_NAME,
947 "HP Pavilion dv6 Notebook PC"),
949 .driver_data = "20090423", /* F.21 */
954 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
955 DMI_MATCH(DMI_PRODUCT_NAME,
956 "HP HDX18 Notebook PC"),
958 .driver_data = "20090430", /* F.23 */
961 * Acer eMachines G725 has the same problem. BIOS
962 * V1.03 is known to be broken. V3.04 is known to
963 * work. Between, there are V1.06, V2.06 and V3.03
964 * that we don't have much idea about. For now,
965 * blacklist anything older than V3.04.
967 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
972 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
975 .driver_data = "20091216", /* V3.04 */
977 { } /* terminate list */
979 const struct dmi_system_id *dmi = dmi_first_match(sysids);
980 int year, month, date;
983 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
986 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
987 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
989 return strcmp(buf, dmi->driver_data) < 0;
992 static bool ahci_broken_online(struct pci_dev *pdev)
994 #define ENCODE_BUSDEVFN(bus, slot, func) \
995 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
996 static const struct dmi_system_id sysids[] = {
998 * There are several gigabyte boards which use
999 * SIMG5723s configured as hardware RAID. Certain
1000 * 5723 firmware revisions shipped there keep the link
1001 * online but fail to answer properly to SRST or
1002 * IDENTIFY when no device is attached downstream
1003 * causing libata to retry quite a few times leading
1004 * to excessive detection delay.
1006 * As these firmwares respond to the second reset try
1007 * with invalid device signature, considering unknown
1008 * sig as offline works around the problem acceptably.
1011 .ident = "EP45-DQ6",
1013 DMI_MATCH(DMI_BOARD_VENDOR,
1014 "Gigabyte Technology Co., Ltd."),
1015 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1017 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1020 .ident = "EP45-DS5",
1022 DMI_MATCH(DMI_BOARD_VENDOR,
1023 "Gigabyte Technology Co., Ltd."),
1024 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1026 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1028 { } /* terminate list */
1030 #undef ENCODE_BUSDEVFN
1031 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1037 val = (unsigned long)dmi->driver_data;
1039 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1042 #ifdef CONFIG_ATA_ACPI
1043 static void ahci_gtf_filter_workaround(struct ata_host *host)
1045 static const struct dmi_system_id sysids[] = {
1047 * Aspire 3810T issues a bunch of SATA enable commands
1048 * via _GTF including an invalid one and one which is
1049 * rejected by the device. Among the successful ones
1050 * is FPDMA non-zero offset enable which when enabled
1051 * only on the drive side leads to NCQ command
1052 * failures. Filter it out.
1055 .ident = "Aspire 3810T",
1057 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1058 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1060 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1064 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1065 unsigned int filter;
1071 filter = (unsigned long)dmi->driver_data;
1072 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1073 filter, dmi->ident);
1075 for (i = 0; i < host->n_ports; i++) {
1076 struct ata_port *ap = host->ports[i];
1077 struct ata_link *link;
1078 struct ata_device *dev;
1080 ata_for_each_link(link, ap, EDGE)
1081 ata_for_each_dev(dev, link, ALL)
1082 dev->gtf_filter |= filter;
1086 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1090 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1093 unsigned int maxvec;
1095 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1096 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1098 if ((rc == maxvec) || (rc == 1))
1101 * Assume that advantage of multipe MSIs is negated,
1102 * so fallback to single MSI mode to save resources
1104 pci_disable_msi(pdev);
1105 if (!pci_enable_msi(pdev))
1115 * ahci_host_activate - start AHCI host, request IRQs and register it
1116 * @host: target ATA host
1117 * @irq: base IRQ number to request
1118 * @n_msis: number of MSIs allocated for this host
1119 * @irq_handler: irq_handler used when requesting IRQs
1120 * @irq_flags: irq_flags used when requesting IRQs
1122 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1123 * when multiple MSIs were allocated. That is one MSI per port, starting
1127 * Inherited from calling layer (may sleep).
1130 * 0 on success, -errno otherwise.
1132 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1136 /* Sharing Last Message among several ports is not supported */
1137 if (n_msis < host->n_ports)
1140 rc = ata_host_start(host);
1144 for (i = 0; i < host->n_ports; i++) {
1145 struct ahci_port_priv *pp = host->ports[i]->private_data;
1147 rc = devm_request_threaded_irq(host->dev,
1148 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1149 pp->irq_desc, host->ports[i]);
1154 for (i = 0; i < host->n_ports; i++)
1155 ata_port_desc(host->ports[i], "irq %d", irq + i);
1157 rc = ata_host_register(host, &ahci_sht);
1159 goto out_free_all_irqs;
1166 for (i--; i >= 0; i--)
1167 devm_free_irq(host->dev, irq + i, host->ports[i]);
1172 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1174 unsigned int board_id = ent->driver_data;
1175 struct ata_port_info pi = ahci_port_info[board_id];
1176 const struct ata_port_info *ppi[] = { &pi, NULL };
1177 struct device *dev = &pdev->dev;
1178 struct ahci_host_priv *hpriv;
1179 struct ata_host *host;
1180 int n_ports, n_msis, i, rc;
1181 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1185 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1187 ata_print_version_once(&pdev->dev, DRV_VERSION);
1189 /* The AHCI driver can only drive the SATA ports, the PATA driver
1190 can drive them all so if both drivers are selected make sure
1191 AHCI stays out of the way */
1192 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1196 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1197 * ahci, use ata_generic instead.
1199 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1200 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1201 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1202 pdev->subsystem_device == 0xcb89)
1205 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1206 * At the moment, we can only use the AHCI mode. Let the users know
1207 * that for SAS drives they're out of luck.
1209 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1210 dev_info(&pdev->dev,
1211 "PDC42819 can only drive SATA devices with this driver\n");
1213 /* Both Connext and Enmotus devices use non-standard BARs */
1214 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1215 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1216 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1217 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1219 /* acquire resources */
1220 rc = pcim_enable_device(pdev);
1224 /* AHCI controllers often implement SFF compatible interface.
1225 * Grab all PCI BARs just in case.
1227 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1229 pcim_pin_device(pdev);
1233 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1234 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1237 /* ICH6s share the same PCI ID for both piix and ahci
1238 * modes. Enabling ahci mode while MAP indicates
1239 * combined mode is a bad idea. Yield to ata_piix.
1241 pci_read_config_byte(pdev, ICH_MAP, &map);
1243 dev_info(&pdev->dev,
1244 "controller is in combined mode, can't enable AHCI mode\n");
1249 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1252 hpriv->flags |= (unsigned long)pi.private_data;
1254 /* MCP65 revision A1 and A2 can't do MSI */
1255 if (board_id == board_ahci_mcp65 &&
1256 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1257 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1259 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1260 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1261 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1263 /* only some SB600s can do 64bit DMA */
1264 if (ahci_sb600_enable_64bit(pdev))
1265 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1267 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1269 n_msis = ahci_init_interrupts(pdev, hpriv);
1271 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1273 /* save initial config */
1274 ahci_pci_save_initial_config(pdev, hpriv);
1277 if (hpriv->cap & HOST_CAP_NCQ) {
1278 pi.flags |= ATA_FLAG_NCQ;
1280 * Auto-activate optimization is supposed to be
1281 * supported on all AHCI controllers indicating NCQ
1282 * capability, but it seems to be broken on some
1283 * chipsets including NVIDIAs.
1285 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1286 pi.flags |= ATA_FLAG_FPDMA_AA;
1289 if (hpriv->cap & HOST_CAP_PMP)
1290 pi.flags |= ATA_FLAG_PMP;
1292 ahci_set_em_messages(hpriv, &pi);
1294 if (ahci_broken_system_poweroff(pdev)) {
1295 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1296 dev_info(&pdev->dev,
1297 "quirky BIOS, skipping spindown on poweroff\n");
1300 if (ahci_broken_suspend(pdev)) {
1301 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1302 dev_warn(&pdev->dev,
1303 "BIOS update required for suspend/resume\n");
1306 if (ahci_broken_online(pdev)) {
1307 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1308 dev_info(&pdev->dev,
1309 "online status unreliable, applying workaround\n");
1312 /* CAP.NP sometimes indicate the index of the last enabled
1313 * port, at other times, that of the last possible port, so
1314 * determining the maximum port number requires looking at
1315 * both CAP.NP and port_map.
1317 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1319 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1322 host->private_data = hpriv;
1324 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1325 host->flags |= ATA_HOST_PARALLEL_SCAN;
1327 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1329 if (pi.flags & ATA_FLAG_EM)
1330 ahci_reset_em(host);
1332 for (i = 0; i < host->n_ports; i++) {
1333 struct ata_port *ap = host->ports[i];
1335 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1336 ata_port_pbar_desc(ap, ahci_pci_bar,
1337 0x100 + ap->port_no * 0x80, "port");
1339 /* set enclosure management message type */
1340 if (ap->flags & ATA_FLAG_EM)
1341 ap->em_message_type = hpriv->em_msg_type;
1344 /* disabled/not-implemented port */
1345 if (!(hpriv->port_map & (1 << i)))
1346 ap->ops = &ata_dummy_port_ops;
1349 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1350 ahci_p5wdh_workaround(host);
1352 /* apply gtf filter quirk */
1353 ahci_gtf_filter_workaround(host);
1355 /* initialize adapter */
1356 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1360 rc = ahci_pci_reset_controller(host);
1364 ahci_pci_init_controller(host);
1365 ahci_pci_print_info(host);
1367 pci_set_master(pdev);
1369 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1370 return ahci_host_activate(host, pdev->irq, n_msis);
1372 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1376 module_pci_driver(ahci_pci_driver);
1378 MODULE_AUTHOR("Jeff Garzik");
1379 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1380 MODULE_LICENSE("GPL");
1381 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1382 MODULE_VERSION(DRV_VERSION);