2 * Copyright (C) 2016 Broadcom
3 * Author: Jayachandran C <jchandra@broadcom.com>
4 * Copyright (C) 2016 Semihalf
5 * Author: Tomasz Nowicki <tn@semihalf.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2, as
9 * published by the Free Software Foundation (the "GPL").
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License version 2 (GPLv2) for more details.
16 * You should have received a copy of the GNU General Public License
17 * version 2 (GPLv2) along with this source code.
20 #define pr_fmt(fmt) "ACPI: " fmt
22 #include <linux/kernel.h>
23 #include <linux/pci.h>
24 #include <linux/pci-acpi.h>
25 #include <linux/pci-ecam.h>
27 /* Structure to hold entries from the MCFG table */
29 struct list_head list;
36 #ifdef CONFIG_PCI_QUIRKS
38 char oem_id[ACPI_OEM_ID_SIZE + 1];
39 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
42 struct resource bus_range;
43 struct pci_ecam_ops *ops;
44 struct resource cfgres;
47 #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
48 ((end) - (start) + 1), \
50 #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
52 static struct mcfg_fixup mcfg_quirks[] = {
53 /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
55 #define AL_ECAM(table_id, rev, seg, ops) \
56 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
58 AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
59 AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
60 AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
61 AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
62 AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
63 AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
64 AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
65 AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
67 #define QCOM_ECAM32(seg) \
68 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
79 #define HISI_QUAD_DOM(table_id, seg, ops) \
80 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
81 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
82 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
83 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
85 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
86 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
87 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
88 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
89 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
90 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
92 #define THUNDER_PEM_RES(addr, node) \
93 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
95 #define THUNDER_PEM_QUIRK(rev, node) \
96 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
97 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
98 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
99 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
100 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
101 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
102 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
103 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
104 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
105 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
106 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
107 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
109 #define THUNDER_ECAM_QUIRK(rev, seg) \
110 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
111 &pci_thunder_ecam_ops }
114 THUNDER_PEM_QUIRK(1, 0),
115 THUNDER_PEM_QUIRK(1, 1),
116 THUNDER_ECAM_QUIRK(1, 10),
119 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
120 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
121 THUNDER_ECAM_QUIRK(2, 0),
122 THUNDER_ECAM_QUIRK(2, 1),
123 THUNDER_ECAM_QUIRK(2, 2),
124 THUNDER_ECAM_QUIRK(2, 3),
125 THUNDER_ECAM_QUIRK(2, 10),
126 THUNDER_ECAM_QUIRK(2, 11),
127 THUNDER_ECAM_QUIRK(2, 12),
128 THUNDER_ECAM_QUIRK(2, 13),
130 #define XGENE_V1_ECAM_MCFG(rev, seg) \
131 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
132 &xgene_v1_pcie_ecam_ops }
134 #define XGENE_V2_ECAM_MCFG(rev, seg) \
135 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
136 &xgene_v2_pcie_ecam_ops }
138 /* X-Gene SoC with v1 PCIe controller */
139 XGENE_V1_ECAM_MCFG(1, 0),
140 XGENE_V1_ECAM_MCFG(1, 1),
141 XGENE_V1_ECAM_MCFG(1, 2),
142 XGENE_V1_ECAM_MCFG(1, 3),
143 XGENE_V1_ECAM_MCFG(1, 4),
144 XGENE_V1_ECAM_MCFG(2, 0),
145 XGENE_V1_ECAM_MCFG(2, 1),
146 XGENE_V1_ECAM_MCFG(2, 2),
147 XGENE_V1_ECAM_MCFG(2, 3),
148 XGENE_V1_ECAM_MCFG(2, 4),
149 /* X-Gene SoC with v2.1 PCIe controller */
150 XGENE_V2_ECAM_MCFG(3, 0),
151 XGENE_V2_ECAM_MCFG(3, 1),
152 /* X-Gene SoC with v2.2 PCIe controller */
153 XGENE_V2_ECAM_MCFG(4, 0),
154 XGENE_V2_ECAM_MCFG(4, 1),
155 XGENE_V2_ECAM_MCFG(4, 2),
158 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
159 static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
160 static u32 mcfg_oem_revision;
162 static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
163 struct resource *bus_range)
165 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
166 !memcmp(f->oem_table_id, mcfg_oem_table_id,
167 ACPI_OEM_TABLE_ID_SIZE) &&
168 f->oem_revision == mcfg_oem_revision &&
169 f->segment == segment &&
170 resource_contains(&f->bus_range, bus_range))
177 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
178 struct resource *cfgres,
179 struct pci_ecam_ops **ecam_ops)
181 #ifdef CONFIG_PCI_QUIRKS
182 u16 segment = root->segment;
183 struct resource *bus_range = &root->secondary;
184 struct mcfg_fixup *f;
187 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
188 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
193 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
194 cfgres, bus_range, *ecam_ops);
201 /* List to save MCFG entries */
202 static LIST_HEAD(pci_mcfg_list);
204 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
205 struct pci_ecam_ops **ecam_ops)
207 struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
208 struct resource *bus_res = &root->secondary;
209 u16 seg = root->segment;
210 struct mcfg_entry *e;
213 /* Use address from _CBA if present, otherwise lookup MCFG */
218 * We expect the range in bus_res in the coverage of MCFG bus range.
220 list_for_each_entry(e, &pci_mcfg_list, list) {
221 if (e->segment == seg && e->bus_start <= bus_res->start &&
222 e->bus_end >= bus_res->end) {
223 root->mcfg_addr = e->addr;
229 memset(&res, 0, sizeof(res));
230 if (root->mcfg_addr) {
231 res.start = root->mcfg_addr + (bus_res->start << 20);
232 res.end = res.start + (resource_size(bus_res) << 20) - 1;
233 res.flags = IORESOURCE_MEM;
237 * Allow quirks to override default ECAM ops and CFG resource
238 * range. This may even fabricate a CFG resource range in case
239 * MCFG does not have it. Invalid CFG start address means MCFG
240 * firmware bug or we need another quirk in array.
242 pci_mcfg_apply_quirks(root, &res, &ops);
251 static __init int pci_mcfg_parse(struct acpi_table_header *header)
253 struct acpi_table_mcfg *mcfg;
254 struct acpi_mcfg_allocation *mptr;
255 struct mcfg_entry *e, *arr;
258 if (header->length < sizeof(struct acpi_table_mcfg))
261 n = (header->length - sizeof(struct acpi_table_mcfg)) /
262 sizeof(struct acpi_mcfg_allocation);
263 mcfg = (struct acpi_table_mcfg *)header;
264 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
266 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
270 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
271 e->segment = mptr->pci_segment;
272 e->addr = mptr->address;
273 e->bus_start = mptr->start_bus_number;
274 e->bus_end = mptr->end_bus_number;
275 list_add(&e->list, &pci_mcfg_list);
278 #ifdef CONFIG_PCI_QUIRKS
279 /* Save MCFG IDs and revision for quirks matching */
280 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
281 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
282 mcfg_oem_revision = header->oem_revision;
285 pr_info("MCFG table detected, %d entries\n", n);
289 /* Interface called by ACPI - parse and save MCFG table */
290 void __init pci_mmcfg_late_init(void)
292 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
294 pr_err("Failed to parse MCFG (%d)\n", err);