1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(c) 2018 Intel Corporation. All rights reserved.
4 * Intel specific definitions for NVDIMM Firmware Interface Table - NFIT
9 #define ND_INTEL_SMART 1
11 #define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID (1 << 5)
12 #define ND_INTEL_SMART_SHUTDOWN_VALID (1 << 10)
14 struct nd_intel_smart {
24 u16 media_temperature;
38 extern const struct nvdimm_security_ops *intel_security_ops;
40 #define ND_INTEL_STATUS_SIZE 4
41 #define ND_INTEL_PASSPHRASE_SIZE 32
43 #define ND_INTEL_STATUS_NOT_SUPPORTED 1
44 #define ND_INTEL_STATUS_RETRY 5
45 #define ND_INTEL_STATUS_NOT_READY 9
46 #define ND_INTEL_STATUS_INVALID_STATE 10
47 #define ND_INTEL_STATUS_INVALID_PASS 11
48 #define ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED 0x10007
49 #define ND_INTEL_STATUS_OQUERY_INPROGRESS 0x10007
50 #define ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR 0x20007
52 #define ND_INTEL_SEC_STATE_ENABLED 0x02
53 #define ND_INTEL_SEC_STATE_LOCKED 0x04
54 #define ND_INTEL_SEC_STATE_FROZEN 0x08
55 #define ND_INTEL_SEC_STATE_PLIMIT 0x10
56 #define ND_INTEL_SEC_STATE_UNSUPPORTED 0x20
57 #define ND_INTEL_SEC_STATE_OVERWRITE 0x40
59 #define ND_INTEL_SEC_ESTATE_ENABLED 0x01
60 #define ND_INTEL_SEC_ESTATE_PLIMIT 0x02
62 struct nd_intel_get_security_state {
70 struct nd_intel_set_passphrase {
71 u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
72 u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
76 struct nd_intel_unlock_unit {
77 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
81 struct nd_intel_disable_passphrase {
82 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
86 struct nd_intel_freeze_lock {
90 struct nd_intel_secure_erase {
91 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
95 struct nd_intel_overwrite {
96 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
100 struct nd_intel_query_overwrite {
104 struct nd_intel_set_master_passphrase {
105 u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
106 u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
110 struct nd_intel_master_secure_erase {
111 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
115 #define ND_INTEL_FWA_IDLE 0
116 #define ND_INTEL_FWA_ARMED 1
117 #define ND_INTEL_FWA_BUSY 2
119 #define ND_INTEL_DIMM_FWA_NONE 0
120 #define ND_INTEL_DIMM_FWA_NOTSTAGED 1
121 #define ND_INTEL_DIMM_FWA_SUCCESS 2
122 #define ND_INTEL_DIMM_FWA_NEEDRESET 3
123 #define ND_INTEL_DIMM_FWA_MEDIAFAILED 4
124 #define ND_INTEL_DIMM_FWA_ABORT 5
125 #define ND_INTEL_DIMM_FWA_NOTSUPP 6
126 #define ND_INTEL_DIMM_FWA_ERROR 7
128 struct nd_intel_fw_activate_dimminfo {
135 #define ND_INTEL_DIMM_FWA_ARM 1
136 #define ND_INTEL_DIMM_FWA_DISARM 0
138 struct nd_intel_fw_activate_arm {
143 /* Root device command payloads */
144 #define ND_INTEL_BUS_FWA_CAP_FWQUIESCE (1 << 0)
145 #define ND_INTEL_BUS_FWA_CAP_OSQUIESCE (1 << 1)
146 #define ND_INTEL_BUS_FWA_CAP_RESET (1 << 2)
148 struct nd_intel_bus_fw_activate_businfo {
159 #define ND_INTEL_BUS_FWA_STATUS_NOARM (6 | 1 << 16)
160 #define ND_INTEL_BUS_FWA_STATUS_BUSY (6 | 2 << 16)
161 #define ND_INTEL_BUS_FWA_STATUS_NOFW (6 | 3 << 16)
162 #define ND_INTEL_BUS_FWA_STATUS_TMO (6 | 4 << 16)
163 #define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16)
164 #define ND_INTEL_BUS_FWA_STATUS_ABORT (6 | 6 << 16)
166 #define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0)
167 #define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1)
168 struct nd_intel_bus_fw_activate {
173 extern const struct nvdimm_fw_ops *intel_fw_ops;
174 extern const struct nvdimm_bus_fw_ops *intel_bus_fw_ops;